Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T98,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13828	0	0
DisabledNoTrigBkwd_A	2147483647	850869	0	0
DisabledNoTrigFwd_A	2147483647	1553295563	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13828	0	0
T23	41893	0	0	0
T29	1901828	0	0	0
T35	0	459	0	0
T75	74829	0	0	0
T76	182029	0	0	0
T77	386129	0	0	0
T78	526026	0	0	0
T81	318981	0	0	0
T82	19519	0	0	0
T83	1872	0	0	0
T98	3144	855	0	0
T99	566755	0	0	0
T108	964902	0	0	0
T109	148389	0	0	0
T110	874218	0	0	0
T111	67028	0	0	0
T114	265616	0	0	0
T210	4482	1019	0	0
T211	6732	762	0	0
T212	0	437	0	0
T213	0	951	0	0
T214	0	961	0	0
T215	0	258	0	0
T216	0	873	0	0
T217	0	250	0	0
T218	0	982	0	0
T219	0	576	0	0
T220	0	436	0	0
T221	0	504	0	0
T222	0	677	0	0
T223	0	582	0	0
T224	0	1029	0	0
T225	0	843	0	0
T226	0	1092	0	0
T227	0	282	0	0
T228	414340	0	0	0
T229	81990	0	0	0
T230	1790614	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	850869	0	0
T1	734680	4183	0	0
T2	555808	1709	0	0
T3	663856	572	0	0
T4	832632	573	0	0
T5	0	11	0	0
T7	0	10	0	0
T11	0	1811	0	0
T13	0	6	0	0
T14	0	435	0	0
T15	238128	42	0	0
T16	1100908	497	0	0
T17	104080	0	0	0
T18	1303280	3326	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	45	0	0
T28	0	20	0	0
T30	0	17	0	0
T44	0	60	0	0
T45	0	68	0	0
T46	0	26	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1553295563	0	0
T1	734680	1360502	0	0
T2	555808	418148	0	0
T3	663856	333726	0	0
T4	832632	264280	0	0
T15	238128	181733	0	0
T16	1100908	1398259	0	0
T17	104080	82647	0	0
T18	1303280	1423987	0	0
T19	169492	113329	0	0
T20	25976	11122	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T35,T221
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696786910	1982	0	0
DisabledNoTrigBkwd_A	696786910	219790	0	0
DisabledNoTrigFwd_A	696786910	390453926	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1982	0	0
T23	41893	0	0	0
T35	0	459	0	0
T75	74829	0	0	0
T76	182029	0	0	0
T81	318981	0	0	0
T108	964902	0	0	0
T109	148389	0	0	0
T110	874218	0	0	0
T111	67028	0	0	0
T210	4482	1019	0	0
T221	0	504	0	0
T228	414340	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	219790	0	0
T1	183670	1570	0	0
T2	138952	2	0	0
T3	165964	373	0	0
T4	208158	0	0	0
T11	0	1810	0	0
T15	59532	42	0	0
T16	275227	254	0	0
T17	26020	0	0	0
T18	325820	3179	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	10	0	0
T28	0	16	0	0
T30	0	17	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	390453926	0	0
T1	183670	72413	0	0
T2	138952	138730	0	0
T3	165964	2112	0	0
T4	208158	208148	0	0
T15	59532	3290	0	0
T16	275227	76744	0	0
T17	26020	24875	0	0
T18	325820	483627	0	0
T19	42373	33854	0	0
T20	6494	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T212,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696786910	5018	0	0
DisabledNoTrigBkwd_A	696786910	163743	0	0
DisabledNoTrigFwd_A	696786910	436100206	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	5018	0	0
T29	950914	0	0	0
T77	386129	0	0	0
T78	263013	0	0	0
T82	19519	0	0	0
T83	1872	0	0	0
T98	3144	855	0	0
T99	566755	0	0	0
T211	3366	0	0	0
T212	0	437	0	0
T215	0	258	0	0
T216	0	873	0	0
T217	0	250	0	0
T219	0	576	0	0
T222	0	677	0	0
T226	0	1092	0	0
T229	81990	0	0	0
T230	895307	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	163743	0	0
T1	183670	34	0	0
T2	138952	3	0	0
T3	165964	3	0	0
T4	208158	282	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	14	0	0
T17	26020	0	0	0
T18	325820	69	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	29	0	0
T28	0	2	0	0
T45	0	47	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	436100206	0	0
T1	183670	181313	0	0
T2	138952	138527	0	0
T3	165964	164358	0	0
T4	208158	2319	0	0
T15	59532	59481	0	0
T16	275227	783348	0	0
T17	26020	25924	0	0
T18	325820	338577	0	0
T19	42373	36605	0	0
T20	6494	6427	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T214,T223
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696786910	2587	0	0
DisabledNoTrigBkwd_A	696786910	217567	0	0
DisabledNoTrigFwd_A	696786910	379885695	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	2587	0	0
T29	950914	0	0	0
T32	144248	0	0	0
T78	263013	0	0	0
T84	30270	0	0	0
T85	219078	0	0	0
T86	761540	0	0	0
T114	265616	0	0	0
T124	106748	0	0	0
T211	3366	762	0	0
T214	0	961	0	0
T223	0	582	0	0
T227	0	282	0	0
T230	895307	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	217567	0	0
T1	183670	2161	0	0
T2	138952	1704	0	0
T3	165964	196	0	0
T4	208158	291	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	116	0	0
T17	26020	0	0	0
T18	325820	67	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	6	0	0
T28	0	1	0	0
T44	0	60	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	379885695	0	0
T1	183670	959414	0	0
T2	138952	2777	0	0
T3	165964	2143	0	0
T4	208158	24945	0	0
T15	59532	59481	0	0
T16	275227	222417	0	0
T17	26020	5924	0	0
T18	325820	307272	0	0
T19	42373	4124	0	0
T20	6494	590	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T213,T218,T220
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696786910	4241	0	0
DisabledNoTrigBkwd_A	696786910	249769	0	0
DisabledNoTrigFwd_A	696786910	346855736	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	4241	0	0
T48	23318	0	0	0
T65	61024	0	0	0
T66	125367	0	0	0
T67	513524	0	0	0
T68	34376	0	0	0
T69	60358	0	0	0
T70	464001	0	0	0
T71	115378	0	0	0
T72	406359	0	0	0
T213	4889	951	0	0
T218	0	982	0	0
T220	0	436	0	0
T224	0	1029	0	0
T225	0	843	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	249769	0	0
T1	183670	418	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	10	0	0
T7	0	10	0	0
T13	0	6	0	0
T14	0	435	0	0
T15	59532	0	0	0
T16	275227	113	0	0
T17	26020	0	0	0
T18	325820	11	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	21	0	0
T46	0	26	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	346855736	0	0
T1	183670	147362	0	0
T2	138952	138114	0	0
T3	165964	165113	0	0
T4	208158	28868	0	0
T15	59532	59481	0	0
T16	275227	315750	0	0
T17	26020	25924	0	0
T18	325820	294511	0	0
T19	42373	38746	0	0
T20	6494	3523	0	0