Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T17
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T16,T17
1	1	1	Covered	T1,T16,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T17
0	1	Covered	T16,T21,T22
1	0	Covered	T18,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T17
1	0	Covered	T25,T26,T27
1	1	Covered	T16,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T16,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T16

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T16,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T16,T17
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T16,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T2,T30,T21
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T1,T2,T23
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T16,T31
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T16
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T16,T17
TimeoutSt->Phase0St	172	Covered	T16,T18,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T30,T21
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T16,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1152	0	0
CheckAccumTrig0_A	2147483647	2261	0	0
CheckAccumTrig1_A	2147483647	91	0	0
CheckClr_A	2147483647	993	0	0
CheckEn_A	2147483647	1200592587	0	0
CheckPhase0_A	2147483647	2547	0	0
CheckPhase1_A	2147483647	2490	0	0
CheckPhase2_A	2147483647	2442	0	0
CheckPhase3_A	2147483647	2397	0	0
CheckTimeout0_A	2147483647	4598	0	0
CheckTimeoutSt1_A	2147483647	549522	0	0
CheckTimeoutSt2_A	2147483647	4245	0	0
CheckTimeoutStTrig_A	2147483647	247	0	0
ErrorStAllEscAsserted_A	2147483647	6391	0	0
ErrorStIsTerminal_A	2147483647	5311	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1152	0	0
T8	178604	258	0	0
T9	0	256	0	0
T10	0	251	0	0
T33	0	121	0	0
T34	0	266	0	0
T35	4692	0	0	0
T36	2957240	0	0	0
T37	1970304	0	0	0
T38	1959656	0	0	0
T39	2220752	0	0	0
T40	315444	0	0	0
T41	907220	0	0	0
T42	398288	0	0	0
T43	180756	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2261	0	0
T1	734680	13	0	0
T2	555808	8	0	0
T3	663856	3	0	0
T4	832632	2	0	0
T5	0	2	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	238128	1	0	0
T16	1100908	15	0	0
T17	104080	0	0	0
T18	1303280	11	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	8	0	0
T28	0	8	0	0
T30	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	91	0	0
T4	208158	0	0	0
T5	103778	0	0	0
T6	831032	0	0	0
T11	247263	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T23	41893	1	0	0
T24	0	1	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T44	229433	0	0	0
T47	0	2	0	0
T48	23318	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	61024	0	0	0
T66	125367	0	0	0
T67	513524	0	0	0
T68	34376	0	0	0
T69	60358	0	0	0
T70	464001	0	0	0
T71	115378	0	0	0
T72	406359	0	0	0
T73	64294	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	993	0	0
T1	551010	5	0	0
T2	555808	6	0	0
T3	663856	0	0	0
T4	832632	0	0	0
T11	247263	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	238128	0	0	0
T16	1100908	9	0	0
T17	104080	0	0	0
T18	1303280	6	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	6	0	0
T22	0	1	0	0
T23	0	3	0	0
T25	0	8	0	0
T28	0	6	0	0
T30	0	1	0	0
T31	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1200592587	0	0
T1	734680	2086085	0	0
T2	555808	285521	0	0
T3	663856	171491	0	0
T4	832632	253189	0	0
T15	238128	181730	0	0
T16	1100908	975213	0	0
T17	104080	82644	0	0
T18	1303280	1257212	0	0
T19	169492	113326	0	0
T20	25976	11120	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2547	0	0
T1	734680	13	0	0
T2	555808	8	0	0
T3	663856	3	0	0
T4	832632	2	0	0
T5	0	2	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	238128	1	0	0
T16	1100908	15	0	0
T17	104080	0	0	0
T18	1303280	12	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	9	0	0
T28	0	7	0	0
T30	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2490	0	0
T1	734680	13	0	0
T2	555808	6	0	0
T3	663856	3	0	0
T4	832632	2	0	0
T5	0	2	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	238128	1	0	0
T16	1100908	15	0	0
T17	104080	0	0	0
T18	1303280	12	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	7	0	0
T28	0	7	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T79	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2442	0	0
T1	734680	12	0	0
T2	555808	5	0	0
T3	663856	3	0	0
T4	832632	2	0	0
T5	0	2	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	238128	1	0	0
T16	1100908	15	0	0
T17	104080	0	0	0
T18	1303280	12	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	7	0	0
T28	0	7	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T79	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T1	734680	11	0	0
T2	555808	5	0	0
T3	663856	3	0	0
T4	832632	2	0	0
T5	0	2	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	238128	1	0	0
T16	1100908	13	0	0
T17	104080	0	0	0
T18	1303280	12	0	0
T19	169492	0	0	0
T20	25976	0	0	0
T21	0	7	0	0
T28	0	7	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T79	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4598	0	0
T1	551010	5	0	0
T2	416856	0	0	0
T3	497892	0	0	0
T4	832632	0	0	0
T11	247263	0	0	0
T15	178596	0	0	0
T16	1100908	75	0	0
T17	104080	3	0	0
T18	1303280	8	0	0
T19	169492	0	0	0
T20	25976	5	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	6	0	0
T25	0	55	0	0
T28	18604	1	0	0
T29	0	1	0	0
T30	16075	0	0	0
T31	0	4	0	0
T32	0	3	0	0
T44	229433	0	0	0
T46	0	5	0	0
T76	0	5	0	0
T77	0	46	0	0
T80	0	6	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	549522	0	0
T1	551010	339	0	0
T2	416856	0	0	0
T3	497892	0	0	0
T4	832632	0	0	0
T11	247263	0	0	0
T15	178596	0	0	0
T16	1100908	8811	0	0
T17	104080	356	0	0
T18	1303280	612	0	0
T19	169492	0	0	0
T20	25976	594	0	0
T21	0	178	0	0
T22	0	49	0	0
T23	0	1681	0	0
T24	0	36	0	0
T25	0	2447	0	0
T28	18604	50	0	0
T29	0	46	0	0
T30	16075	0	0	0
T31	0	768	0	0
T44	229433	0	0	0
T46	0	180	0	0
T76	0	288	0	0
T77	0	9297	0	0
T80	0	534	0	0
T81	0	32	0	0
T82	0	169	0	0
T83	0	39	0	0
T84	0	384	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4245	0	0
T1	183670	2	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	832632	0	0	0
T11	741789	0	0	0
T15	59532	0	0	0
T16	1100908	42	0	0
T17	104080	3	0	0
T18	1303280	6	0	0
T19	169492	0	0	0
T20	25976	4	0	0
T21	0	1	0	0
T23	0	2	0	0
T25	0	59	0	0
T28	55812	1	0	0
T29	0	1	0	0
T30	48225	0	0	0
T31	0	1	0	0
T44	688299	0	0	0
T46	0	5	0	0
T76	0	4	0	0
T77	0	30	0	0
T80	0	6	0	0
T81	0	1	0	0
T82	0	3	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	216	0	0
T87	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	247	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	41893	3	0	0
T25	360323	1	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	123581	1	0	0
T44	229433	0	0	0
T48	0	2	0	0
T49	0	3	0	0
T55	0	1	0	0
T56	0	1	0	0
T68	0	1	0	0
T73	0	2	0	0
T76	0	1	0	0
T77	386129	4	0	0
T87	0	5	0	0
T88	11973	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	5	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	5502	0	0	0
T95	73395	0	0	0
T96	75520	0	0	0
T97	153762	0	0	0
T98	3144	0	0	0
T99	566755	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6391	0	0
T8	178604	1401	0	0
T9	0	1402	0	0
T10	0	1361	0	0
T33	0	766	0	0
T34	0	1461	0	0
T35	4692	0	0	0
T36	2957240	0	0	0
T37	1970304	0	0	0
T38	1959656	0	0	0
T39	2220752	0	0	0
T40	315444	0	0	0
T41	907220	0	0	0
T42	398288	0	0	0
T43	180756	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5311	0	0
T8	178604	1161	0	0
T9	0	1162	0	0
T10	0	1121	0	0
T33	0	646	0	0
T34	0	1221	0	0
T35	4692	0	0	0
T36	2957240	0	0	0
T37	1970304	0	0	0
T38	1959656	0	0	0
T39	2220752	0	0	0
T40	315444	0	0	0
T41	907220	0	0	0
T42	398288	0	0	0
T43	180756	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	734680	734640	0	0
T2	555808	555784	0	0
T3	663856	663832	0	0
T4	832632	832592	0	0
T15	238128	237924	0	0
T16	1100908	1100864	0	0
T17	104080	103696	0	0
T18	1303280	1303148	0	0
T19	169492	169120	0	0
T20	25976	25708	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	734680	734640	0	0
T2	555808	555784	0	0
T3	663856	663832	0	0
T4	832632	832592	0	0
T15	238128	237924	0	0
T16	1100908	1100864	0	0
T17	104080	103696	0	0
T18	1303280	1303148	0	0
T19	169492	169120	0	0
T20	25976	25708	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T17
1	0	1	Covered	T1,T3,T16
1	1	0	Covered	T1,T16,T17
1	1	1	Covered	T1,T16,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T17
0	1	Covered	T23,T77,T89
1	0	Covered	T23,T57,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T57,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T17
1	0	Not Covered
1	1	Covered	T23,T77,T89

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T3,T28

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T45,T46

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T5,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T16,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T28

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T16,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T16,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T51,T56
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T87,T91
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T23,T56
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T100,T101
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T16,T17
TimeoutSt->Phase0St	172	Covered	T23,T77,T89

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T77,T89
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T51,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T87,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T23,T56
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T16,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696786910	265	0	0
CheckAccumTrig0_A	696786910	483	0	0
CheckAccumTrig1_A	696786910	15	0	0
CheckClr_A	696786910	210	0	0
CheckEn_A	696479178	294338242	0	0
CheckPhase0_A	696786910	554	0	0
CheckPhase1_A	696786910	543	0	0
CheckPhase2_A	696786910	536	0	0
CheckPhase3_A	696786910	529	0	0
CheckTimeout0_A	696786910	1035	0	0
CheckTimeoutSt1_A	696786910	129386	0	0
CheckTimeoutSt2_A	696786910	953	0	0
CheckTimeoutStTrig_A	696786910	64	0	0
ErrorStAllEscAsserted_A	696786910	1546	0	0
ErrorStIsTerminal_A	696786910	1276	0	0
EscStateOut_A	696477628	696409030	0	0
u_state_regs_A	696786910	696605023	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	265	0	0
T8	44651	80	0	0
T9	0	55	0	0
T10	0	45	0	0
T33	0	18	0	0
T34	0	67	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	483	0	0
T1	183670	2	0	0
T2	138952	5	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	15	0	0
T23	41893	1	0	0
T24	122195	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T75	74829	0	0	0
T76	182029	0	0	0
T81	318981	0	0	0
T100	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	964902	0	0	0
T109	148389	0	0	0
T110	874218	0	0	0
T111	67028	0	0	0
T112	298825	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	210	0	0
T2	138952	4	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T15	59532	0	0	0
T16	275227	1	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T23	0	3	0	0
T25	0	1	0	0
T28	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T46	0	5	0	0
T77	0	3	0	0
T78	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696479178	294338242	0	0
T1	183670	946474	0	0
T2	138952	2777	0	0
T3	165964	2143	0	0
T4	208158	13854	0	0
T15	59532	59480	0	0
T16	275227	222416	0	0
T17	26020	5924	0	0
T18	325820	307272	0	0
T19	42373	4124	0	0
T20	6494	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	554	0	0
T1	183670	2	0	0
T2	138952	5	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	543	0	0
T1	183670	2	0	0
T2	138952	4	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	536	0	0
T1	183670	2	0	0
T2	138952	3	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	529	0	0
T1	183670	2	0	0
T2	138952	3	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T5	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1035	0	0
T1	183670	1	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	3	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	1	0	0
T23	0	5	0	0
T25	0	32	0	0
T31	0	1	0	0
T46	0	5	0	0
T77	0	10	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	129386	0	0
T1	183670	75	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	520	0	0
T17	26020	356	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	135	0	0
T23	0	844	0	0
T25	0	1242	0	0
T31	0	457	0	0
T46	0	180	0	0
T77	0	2431	0	0
T80	0	106	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	953	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	3	0	0
T17	26020	3	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	1	0	0
T23	0	2	0	0
T25	0	32	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	0	1	0	0
T44	229433	0	0	0
T46	0	5	0	0
T77	0	8	0	0
T80	0	1	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	64	0	0
T23	41893	2	0	0
T24	122195	0	0	0
T49	0	2	0	0
T53	0	2	0	0
T68	0	1	0	0
T73	0	2	0	0
T75	74829	0	0	0
T76	182029	0	0	0
T77	0	2	0	0
T81	318981	0	0	0
T87	0	1	0	0
T89	0	1	0	0
T91	0	4	0	0
T108	964902	0	0	0
T109	148389	0	0	0
T110	874218	0	0	0
T111	67028	0	0	0
T112	298825	0	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1546	0	0
T8	44651	359	0	0
T9	0	340	0	0
T10	0	328	0	0
T33	0	171	0	0
T34	0	348	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1276	0	0
T8	44651	299	0	0
T9	0	280	0	0
T10	0	268	0	0
T33	0	141	0	0
T34	0	288	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696477628	696409030	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	696605023	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T17
1	0	1	Covered	T3,T16,T19
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T1,T16,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T20
0	1	Covered	T16,T21,T22
1	0	Covered	T18,T24,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T24,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T18
1	0	Covered	T26
1	1	Covered	T16,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T18,T46

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T2,T18,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T18,T28
1	Covered	T1,T3,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T16,T30,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T16,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T3,T15
Phase3St	233	Covered	T1,T3,T15
TerminalSt	249	Covered	T1,T3,T15
TimeoutSt	159	Covered	T1,T16,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T16,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T30,T32
Phase1St->Phase2St	215	Covered	T1,T3,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T114,T53
Phase2St->Phase3St	233	Covered	T1,T3,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T114,T47
Phase3St->TerminalSt	249	Covered	T1,T3,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T16,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T16,T20
TimeoutSt->Phase0St	172	Covered	T16,T18,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T49
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T30,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T114,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T114,T47
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696786910	317	0	0
CheckAccumTrig0_A	696786910	793	0	0
CheckAccumTrig1_A	696786910	35	0	0
CheckClr_A	696786910	369	0	0
CheckEn_A	696479178	295424472	0	0
CheckPhase0_A	696786910	870	0	0
CheckPhase1_A	696786910	851	0	0
CheckPhase2_A	696786910	831	0	0
CheckPhase3_A	696786910	811	0	0
CheckTimeout0_A	696786910	914	0	0
CheckTimeoutSt1_A	696786910	116489	0	0
CheckTimeoutSt2_A	696786910	809	0	0
CheckTimeoutStTrig_A	696786910	65	0	0
ErrorStAllEscAsserted_A	696786910	1657	0	0
ErrorStIsTerminal_A	696786910	1387	0	0
EscStateOut_A	696477628	696409030	0	0
u_state_regs_A	696786910	696605023	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	317	0	0
T8	44651	51	0	0
T9	0	64	0	0
T10	0	82	0	0
T33	0	43	0	0
T34	0	77	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	793	0	0
T1	183670	5	0	0
T2	138952	1	0	0
T3	165964	1	0	0
T4	208158	0	0	0
T11	0	1	0	0
T15	59532	1	0	0
T16	275227	7	0	0
T17	26020	0	0	0
T18	325820	5	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	2	0	0
T28	0	4	0	0
T30	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	35	0	0
T4	208158	0	0	0
T5	103778	0	0	0
T6	831032	0	0	0
T11	247263	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T24	0	1	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T44	229433	0	0	0
T47	0	2	0	0
T51	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	369	0	0
T1	183670	2	0	0
T2	138952	1	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	5	0	0
T17	26020	0	0	0
T18	325820	4	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696479178	295424472	0	0
T1	183670	69368	0	0
T2	138952	138730	0	0
T3	165964	2112	0	0
T4	208158	208148	0	0
T15	59532	3290	0	0
T16	275227	76743	0	0
T17	26020	24874	0	0
T18	325820	330727	0	0
T19	42373	33853	0	0
T20	6494	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	870	0	0
T1	183670	5	0	0
T2	138952	1	0	0
T3	165964	1	0	0
T4	208158	0	0	0
T11	0	1	0	0
T15	59532	1	0	0
T16	275227	8	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	3	0	0
T30	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	851	0	0
T1	183670	5	0	0
T2	138952	0	0	0
T3	165964	1	0	0
T4	208158	0	0	0
T11	0	1	0	0
T15	59532	1	0	0
T16	275227	8	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	3	0	0
T30	0	1	0	0
T79	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	831	0	0
T1	183670	5	0	0
T2	138952	0	0	0
T3	165964	1	0	0
T4	208158	0	0	0
T11	0	1	0	0
T15	59532	1	0	0
T16	275227	8	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	3	0	0
T30	0	1	0	0
T79	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	811	0	0
T1	183670	5	0	0
T2	138952	0	0	0
T3	165964	1	0	0
T4	208158	0	0	0
T11	0	1	0	0
T15	59532	1	0	0
T16	275227	7	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	3	0	0
T30	0	1	0	0
T79	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	914	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	4	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	3	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T76	0	5	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	116489	0	0
T1	183670	190	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	383	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	384	0	0
T21	0	178	0	0
T22	0	49	0	0
T23	0	837	0	0
T24	0	36	0	0
T76	0	288	0	0
T80	0	41	0	0
T81	0	32	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	809	0	0
T1	183670	2	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	1	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	3	0	0
T21	0	1	0	0
T25	0	10	0	0
T76	0	4	0	0
T77	0	11	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	65	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T44	229433	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	2	0	0
T88	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1657	0	0
T8	44651	351	0	0
T9	0	366	0	0
T10	0	337	0	0
T33	0	206	0	0
T34	0	397	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1387	0	0
T8	44651	291	0	0
T9	0	306	0	0
T10	0	277	0	0
T33	0	176	0	0
T34	0	337	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696477628	696409030	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	696605023	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T18
1	0	1	Covered	T1,T3,T16
1	1	0	Covered	T1,T16,T17
1	1	1	Covered	T1,T16,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T18
0	1	Covered	T25,T31,T77
1	0	Covered	T48,T49,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T49,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T18
1	0	Covered	T25
1	1	Covered	T25,T31,T77

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T16,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T22,T115

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T3,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T16,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T16,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T48,T51
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T49,T91
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T1,T59,T116
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T16,T100
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T16,T18
TimeoutSt->Phase0St	172	Covered	T25,T31,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T31,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T48,T51
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T49,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T59,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T16,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T16,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696786910	304	0	0
CheckAccumTrig0_A	696786910	468	0	0
CheckAccumTrig1_A	696786910	16	0	0
CheckClr_A	696786910	192	0	0
CheckEn_A	696479178	348422104	0	0
CheckPhase0_A	696786910	522	0	0
CheckPhase1_A	696786910	512	0	0
CheckPhase2_A	696786910	504	0	0
CheckPhase3_A	696786910	493	0	0
CheckTimeout0_A	696786910	1448	0	0
CheckTimeoutSt1_A	696786910	164396	0	0
CheckTimeoutSt2_A	696786910	1374	0	0
CheckTimeoutStTrig_A	696786910	51	0	0
ErrorStAllEscAsserted_A	696786910	1593	0	0
ErrorStIsTerminal_A	696786910	1323	0	0
EscStateOut_A	696477628	696409030	0	0
u_state_regs_A	696786910	696605023	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	304	0	0
T8	44651	66	0	0
T9	0	63	0	0
T10	0	59	0	0
T33	0	49	0	0
T34	0	67	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	468	0	0
T1	183670	3	0	0
T2	138952	2	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	3	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	5	0	0
T28	0	2	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	16	0	0
T48	23318	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	61024	0	0	0
T66	125367	0	0	0
T67	513524	0	0	0
T68	34376	0	0	0
T69	60358	0	0	0
T70	464001	0	0	0
T71	115378	0	0	0
T72	406359	0	0	0
T73	64294	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	192	0	0
T1	183670	2	0	0
T2	138952	1	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T11	0	1	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	4	0	0
T25	0	7	0	0
T28	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696479178	348422104	0	0
T1	183670	128219	0	0
T2	138952	5900	0	0
T3	165964	2123	0	0
T4	208158	2319	0	0
T15	59532	59480	0	0
T16	275227	360306	0	0
T17	26020	25923	0	0
T18	325820	338575	0	0
T19	42373	36604	0	0
T20	6494	6426	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	522	0	0
T1	183670	3	0	0
T2	138952	2	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	3	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	5	0	0
T28	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	512	0	0
T1	183670	3	0	0
T2	138952	2	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	3	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	504	0	0
T1	183670	2	0	0
T2	138952	2	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	3	0	0
T17	26020	0	0	0
T18	325820	3	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	493	0	0
T1	183670	1	0	0
T2	138952	2	0	0
T3	165964	1	0	0
T4	208158	1	0	0
T11	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	3	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T21	0	3	0	0
T28	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1448	0	0
T1	183670	1	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	38	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T25	0	18	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T77	0	12	0	0
T80	0	4	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	164396	0	0
T1	183670	74	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T15	59532	0	0	0
T16	275227	4029	0	0
T17	26020	0	0	0
T18	325820	480	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T25	0	1032	0	0
T28	0	50	0	0
T29	0	46	0	0
T31	0	268	0	0
T77	0	2343	0	0
T80	0	387	0	0
T84	0	177	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1374	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	38	0	0
T17	26020	0	0	0
T18	325820	6	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T25	0	17	0	0
T28	18604	1	0	0
T29	0	1	0	0
T30	16075	0	0	0
T44	229433	0	0	0
T77	0	11	0	0
T80	0	4	0	0
T84	0	2	0	0
T86	0	216	0	0
T87	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	51	0	0
T25	360323	1	0	0
T31	123581	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T77	386129	1	0	0
T87	0	2	0	0
T88	11973	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	5502	0	0	0
T95	73395	0	0	0
T96	75520	0	0	0
T97	153762	0	0	0
T98	3144	0	0	0
T99	566755	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1593	0	0
T8	44651	337	0	0
T9	0	327	0	0
T10	0	390	0	0
T33	0	192	0	0
T34	0	347	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1323	0	0
T8	44651	277	0	0
T9	0	267	0	0
T10	0	330	0	0
T33	0	162	0	0
T34	0	287	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696477628	696409030	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	696605023	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T16,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T18
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T16,T17
1	1	1	Covered	T16,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T25,T31
1	0	Covered	T32,T87,T117

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T87,T117

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T27
1	1	Covered	T16,T25,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T18
1	Covered	T18,T28,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T18
1	Covered	T1,T115,T76

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T28
1	Covered	T1,T16,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T18
1	Covered	T5,T14,T46

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T16,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T16,T18,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T16,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T16,T18
Phase1St	198	Covered	T1,T16,T18
Phase2St	215	Covered	T1,T16,T18
Phase3St	233	Covered	T1,T16,T18
TerminalSt	249	Covered	T1,T16,T18
TimeoutSt	159	Covered	T16,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T16,T18
IdleSt->TimeoutSt	159	Covered	T16,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T99,T118
Phase0St->Phase1St	198	Covered	T1,T16,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T91,T117
Phase1St->Phase2St	215	Covered	T1,T16,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T41,T119
Phase2St->Phase3St	233	Covered	T1,T16,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T56,T120,T121
Phase3St->TerminalSt	249	Covered	T1,T16,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T16,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T18,T20
TimeoutSt->Phase0St	172	Covered	T16,T25,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T25,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T99,T118,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T16,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T16,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T91,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T16,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T16,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T41,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T16,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T16,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T56,T120,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T16,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T16,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696786910	266	0	0
CheckAccumTrig0_A	696786910	517	0	0
CheckAccumTrig1_A	696786910	25	0	0
CheckClr_A	696786910	222	0	0
CheckEn_A	696479178	262407769	0	0
CheckPhase0_A	696786910	601	0	0
CheckPhase1_A	696786910	584	0	0
CheckPhase2_A	696786910	571	0	0
CheckPhase3_A	696786910	564	0	0
CheckTimeout0_A	696786910	1201	0	0
CheckTimeoutSt1_A	696786910	139251	0	0
CheckTimeoutSt2_A	696786910	1109	0	0
CheckTimeoutStTrig_A	696786910	67	0	0
ErrorStAllEscAsserted_A	696786910	1595	0	0
ErrorStIsTerminal_A	696786910	1325	0	0
EscStateOut_A	696477628	696409030	0	0
u_state_regs_A	696786910	696605023	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	266	0	0
T8	44651	61	0	0
T9	0	74	0	0
T10	0	65	0	0
T33	0	11	0	0
T34	0	55	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	517	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	1	0	0
T7	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	25	0	0
T32	144248	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T84	30270	0	0	0
T86	761540	0	0	0
T87	927426	2	0	0
T89	25037	0	0	0
T117	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	106748	0	0	0
T125	64234	0	0	0
T126	386471	0	0	0
T127	30720	0	0	0
T128	27241	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	222	0	0
T1	183670	1	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T13	0	2	0	0
T15	59532	0	0	0
T16	275227	1	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T31	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	1	0	0
T99	0	3	0	0
T109	0	1	0	0
T129	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696479178	262407769	0	0
T1	183670	942024	0	0
T2	138952	138114	0	0
T3	165964	165113	0	0
T4	208158	28868	0	0
T15	59532	59480	0	0
T16	275227	315748	0	0
T17	26020	25923	0	0
T18	325820	280638	0	0
T19	42373	38745	0	0
T20	6494	3522	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	601	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	1	0	0
T7	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	584	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	1	0	0
T7	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	571	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	1	0	0
T7	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	564	0	0
T1	183670	3	0	0
T2	138952	0	0	0
T3	165964	0	0	0
T4	208158	0	0	0
T5	0	1	0	0
T7	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	59532	0	0	0
T16	275227	2	0	0
T17	26020	0	0	0
T18	325820	2	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T28	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1201	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	30	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	1	0	0
T25	0	5	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T44	229433	0	0	0
T77	0	24	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	139251	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	3879	0	0
T17	26020	0	0	0
T18	325820	132	0	0
T19	42373	0	0	0
T20	6494	75	0	0
T25	0	173	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	0	43	0	0
T32	0	226	0	0
T44	229433	0	0	0
T77	0	4523	0	0
T82	0	169	0	0
T83	0	39	0	0
T84	0	207	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1109	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	29	0	0
T17	26020	0	0	0
T18	325820	1	0	0
T19	42373	0	0	0
T20	6494	1	0	0
T25	0	4	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T44	229433	0	0	0
T77	0	22	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	67	0	0
T4	208158	0	0	0
T11	247263	0	0	0
T16	275227	1	0	0
T17	26020	0	0	0
T18	325820	0	0	0
T19	42373	0	0	0
T20	6494	0	0	0
T25	0	1	0	0
T28	18604	0	0	0
T30	16075	0	0	0
T31	0	1	0	0
T44	229433	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T77	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1595	0	0
T8	44651	354	0	0
T9	0	369	0	0
T10	0	306	0	0
T33	0	197	0	0
T34	0	369	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	1325	0	0
T8	44651	294	0	0
T9	0	309	0	0
T10	0	246	0	0
T33	0	167	0	0
T34	0	309	0	0
T35	1173	0	0	0
T36	739310	0	0	0
T37	492576	0	0	0
T38	489914	0	0	0
T39	555188	0	0	0
T40	78861	0	0	0
T41	226805	0	0	0
T42	99572	0	0	0
T43	45189	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696477628	696409030	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696786910	696605023	0	0
T1	183670	183660	0	0
T2	138952	138946	0	0
T3	165964	165958	0	0
T4	208158	208148	0	0
T15	59532	59481	0	0
T16	275227	275216	0	0
T17	26020	25924	0	0
T18	325820	325787	0	0
T19	42373	42280	0	0
T20	6494	6427	0	0