Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	55556	1			T1	7		T4	823		T8	10
class_i[0x1]	62868	1			T4	2915		T8	10		T6	664
class_i[0x2]	48835	1			T1	8		T4	258		T8	6
class_i[0x3]	57899	1			T2	6		T4	3		T8	8

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	53519	1			T1	2		T2	2		T4	1288
alert[0x1]	56822	1			T1	4		T2	1		T4	1021
alert[0x2]	56200	1			T1	6		T2	2		T4	805
alert[0x3]	58617	1			T1	3		T2	1		T4	885

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

224886

1

T1

9

T4

3999

T8

34

esc_ping_fail

272

1

T1

6

T2

6

T9

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	53437	1			T1	1		T4	1288		T8	5
esc_integrity_fail	alert[0x1]	56757	1			T1	2		T4	1021		T8	21
esc_integrity_fail	alert[0x2]	56134	1			T1	4		T4	805		T8	4
esc_integrity_fail	alert[0x3]	58558	1			T1	2		T4	885		T8	4
esc_ping_fail	alert[0x0]	82	1			T1	1		T2	2		T9	3
esc_ping_fail	alert[0x1]	65	1			T1	2		T2	1		T9	2
esc_ping_fail	alert[0x2]	66	1			T1	2		T2	2		T9	2
esc_ping_fail	alert[0x3]	59	1			T1	1		T2	1		T9	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	55490	1			T1	1		T4	823		T8	10
esc_integrity_fail	class_i[0x1]	62795	1			T4	2915		T8	10		T6	664
esc_integrity_fail	class_i[0x2]	48794	1			T1	8		T4	258		T8	6
esc_integrity_fail	class_i[0x3]	57807	1			T4	3		T8	8		T5	2
esc_ping_fail	class_i[0x0]	66	1			T1	6		T9	5		T61	1
esc_ping_fail	class_i[0x1]	73	1			T9	2		T61	3		T79	1
esc_ping_fail	class_i[0x2]	41	1			T233	1		T292	2		T223	1
esc_ping_fail	class_i[0x3]	92	1			T2	6		T9	1		T79	4