Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	655319166	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	655319166	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	655319166	655160807	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	655319166	655160807	0	0
tb.dut.EdnKnownO_A	0	0	655319166	655160807	0	0
tb.dut.EscPKnownO_A	0	0	655319166	655160807	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	655319166	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	655319166	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	655319166	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	655319166	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	655319166	70	0	0
tb.dut.IrqAKnownO_A	0	0	655319166	655160807	0	0
tb.dut.IrqBKnownO_A	0	0	655319166	655160807	0	0
tb.dut.IrqCKnownO_A	0	0	655319166	655160807	0	0
tb.dut.IrqDKnownO_A	0	0	655319166	655160807	0	0
tb.dut.TlAReadyKnownO_A	0	0	655319166	655160807	0	0
tb.dut.TlDValidKnownO_A	0	0	655319166	655160807	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	681895836	2935633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	681895836	18252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	681895836	16064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	681895836	16758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	681895836	17871	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	681895836	18541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	681895836	17611	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	681895836	17243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	681895836	17204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	681895836	17509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	681895836	17496	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	681895836	17594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	681895836	16558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	681895836	16220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	681895836	16845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	681895836	17896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	681895836	16179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	681895836	16940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	681895836	17197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	681895836	18865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	681895836	17263	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	681895836	17563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	681895836	15921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	681895836	16385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	681895836	16343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	681895836	17380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	681895836	16306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	681895836	16911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	681895836	17186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	681895836	17979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	681895836	17681	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	681895836	16747	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	681895836	17570	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	681895836	17191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	681895836	16628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	681895836	18162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	681895836	16025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	681895836	16185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	681895836	16306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	681895836	17217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	681895836	17148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	681895836	16951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	681895836	16319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	681895836	16280	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	681895836	18117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	681895836	16454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	681895836	16626	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	681895836	16091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	681895836	16182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	681895836	16955	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	681895836	18409	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	681895836	16621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	681895836	19684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	681895836	17509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	681895836	17017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	681895836	18499	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	681895836	16879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	681895836	17174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	681895836	17314	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	681895836	16759	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	681895836	18794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	681895836	16057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	681895836	17520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	681895836	18166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	681895836	19078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	681895836	16079	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	681895836	18025	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	681895836	16943	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	681895836	16139	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	681895836	17663	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	681895836	32381	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	681895836	17009	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	681895836	18558	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	681895836	16134	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	681895836	17287	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	681895836	17636	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	681895836	17213	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	681895836	17293	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	681895836	16380	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	655319166	5381	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	655319166	213993	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	655319166	324860126	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	655319166	238	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	655319166	890	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	655319166	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	655319166	467	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	655084264	228279553	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	655319166	979	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	655319166	955	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	655319166	927	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	655319166	911	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	655319166	1656	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	655319166	126935	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	655319166	1545	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	655319166	64	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655319166	1274	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	655319166	1064	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	655082827	655014024	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	655319166	655160807	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	655319166	1237	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	655319166	157136	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	655319166	392112252	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	655319166	234	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	655319166	454	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	655319166	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	655319166	183	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	655084264	282300684	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	655319166	538	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	655319166	528	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	655319166	521	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	655319166	514	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	655319166	1043	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	655319166	133294	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	655319166	946	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	655319166	75	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655319166	1262	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	655319166	1052	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	655082827	655014024	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	655319166	655160807	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	655319166	1093	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	655319166	165208	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	655319166	380407835	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	655319166	243	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	655319166	454	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	655319166	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	655319166	191	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	655084264	302847664	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	655319166	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	655319166	503	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	655319166	495	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	655319166	485	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	655319166	1450	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	655319166	150797	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	655319166	1379	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	655319166	54	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655319166	1176	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	655319166	966	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	655082827	655014024	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	655319166	655160807	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	655319166	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	655319166	5641	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	655319166	189408	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	655319166	379473321	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	655319166	273	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	655319166	546	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	655319166	25	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	655319166	259	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	655084264	278983591	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	655319166	616	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	655319166	603	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	655319166	589	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	655319166	585	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	655319166	2132	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	655319166	180841	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	655319166	2045	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	655319166	60	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655319166	1265	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	655319166	1055	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	655082827	655014024	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	655319166	655160807	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	681895836	135028232	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	681895836	681259695	0	0
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