Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	64	1			T19	2		T20	1		T67	1
class_index[0x1]	75	1			T20	2		T65	2		T66	3
class_index[0x2]	54	1			T18	1		T62	1		T24	1
class_index[0x3]	60	1			T3	1		T4	1		T20	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	96	1			T3	1		T4	1		T18	1
intr_timeout_cnt[1]	57	1			T20	3		T62	1		T108	1
intr_timeout_cnt[2]	26	1			T20	1		T65	1		T74	1
intr_timeout_cnt[3]	15	1			T65	1		T70	1		T76	1
intr_timeout_cnt[4]	11	1			T24	1		T77	1		T89	1
intr_timeout_cnt[5]	8	1			T69	1		T109	1		T239	2
intr_timeout_cnt[6]	11	1			T24	1		T75	1		T77	1
intr_timeout_cnt[7]	17	1			T66	1		T222	1		T240	1
intr_timeout_cnt[8]	5	1			T89	1		T179	1		T241	1
intr_timeout_cnt[9]	7	1			T66	3		T110	1		T242	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T19	2		T67	1		T48	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T20	1		T73	1		T78	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T76	1		T235	1		T190	2
class_index[0x0]	intr_timeout_cnt[3]	2	1			T77	1		T243	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T24	1		T103	1		T244	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T245	2		T246	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T179	1		T90	1		T98	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T247	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T248	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	34	1			T71	1		T69	1		T72	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T20	2		T49	1		T50	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T65	1		T74	1		T110	1
class_index[0x1]	intr_timeout_cnt[3]	6	1			T65	1		T76	1		T249	2
class_index[0x1]	intr_timeout_cnt[4]	1	1			T250	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T69	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T77	1		T235	1		T251	1
class_index[0x1]	intr_timeout_cnt[7]	5	1			T222	1		T252	1		T235	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T66	3		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	16	1			T18	1		T71	1		T72	5
class_index[0x2]	intr_timeout_cnt[1]	14	1			T62	1		T108	1		T87	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T253	1		T254	1		T242	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T70	1		T77	1		T243	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T255	1		T104	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T109	1		T103	1		T256	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T24	1		T257	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T258	1		T245	1		T237	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T89	1		T259	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T110	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	22	1			T3	1		T4	1		T72	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T77	1		T235	1		T260	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T20	1		T253	1		T192	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T96	1		T190	1		T261	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T77	1		T89	1		T104	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T239	2		T262	2		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T75	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	4	1			T66	1		T240	1		T179	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T179	1		T241	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T242	1		T263	1		-	-