Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361325	1			T1	35		T2	43		T3	9
all_values[1]	361325	1			T1	35		T2	43		T3	9
all_values[2]	361325	1			T1	35		T2	43		T3	9
all_values[3]	361325	1			T1	35		T2	43		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718620

1

T3

15

T15

69

T16

379

auto[1]

726680

1

T1

140

T2

172

T3

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875942

1

T1

118

T2

151

T3

20

auto[1]

569358

1

T1

22

T2

21

T3

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104785	1			T15	6		T16	42		T4	432
all_values[0]	auto[0]	auto[1]	74966	1			T15	6		T16	42		T4	388
all_values[0]	auto[1]	auto[0]	106642	1			T1	26		T2	28		T3	5
all_values[0]	auto[1]	auto[1]	74932	1			T1	9		T2	15		T3	4
all_values[1]	auto[0]	auto[0]	110909	1			T3	2		T15	11		T16	49
all_values[1]	auto[0]	auto[1]	68822	1			T3	1		T15	10		T16	48
all_values[1]	auto[1]	auto[0]	112590	1			T1	32		T2	43		T3	3
all_values[1]	auto[1]	auto[1]	69004	1			T1	3		T3	3		T15	7
all_values[2]	auto[0]	auto[0]	109713	1			T3	4		T15	9		T16	47
all_values[2]	auto[0]	auto[1]	70237	1			T3	3		T15	8		T16	40
all_values[2]	auto[1]	auto[0]	111047	1			T1	29		T2	43		T3	1
all_values[2]	auto[1]	auto[1]	70328	1			T1	6		T3	1		T15	9
all_values[3]	auto[0]	auto[0]	109039	1			T3	3		T15	10		T16	57
all_values[3]	auto[0]	auto[1]	70149	1			T3	2		T15	9		T16	54
all_values[3]	auto[1]	auto[0]	111217	1			T1	31		T2	37		T3	2
all_values[3]	auto[1]	auto[1]	70920	1			T1	4		T2	6		T3	2