Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361325	1			T1	35		T2	43		T3	9
all_pins[1]	361325	1			T1	35		T2	43		T3	9
all_pins[2]	361325	1			T1	35		T2	43		T3	9
all_pins[3]	361325	1			T1	35		T2	43		T3	9

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1160116	1			T1	118		T2	151		T3	26
values[0x1]	285184	1			T1	22		T2	21		T3	10
transitions[0x0=>0x1]	189578	1			T1	22		T2	20		T3	4
transitions[0x1=>0x0]	189814	1			T1	22		T2	21		T3	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286393	1			T1	26		T2	28		T3	5
all_pins[0]	values[0x1]	74932	1			T1	9		T2	15		T3	4
all_pins[0]	transitions[0x0=>0x1]	74307	1			T1	9		T2	14		T3	3
all_pins[0]	transitions[0x1=>0x0]	70531	1			T1	4		T2	6		T3	2
all_pins[1]	values[0x0]	292321	1			T1	32		T2	43		T3	6
all_pins[1]	values[0x1]	69004	1			T1	3		T3	3		T15	7
all_pins[1]	transitions[0x0=>0x1]	37590	1			T1	3		T15	3		T16	18
all_pins[1]	transitions[0x1=>0x0]	43518	1			T1	9		T2	15		T3	1
all_pins[2]	values[0x0]	290997	1			T1	29		T2	43		T3	8
all_pins[2]	values[0x1]	70328	1			T1	6		T3	1		T15	9
all_pins[2]	transitions[0x0=>0x1]	38755	1			T1	6		T15	6		T16	22
all_pins[2]	transitions[0x1=>0x0]	37431	1			T1	3		T3	2		T15	4
all_pins[3]	values[0x0]	290405	1			T1	31		T2	37		T3	7
all_pins[3]	values[0x1]	70920	1			T1	4		T2	6		T3	2
all_pins[3]	transitions[0x0=>0x1]	38926	1			T1	4		T2	6		T3	1
all_pins[3]	transitions[0x1=>0x0]	38334	1			T1	6		T15	6		T16	23