Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T161	7		T162	7		T163	4
all_values[1]	281	1			T161	7		T162	7		T163	4
all_values[2]	281	1			T161	7		T162	7		T163	4
all_values[3]	281	1			T161	7		T162	7		T163	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T161

16

T162

15

T163

10

auto[1]

515

1

T161

12

T162

13

T163

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

433

1

T161

13

T162

7

T163

10

auto[1]

691

1

T161

15

T162

21

T163

6

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

661

1

T161

17

T162

13

T163

11

auto[1]

463

1

T161

11

T162

15

T163

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

51

1

T161

2

T162

1

T163

1

all_values[0]

auto[0]

auto[0]

auto[1]

35

1

T161

1

T162

2

T163

1

all_values[0]

auto[0]

auto[1]

auto[0]

52

1

T161

2

T162

1

T163

1

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T162

1

T334

1

T335

1

all_values[0]

auto[1]

auto[0]

auto[1]

71

1

T161

2

T163

1

T234

1

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T162

2

T334

2

T336

1

all_values[1]

auto[0]

auto[0]

auto[0]

53

1

T162

1

T234

1

T334

3

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T161

1

T234

1

T336

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T162

1

T163

2

T334

1

all_values[1]

auto[0]

auto[1]

auto[1]

38

1

T161

1

T162

1

T335

2

all_values[1]

auto[1]

auto[0]

auto[1]

56

1

T161

2

T162

1

T163

1

all_values[1]

auto[1]

auto[1]

auto[1]

68

1

T161

3

T162

3

T163

1

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T161

3

T163

3

T234

2

all_values[2]

auto[0]

auto[0]

auto[1]

26

1

T162

2

T334

1

T336

1

all_values[2]

auto[0]

auto[1]

auto[0]

60

1

T161

3

T163

1

T234

1

all_values[2]

auto[0]

auto[1]

auto[1]

23

1

T334

1

T335

1

T337

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T162

3

T234

1

T334

1

all_values[2]

auto[1]

auto[1]

auto[1]

42

1

T161

1

T162

2

T334

2

all_values[3]

auto[0]

auto[0]

auto[0]

59

1

T161

3

T162

2

T163

1

all_values[3]

auto[0]

auto[0]

auto[1]

23

1

T334

1

T338

2

T339

2

all_values[3]

auto[0]

auto[1]

auto[0]

51

1

T162

1

T163

1

T336

3

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T161

1

T334

1

T336

1

all_values[3]

auto[1]

auto[0]

auto[1]

77

1

T161

2

T162

3

T163

2

all_values[3]

auto[1]

auto[1]

auto[1]

43

1

T161

1

T162

1

T234

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal