Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87975	1			T4	493		T8	327		T5	886
accum_cnt_1000	224103	1			T16	88		T4	684		T8	552
accum_cnt_100	31365	1			T16	71		T4	131		T8	31
accum_cnt_50	78185	1			T2	5		T15	37		T16	58
accum_cnt_10	185366	1			T1	54		T2	20		T3	12
accum_cnt_0	424082	1			T1	50		T2	99		T3	20

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	266949	1			T1	26		T2	31		T3	8
class_index[0x1]	266949	1			T1	26		T2	31		T3	8
class_index[0x2]	266949	1			T1	26		T2	31		T3	8
class_index[0x3]	266949	1			T1	26		T2	31		T3	8

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20473	1			T14	577		T20	256		T35	513
class_index[0x0]	accum_cnt_1000	61546	1			T16	49		T4	14		T6	108
class_index[0x0]	accum_cnt_100	10239	1			T16	14		T4	22		T6	27
class_index[0x0]	accum_cnt_50	22932	1			T2	5		T15	18		T16	12
class_index[0x0]	accum_cnt_10	47087	1			T1	13		T2	20		T3	2
class_index[0x0]	accum_cnt_0	94177	1			T1	13		T2	6		T3	6
class_index[0x1]	accum_cnt_2000	20671	1			T5	180		T19	104		T22	633
class_index[0x1]	accum_cnt_1000	52986	1			T5	671		T6	37		T19	231
class_index[0x1]	accum_cnt_100	7184	1			T4	28		T5	36		T19	35
class_index[0x1]	accum_cnt_50	19792	1			T4	56		T5	29		T6	4
class_index[0x1]	accum_cnt_10	48467	1			T1	25		T3	2		T15	1
class_index[0x1]	accum_cnt_0	110000	1			T1	1		T2	31		T3	6
class_index[0x2]	accum_cnt_2000	21956	1			T4	334		T8	327		T5	426
class_index[0x2]	accum_cnt_1000	55527	1			T16	10		T4	518		T8	552
class_index[0x2]	accum_cnt_100	7396	1			T16	28		T4	23		T8	31
class_index[0x2]	accum_cnt_50	16354	1			T15	19		T16	26		T4	31
class_index[0x2]	accum_cnt_10	44479	1			T3	6		T15	5		T16	12
class_index[0x2]	accum_cnt_0	113801	1			T1	26		T2	31		T3	2
class_index[0x3]	accum_cnt_2000	24875	1			T4	159		T5	280		T14	547
class_index[0x3]	accum_cnt_1000	54044	1			T16	29		T4	152		T5	574
class_index[0x3]	accum_cnt_100	6546	1			T16	29		T4	58		T5	31
class_index[0x3]	accum_cnt_50	19107	1			T16	20		T4	57		T5	25
class_index[0x3]	accum_cnt_10	45333	1			T1	16		T3	2		T15	3
class_index[0x3]	accum_cnt_0	106104	1			T1	10		T2	31		T3	6