Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3110	1			T6	1		T19	54		T79	1
alert[0x1]	13780	1			T4	179		T6	4		T14	201
alert[0x2]	7462	1			T9	1		T28	2		T22	37
alert[0x3]	12834	1			T2	1		T4	3086		T86	1
alert[0x4]	15033	1			T1	1		T4	61		T20	10
alert[0x5]	7648	1			T1	1		T2	1		T4	138
alert[0x6]	5325	1			T8	1		T6	8		T9	1
alert[0x7]	2076	1			T8	2		T61	2		T22	29
alert[0x8]	5935	1			T2	2		T4	51		T8	2
alert[0x9]	5633	1			T4	368		T8	1		T19	1618
alert[0xa]	12388	1			T8	3		T61	1		T19	333
alert[0xb]	14742	1			T4	11		T14	281		T19	163
alert[0xc]	3751	1			T4	124		T14	112		T19	81
alert[0xd]	4063	1			T20	61		T189	34		T74	3
alert[0xe]	5273	1			T14	189		T61	1		T19	135
alert[0xf]	5423	1			T4	446		T14	345		T19	127
alert[0x10]	6309	1			T2	1		T4	19		T8	2
alert[0x11]	3414	1			T2	1		T4	46		T14	3
alert[0x12]	2989	1			T2	1		T5	4		T6	6
alert[0x13]	4434	1			T6	33		T19	18		T65	5
alert[0x14]	7896	1			T8	2		T19	27		T86	1
alert[0x15]	10942	1			T4	28		T8	3		T6	3
alert[0x16]	8170	1			T8	20		T19	543		T65	4
alert[0x17]	4184	1			T6	41		T9	1		T19	317
alert[0x18]	9294	1			T14	29		T19	15		T86	1
alert[0x19]	3536	1			T4	26		T6	1		T9	1
alert[0x1a]	5056	1			T1	2		T6	5		T9	1
alert[0x1b]	7365	1			T4	9		T19	20		T65	6
alert[0x1c]	8919	1			T2	1		T4	18		T19	8
alert[0x1d]	3858	1			T1	1		T6	3		T14	19
alert[0x1e]	5792	1			T14	155		T61	1		T19	2688
alert[0x1f]	8629	1			T6	7		T14	94		T65	2
alert[0x20]	4222	1			T4	289		T14	75		T19	192
alert[0x21]	13669	1			T6	2		T79	1		T80	1
alert[0x22]	2094	1			T2	1		T8	1		T6	2
alert[0x23]	4890	1			T2	2		T6	22		T14	300
alert[0x24]	4823	1			T6	13		T19	106		T80	1
alert[0x25]	4857	1			T79	1		T196	1		T24	53
alert[0x26]	4596	1			T19	112		T20	1		T86	1
alert[0x27]	6188	1			T4	74		T6	55		T14	74
alert[0x28]	7389	1			T1	1		T4	15		T19	4
alert[0x29]	10495	1			T61	1		T19	45		T22	139
alert[0x2a]	13610	1			T6	17		T19	15		T24	9
alert[0x2b]	5554	1			T2	1		T19	73		T86	1
alert[0x2c]	4194	1			T4	32		T14	22		T22	72
alert[0x2d]	5302	1			T1	1		T2	1		T4	369
alert[0x2e]	7451	1			T9	1		T13	1		T14	454
alert[0x2f]	3716	1			T8	2		T6	77		T21	4
alert[0x30]	13614	1			T6	3		T14	649		T196	1
alert[0x31]	7367	1			T8	4		T6	8		T86	1
alert[0x32]	4169	1			T14	322		T80	1		T86	1
alert[0x33]	9313	1			T4	164		T14	335		T86	1
alert[0x34]	6978	1			T65	361		T189	43		T74	1
alert[0x35]	4923	1			T6	3		T9	1		T196	1
alert[0x36]	9979	1			T4	2		T8	4		T6	7
alert[0x37]	9952	1			T9	1		T80	1		T196	1
alert[0x38]	19661	1			T2	1		T4	37		T14	1499
alert[0x39]	5078	1			T6	3		T14	368		T196	1
alert[0x3a]	5242	1			T21	2		T24	2		T69	11
alert[0x3b]	4850	1			T1	1		T6	3		T9	2
alert[0x3c]	6569	1			T4	153		T6	11		T19	199
alert[0x3d]	6872	1			T4	70		T14	18		T65	26
alert[0x3e]	4812	1			T1	2		T19	38		T86	1
alert[0x3f]	4987	1			T8	158		T14	212		T20	3
alert[0x40]	3468	1			T1	1		T2	1		T19	46

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	129410	1			T1	3		T2	15		T4	98
class_i[0x1]	142728	1			T1	3		T8	14		T6	14
class_i[0x2]	94821	1			T1	1		T4	3		T8	142
class_i[0x3]	89188	1			T1	4		T4	5714		T8	39

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

455491

1

T4

5815

T8

206

T5

4

alert_ping_fail

656

1

T1

11

T2

15

T9

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3098	1			T6	1		T19	54		T24	281
alert_integrity_fail	alert[0x1]	13767	1			T4	179		T6	4		T14	201
alert_integrity_fail	alert[0x2]	7454	1			T22	37		T24	267		T69	41
alert_integrity_fail	alert[0x3]	12820	1			T4	3086		T22	3741		T69	2
alert_integrity_fail	alert[0x4]	15025	1			T4	61		T20	10		T45	1
alert_integrity_fail	alert[0x5]	7634	1			T4	138		T21	1		T65	8
alert_integrity_fail	alert[0x6]	5302	1			T8	1		T6	8		T19	282
alert_integrity_fail	alert[0x7]	2059	1			T8	2		T22	29		T94	500
alert_integrity_fail	alert[0x8]	5917	1			T4	51		T8	2		T6	1
alert_integrity_fail	alert[0x9]	5620	1			T4	368		T8	1		T19	1618
alert_integrity_fail	alert[0xa]	12372	1			T8	3		T19	333		T22	4
alert_integrity_fail	alert[0xb]	14732	1			T4	11		T14	281		T19	163
alert_integrity_fail	alert[0xc]	3746	1			T4	124		T14	112		T19	81
alert_integrity_fail	alert[0xd]	4056	1			T20	61		T189	34		T74	3
alert_integrity_fail	alert[0xe]	5267	1			T14	189		T19	135		T45	2
alert_integrity_fail	alert[0xf]	5409	1			T4	446		T14	345		T19	127
alert_integrity_fail	alert[0x10]	6299	1			T4	19		T8	2		T14	2898
alert_integrity_fail	alert[0x11]	3407	1			T4	46		T14	3		T19	70
alert_integrity_fail	alert[0x12]	2985	1			T5	4		T6	6		T14	40
alert_integrity_fail	alert[0x13]	4425	1			T6	33		T19	18		T65	5
alert_integrity_fail	alert[0x14]	7882	1			T8	2		T19	27		T65	56
alert_integrity_fail	alert[0x15]	10933	1			T4	28		T8	3		T6	3
alert_integrity_fail	alert[0x16]	8162	1			T8	20		T19	543		T65	4
alert_integrity_fail	alert[0x17]	4172	1			T6	41		T19	317		T20	1
alert_integrity_fail	alert[0x18]	9284	1			T14	29		T19	15		T24	2
alert_integrity_fail	alert[0x19]	3524	1			T4	26		T6	1		T19	78
alert_integrity_fail	alert[0x1a]	5048	1			T6	5		T65	559		T22	578
alert_integrity_fail	alert[0x1b]	7361	1			T4	9		T19	20		T65	6
alert_integrity_fail	alert[0x1c]	8912	1			T4	18		T19	8		T65	24
alert_integrity_fail	alert[0x1d]	3849	1			T6	3		T14	19		T20	20
alert_integrity_fail	alert[0x1e]	5784	1			T14	155		T19	2688		T20	5
alert_integrity_fail	alert[0x1f]	8617	1			T6	7		T14	94		T65	2
alert_integrity_fail	alert[0x20]	4214	1			T4	289		T14	75		T19	192
alert_integrity_fail	alert[0x21]	13661	1			T6	2		T65	76		T66	2
alert_integrity_fail	alert[0x22]	2073	1			T8	1		T6	2		T22	25
alert_integrity_fail	alert[0x23]	4874	1			T6	22		T14	300		T19	48
alert_integrity_fail	alert[0x24]	4818	1			T6	13		T19	106		T45	8
alert_integrity_fail	alert[0x25]	4851	1			T24	53		T50	48		T97	24
alert_integrity_fail	alert[0x26]	4585	1			T19	112		T20	1		T65	3
alert_integrity_fail	alert[0x27]	6183	1			T4	74		T6	55		T14	74
alert_integrity_fail	alert[0x28]	7373	1			T4	15		T19	4		T65	410
alert_integrity_fail	alert[0x29]	10482	1			T19	45		T22	139		T189	14
alert_integrity_fail	alert[0x2a]	13602	1			T6	17		T19	15		T24	9
alert_integrity_fail	alert[0x2b]	5547	1			T19	73		T65	24		T189	10
alert_integrity_fail	alert[0x2c]	4185	1			T4	32		T14	22		T22	72
alert_integrity_fail	alert[0x2d]	5285	1			T4	369		T8	1		T14	25
alert_integrity_fail	alert[0x2e]	7442	1			T14	454		T69	5		T47	1
alert_integrity_fail	alert[0x2f]	3707	1			T8	2		T6	77		T21	4
alert_integrity_fail	alert[0x30]	13606	1			T6	3		T14	649		T22	148
alert_integrity_fail	alert[0x31]	7362	1			T8	4		T6	8		T189	40
alert_integrity_fail	alert[0x32]	4156	1			T14	322		T65	27		T22	56
alert_integrity_fail	alert[0x33]	9303	1			T4	164		T14	335		T22	453
alert_integrity_fail	alert[0x34]	6969	1			T65	361		T189	43		T74	1
alert_integrity_fail	alert[0x35]	4914	1			T6	3		T24	46		T189	48
alert_integrity_fail	alert[0x36]	9967	1			T4	2		T8	4		T6	7
alert_integrity_fail	alert[0x37]	9943	1			T65	23		T189	1853		T54	47
alert_integrity_fail	alert[0x38]	19652	1			T4	37		T14	1499		T19	12
alert_integrity_fail	alert[0x39]	5071	1			T6	3		T14	368		T69	10
alert_integrity_fail	alert[0x3a]	5236	1			T21	2		T24	2		T69	11
alert_integrity_fail	alert[0x3b]	4839	1			T6	3		T19	11		T69	50
alert_integrity_fail	alert[0x3c]	6561	1			T4	153		T6	11		T19	199
alert_integrity_fail	alert[0x3d]	6864	1			T4	70		T14	18		T65	26
alert_integrity_fail	alert[0x3e]	4800	1			T19	38		T65	15		T49	2
alert_integrity_fail	alert[0x3f]	4983	1			T8	158		T14	212		T20	3
alert_integrity_fail	alert[0x40]	3461	1			T19	46		T22	86		T24	34
alert_ping_fail	alert[0x0]	12	1			T79	1		T233	1		T292	1
alert_ping_fail	alert[0x1]	13	1			T80	1		T293	1		T223	1
alert_ping_fail	alert[0x2]	8	1			T9	1		T28	2		T294	1
alert_ping_fail	alert[0x3]	14	1			T2	1		T86	1		T223	1
alert_ping_fail	alert[0x4]	8	1			T1	1		T86	1		T28	1
alert_ping_fail	alert[0x5]	14	1			T1	1		T2	1		T9	1
alert_ping_fail	alert[0x6]	23	1			T9	1		T81	1		T196	1
alert_ping_fail	alert[0x7]	17	1			T61	2		T288	1		T295	2
alert_ping_fail	alert[0x8]	18	1			T2	2		T28	1		T218	2
alert_ping_fail	alert[0x9]	13	1			T233	1		T292	3		T295	1
alert_ping_fail	alert[0xa]	16	1			T61	1		T28	1		T288	1
alert_ping_fail	alert[0xb]	10	1			T86	1		T223	1		T296	1
alert_ping_fail	alert[0xc]	5	1			T295	1		T296	1		T297	1
alert_ping_fail	alert[0xd]	7	1			T294	1		T298	1		T299	1
alert_ping_fail	alert[0xe]	6	1			T61	1		T300	2		T301	1
alert_ping_fail	alert[0xf]	14	1			T28	1		T295	1		T294	1
alert_ping_fail	alert[0x10]	10	1			T2	1		T196	1		T28	1
alert_ping_fail	alert[0x11]	7	1			T2	1		T233	1		T223	1
alert_ping_fail	alert[0x12]	4	1			T2	1		T86	1		T300	1
alert_ping_fail	alert[0x13]	9	1			T34	1		T296	1		T302	1
alert_ping_fail	alert[0x14]	14	1			T86	1		T218	1		T295	1
alert_ping_fail	alert[0x15]	9	1			T86	1		T28	1		T294	1
alert_ping_fail	alert[0x16]	8	1			T233	1		T303	1		T285	1
alert_ping_fail	alert[0x17]	12	1			T9	1		T86	1		T233	1
alert_ping_fail	alert[0x18]	10	1			T86	1		T196	1		T223	1
alert_ping_fail	alert[0x19]	12	1			T9	1		T79	2		T28	1
alert_ping_fail	alert[0x1a]	8	1			T1	2		T9	1		T233	1
alert_ping_fail	alert[0x1b]	4	1			T304	1		T305	1		T306	1
alert_ping_fail	alert[0x1c]	7	1			T2	1		T28	1		T298	1
alert_ping_fail	alert[0x1d]	9	1			T1	1		T224	2		T302	1
alert_ping_fail	alert[0x1e]	8	1			T61	1		T86	2		T295	1
alert_ping_fail	alert[0x1f]	12	1			T28	1		T37	1		T224	1
alert_ping_fail	alert[0x20]	8	1			T290	1		T296	3		T302	1
alert_ping_fail	alert[0x21]	8	1			T79	1		T80	1		T288	1
alert_ping_fail	alert[0x22]	21	1			T2	1		T81	2		T86	4
alert_ping_fail	alert[0x23]	16	1			T2	2		T80	1		T196	1
alert_ping_fail	alert[0x24]	5	1			T80	1		T307	1		T302	1
alert_ping_fail	alert[0x25]	6	1			T79	1		T196	1		T297	1
alert_ping_fail	alert[0x26]	11	1			T86	1		T233	1		T292	1
alert_ping_fail	alert[0x27]	5	1			T292	1		T308	1		T309	1
alert_ping_fail	alert[0x28]	16	1			T1	1		T196	1		T28	1
alert_ping_fail	alert[0x29]	13	1			T61	1		T218	1		T292	2
alert_ping_fail	alert[0x2a]	8	1			T292	1		T296	1		T310	1
alert_ping_fail	alert[0x2b]	7	1			T2	1		T86	1		T293	1
alert_ping_fail	alert[0x2c]	9	1			T218	1		T224	2		T298	1
alert_ping_fail	alert[0x2d]	17	1			T1	1		T2	1		T9	2
alert_ping_fail	alert[0x2e]	9	1			T9	1		T13	1		T81	1
alert_ping_fail	alert[0x2f]	9	1			T13	1		T292	2		T303	1
alert_ping_fail	alert[0x30]	8	1			T196	1		T292	1		T224	1
alert_ping_fail	alert[0x31]	5	1			T86	1		T292	1		T311	1
alert_ping_fail	alert[0x32]	13	1			T80	1		T86	1		T218	1
alert_ping_fail	alert[0x33]	10	1			T86	1		T294	2		T307	1
alert_ping_fail	alert[0x34]	9	1			T293	1		T311	1		T301	3
alert_ping_fail	alert[0x35]	9	1			T9	1		T196	1		T28	1
alert_ping_fail	alert[0x36]	12	1			T292	1		T304	1		T296	1
alert_ping_fail	alert[0x37]	9	1			T9	1		T80	1		T196	1
alert_ping_fail	alert[0x38]	9	1			T2	1		T28	1		T218	1
alert_ping_fail	alert[0x39]	7	1			T196	1		T28	1		T293	1
alert_ping_fail	alert[0x3a]	6	1			T307	1		T312	1		T299	1
alert_ping_fail	alert[0x3b]	11	1			T1	1		T9	2		T86	1
alert_ping_fail	alert[0x3c]	8	1			T295	1		T304	2		T302	2
alert_ping_fail	alert[0x3d]	8	1			T304	2		T313	1		T308	1
alert_ping_fail	alert[0x3e]	12	1			T1	2		T86	1		T28	1
alert_ping_fail	alert[0x3f]	4	1			T196	1		T311	1		T309	1
alert_ping_fail	alert[0x40]	7	1			T1	1		T2	1		T298	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	129254	1			T4	98		T8	11		T6	286
alert_integrity_fail	class_i[0x1]	142619	1			T8	14		T6	14		T21	4
alert_integrity_fail	class_i[0x2]	94610	1			T4	3		T8	142		T5	4
alert_integrity_fail	class_i[0x3]	89008	1			T4	5714		T8	39		T6	28
alert_ping_fail	class_i[0x0]	156	1			T1	3		T2	15		T9	2
alert_ping_fail	class_i[0x1]	109	1			T1	3		T9	2		T61	3
alert_ping_fail	class_i[0x2]	211	1			T1	1		T9	7		T13	2
alert_ping_fail	class_i[0x3]	180	1			T1	4		T9	2		T61	2