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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.66 99.97 100.00 100.00 99.38 99.60


Total test records in report: 826
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T769 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3662252612 May 12 02:11:50 PM PDT 24 May 12 02:11:53 PM PDT 24 34572776 ps
T770 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3991706465 May 12 02:11:59 PM PDT 24 May 12 02:12:05 PM PDT 24 92856082 ps
T169 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.493743253 May 12 02:11:57 PM PDT 24 May 12 02:12:47 PM PDT 24 372108218 ps
T771 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4017033602 May 12 02:12:05 PM PDT 24 May 12 02:12:45 PM PDT 24 552178097 ps
T772 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2376223046 May 12 02:12:02 PM PDT 24 May 12 02:12:07 PM PDT 24 19953142 ps
T144 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4159896996 May 12 02:11:51 PM PDT 24 May 12 02:30:02 PM PDT 24 28527070283 ps
T773 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1735375555 May 12 02:11:53 PM PDT 24 May 12 02:12:34 PM PDT 24 578654106 ps
T774 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.150352021 May 12 02:11:54 PM PDT 24 May 12 02:12:00 PM PDT 24 23036425 ps
T775 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1893041990 May 12 02:12:04 PM PDT 24 May 12 02:12:07 PM PDT 24 12480433 ps
T776 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.992231282 May 12 02:12:02 PM PDT 24 May 12 02:12:13 PM PDT 24 2114034085 ps
T145 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3149856846 May 12 02:11:57 PM PDT 24 May 12 02:17:44 PM PDT 24 32683096308 ps
T777 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.190888621 May 12 02:12:06 PM PDT 24 May 12 02:12:08 PM PDT 24 15198496 ps
T778 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1954994175 May 12 02:11:51 PM PDT 24 May 12 02:12:02 PM PDT 24 496186166 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.765225238 May 12 02:11:55 PM PDT 24 May 12 02:12:04 PM PDT 24 778280375 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.528112286 May 12 02:11:48 PM PDT 24 May 12 02:15:39 PM PDT 24 16804856147 ps
T141 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3493006909 May 12 02:11:58 PM PDT 24 May 12 02:18:11 PM PDT 24 70819444897 ps
T781 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1934276132 May 12 02:11:56 PM PDT 24 May 12 02:11:58 PM PDT 24 11897308 ps
T782 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3498781663 May 12 02:11:57 PM PDT 24 May 12 02:12:08 PM PDT 24 492837938 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.135468584 May 12 02:11:48 PM PDT 24 May 12 02:12:05 PM PDT 24 899507182 ps
T784 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4104508830 May 12 02:12:10 PM PDT 24 May 12 02:12:13 PM PDT 24 8707208 ps
T785 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2874781989 May 12 02:12:01 PM PDT 24 May 12 02:12:13 PM PDT 24 250907215 ps
T345 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.188712264 May 12 02:12:02 PM PDT 24 May 12 02:22:33 PM PDT 24 8650423485 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.168301548 May 12 02:11:46 PM PDT 24 May 12 02:18:00 PM PDT 24 23712162109 ps
T139 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3589794344 May 12 02:12:04 PM PDT 24 May 12 02:13:28 PM PDT 24 747137492 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3328784115 May 12 02:11:48 PM PDT 24 May 12 02:14:10 PM PDT 24 2257124007 ps
T165 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4024340678 May 12 02:11:52 PM PDT 24 May 12 02:11:57 PM PDT 24 142016871 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3598050484 May 12 02:11:56 PM PDT 24 May 12 02:12:04 PM PDT 24 139300634 ps
T789 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.175149596 May 12 02:11:56 PM PDT 24 May 12 02:12:01 PM PDT 24 56231456 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3392222522 May 12 02:11:46 PM PDT 24 May 12 02:23:06 PM PDT 24 9382356675 ps
T152 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.291227506 May 12 02:11:48 PM PDT 24 May 12 02:13:21 PM PDT 24 3858693352 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1518789238 May 12 02:12:05 PM PDT 24 May 12 02:12:54 PM PDT 24 7213319747 ps
T143 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2409089006 May 12 02:11:53 PM PDT 24 May 12 02:15:15 PM PDT 24 1568714471 ps
T791 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.110885146 May 12 02:11:56 PM PDT 24 May 12 02:12:10 PM PDT 24 92660373 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2978031911 May 12 02:11:50 PM PDT 24 May 12 02:11:53 PM PDT 24 7965797 ps
T793 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2495720485 May 12 02:11:58 PM PDT 24 May 12 02:12:12 PM PDT 24 584430636 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1337024793 May 12 02:12:05 PM PDT 24 May 12 02:28:37 PM PDT 24 49210922823 ps
T156 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.164015196 May 12 02:12:02 PM PDT 24 May 12 02:14:04 PM PDT 24 1681543464 ps
T794 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.229841038 May 12 02:12:11 PM PDT 24 May 12 02:12:13 PM PDT 24 23765149 ps
T795 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3349151901 May 12 02:11:49 PM PDT 24 May 12 02:12:16 PM PDT 24 370366599 ps
T154 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3389523123 May 12 02:11:47 PM PDT 24 May 12 02:15:11 PM PDT 24 7134614849 ps
T344 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2890438746 May 12 02:11:58 PM PDT 24 May 12 02:28:56 PM PDT 24 51995087408 ps
T796 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3834168321 May 12 02:11:57 PM PDT 24 May 12 02:12:08 PM PDT 24 124781699 ps
T797 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4266071648 May 12 02:12:04 PM PDT 24 May 12 02:12:06 PM PDT 24 9991000 ps
T153 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.659363709 May 12 02:11:57 PM PDT 24 May 12 02:20:43 PM PDT 24 6033191464 ps
T157 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2647704905 May 12 02:11:51 PM PDT 24 May 12 02:14:04 PM PDT 24 1955434188 ps
T798 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4033579910 May 12 02:12:01 PM PDT 24 May 12 02:12:04 PM PDT 24 15818982 ps
T799 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4065451884 May 12 02:12:12 PM PDT 24 May 12 02:12:14 PM PDT 24 9373962 ps
T800 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.996782323 May 12 02:12:04 PM PDT 24 May 12 02:12:12 PM PDT 24 115097334 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2560457347 May 12 02:12:04 PM PDT 24 May 12 02:12:20 PM PDT 24 428954071 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.481937203 May 12 02:12:03 PM PDT 24 May 12 02:12:06 PM PDT 24 9655158 ps
T803 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3031290106 May 12 02:12:13 PM PDT 24 May 12 02:12:15 PM PDT 24 19916255 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.709913169 May 12 02:11:47 PM PDT 24 May 12 02:11:53 PM PDT 24 82323995 ps
T805 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1262880260 May 12 02:11:52 PM PDT 24 May 12 02:12:03 PM PDT 24 122056363 ps
T148 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1783155451 May 12 02:11:47 PM PDT 24 May 12 02:13:22 PM PDT 24 779627975 ps
T806 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2414299012 May 12 02:12:11 PM PDT 24 May 12 02:12:13 PM PDT 24 7514317 ps
T807 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1651611169 May 12 02:11:53 PM PDT 24 May 12 02:14:24 PM PDT 24 4639120012 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3626159347 May 12 02:12:04 PM PDT 24 May 12 02:12:26 PM PDT 24 577688603 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.983682787 May 12 02:12:10 PM PDT 24 May 12 02:13:20 PM PDT 24 1774754624 ps
T810 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3416036278 May 12 02:12:10 PM PDT 24 May 12 02:12:12 PM PDT 24 8103372 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2790879092 May 12 02:11:52 PM PDT 24 May 12 02:18:23 PM PDT 24 5710547883 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3456460081 May 12 02:11:56 PM PDT 24 May 12 02:12:10 PM PDT 24 1348317607 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1584643828 May 12 02:11:48 PM PDT 24 May 12 02:11:51 PM PDT 24 14624769 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.343366594 May 12 02:11:50 PM PDT 24 May 12 02:11:57 PM PDT 24 96817937 ps
T815 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4185702427 May 12 02:12:03 PM PDT 24 May 12 02:12:10 PM PDT 24 474155251 ps
T816 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.701468364 May 12 02:12:04 PM PDT 24 May 12 02:12:07 PM PDT 24 9339751 ps
T817 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2229413672 May 12 02:11:54 PM PDT 24 May 12 02:12:41 PM PDT 24 622794109 ps
T818 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2862012000 May 12 02:12:01 PM PDT 24 May 12 02:12:10 PM PDT 24 343812536 ps
T819 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2507492159 May 12 02:12:11 PM PDT 24 May 12 02:12:14 PM PDT 24 7622926 ps
T155 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.98297929 May 12 02:11:50 PM PDT 24 May 12 02:20:29 PM PDT 24 26692948143 ps
T820 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.995836468 May 12 02:12:03 PM PDT 24 May 12 02:12:25 PM PDT 24 183465586 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1963432576 May 12 02:11:52 PM PDT 24 May 12 02:11:59 PM PDT 24 232546489 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3191030926 May 12 02:11:59 PM PDT 24 May 12 02:12:06 PM PDT 24 72530059 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3575876948 May 12 02:11:47 PM PDT 24 May 12 02:11:55 PM PDT 24 34709992 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4058856424 May 12 02:12:02 PM PDT 24 May 12 02:12:11 PM PDT 24 212442613 ps
T825 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.397279789 May 12 02:11:45 PM PDT 24 May 12 02:15:12 PM PDT 24 1636531318 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.721607947 May 12 02:11:50 PM PDT 24 May 12 02:11:57 PM PDT 24 74491009 ps

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2709527273
Short name T6
Test name
Test status
Simulation time 31160692030 ps
CPU time 2110.53 seconds
Started May 12 02:55:51 PM PDT 24
Finished May 12 03:31:03 PM PDT 24
Peak memory 287752 kb
Host smart-12f876cc-241f-4e96-93fe-47300e0d4f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709527273 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2709527273
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4102104283
Short name T29
Test name
Test status
Simulation time 1121723146 ps
CPU time 47.73 seconds
Started May 12 02:54:41 PM PDT 24
Finished May 12 02:55:29 PM PDT 24
Peak memory 270212 kb
Host smart-7169422e-a80e-44a6-8986-eeec61270088
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4102104283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4102104283
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2315896671
Short name T19
Test name
Test status
Simulation time 30179648984 ps
CPU time 4145.46 seconds
Started May 12 02:57:33 PM PDT 24
Finished May 12 04:06:40 PM PDT 24
Peak memory 331684 kb
Host smart-61a36b30-3969-4ecf-aeed-64b5f1d60447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315896671 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2315896671
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1823530252
Short name T122
Test name
Test status
Simulation time 15664318242 ps
CPU time 1135.56 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:30:54 PM PDT 24
Peak memory 265444 kb
Host smart-ee9a5a20-b7e5-4c60-874c-e03732147f61
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823530252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1823530252
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1743250813
Short name T7
Test name
Test status
Simulation time 904896066 ps
CPU time 21.69 seconds
Started May 12 02:55:51 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 240536 kb
Host smart-515cb590-ad0e-40be-a49e-fde7b5e3c0ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1743250813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1743250813
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.608518491
Short name T72
Test name
Test status
Simulation time 586437702 ps
CPU time 44.37 seconds
Started May 12 02:57:05 PM PDT 24
Finished May 12 02:57:50 PM PDT 24
Peak memory 248796 kb
Host smart-5e864ca9-d579-4535-b749-242292a2db81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60851
8491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.608518491
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.538598899
Short name T178
Test name
Test status
Simulation time 486669841 ps
CPU time 33.51 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:12:27 PM PDT 24
Peak memory 245480 kb
Host smart-b409a0a5-781a-4ddd-ab24-ceafac35aa02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=538598899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.538598899
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3781667287
Short name T81
Test name
Test status
Simulation time 35305405163 ps
CPU time 2396.68 seconds
Started May 12 02:59:06 PM PDT 24
Finished May 12 03:39:03 PM PDT 24
Peak memory 281548 kb
Host smart-149477e2-0636-43bf-90fc-5d583ebf900d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781667287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3781667287
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.649645452
Short name T92
Test name
Test status
Simulation time 9718364571 ps
CPU time 586.64 seconds
Started May 12 02:56:31 PM PDT 24
Finished May 12 03:06:18 PM PDT 24
Peak memory 256984 kb
Host smart-2c4fc03b-5d90-42ae-9250-161398e62517
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649645452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.649645452
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1473916477
Short name T120
Test name
Test status
Simulation time 5472460533 ps
CPU time 386.81 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:18:22 PM PDT 24
Peak memory 265344 kb
Host smart-1b726527-fc45-490e-ad50-c63292285b69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1473916477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1473916477
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.575770175
Short name T127
Test name
Test status
Simulation time 10563913403 ps
CPU time 368.33 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:18:02 PM PDT 24
Peak memory 265384 kb
Host smart-6883fe8a-56b9-4a91-ac05-77f47e0598ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=575770175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.575770175
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1616032624
Short name T303
Test name
Test status
Simulation time 131307681934 ps
CPU time 3322.51 seconds
Started May 12 02:55:42 PM PDT 24
Finished May 12 03:51:05 PM PDT 24
Peak memory 286752 kb
Host smart-8ffcd334-d449-4ee0-8aa6-74f4660a0cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616032624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1616032624
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.425745854
Short name T95
Test name
Test status
Simulation time 89029568765 ps
CPU time 4492.37 seconds
Started May 12 02:55:23 PM PDT 24
Finished May 12 04:10:16 PM PDT 24
Peak memory 297600 kb
Host smart-0568e19c-4f34-4fb0-abe2-cc10e0cbc648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425745854 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.425745854
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3162395061
Short name T247
Test name
Test status
Simulation time 1511265515 ps
CPU time 23.91 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:57:11 PM PDT 24
Peak memory 255156 kb
Host smart-4f37f217-2d6d-4266-b1cd-2a2612a74209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31623
95061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3162395061
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3278010193
Short name T14
Test name
Test status
Simulation time 190928738832 ps
CPU time 3240.58 seconds
Started May 12 02:57:16 PM PDT 24
Finished May 12 03:51:17 PM PDT 24
Peak memory 281592 kb
Host smart-95e9c0fb-89c6-433b-b8f3-a06475d465ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278010193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3278010193
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.506971224
Short name T134
Test name
Test status
Simulation time 47327418042 ps
CPU time 869.77 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:26:29 PM PDT 24
Peak memory 270820 kb
Host smart-87e74816-4aa4-488d-9b12-9278046ecce0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506971224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.506971224
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.795456625
Short name T28
Test name
Test status
Simulation time 44750245354 ps
CPU time 459.92 seconds
Started May 12 02:57:30 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 247148 kb
Host smart-e755a4b6-8763-4ae3-a6b5-d9693a9481cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795456625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.795456625
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.359514018
Short name T335
Test name
Test status
Simulation time 14062989 ps
CPU time 1.45 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 235896 kb
Host smart-c1d664c8-45f2-4f68-bb7e-31315dd1c2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=359514018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.359514018
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2610345186
Short name T136
Test name
Test status
Simulation time 17247123800 ps
CPU time 1206.51 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:31:58 PM PDT 24
Peak memory 273000 kb
Host smart-76abaded-4fd0-41fb-a241-98e488a08248
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610345186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2610345186
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3695693932
Short name T77
Test name
Test status
Simulation time 222088386992 ps
CPU time 3862.93 seconds
Started May 12 02:57:16 PM PDT 24
Finished May 12 04:01:40 PM PDT 24
Peak memory 304276 kb
Host smart-7b3e68bb-761e-405f-9e2b-951001113d29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695693932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3695693932
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2409089006
Short name T143
Test name
Test status
Simulation time 1568714471 ps
CPU time 199.78 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:15:15 PM PDT 24
Peak memory 265340 kb
Host smart-0c81eab4-3b86-44e4-a995-deced9f9a75a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2409089006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2409089006
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1045028631
Short name T86
Test name
Test status
Simulation time 93345292961 ps
CPU time 514.73 seconds
Started May 12 02:58:11 PM PDT 24
Finished May 12 03:06:46 PM PDT 24
Peak memory 248268 kb
Host smart-6445cebe-5491-4a59-8958-2930371f0a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045028631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1045028631
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2263451852
Short name T196
Test name
Test status
Simulation time 38557751802 ps
CPU time 403.73 seconds
Started May 12 02:57:24 PM PDT 24
Finished May 12 03:04:08 PM PDT 24
Peak memory 248352 kb
Host smart-ac0e2d74-d65d-484b-8710-73f64576cf9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263451852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2263451852
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3503068107
Short name T121
Test name
Test status
Simulation time 8983198932 ps
CPU time 331.73 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:17:37 PM PDT 24
Peak memory 265556 kb
Host smart-53d7134a-f65c-430a-8836-c3d829af2297
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503068107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3503068107
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.329516371
Short name T20
Test name
Test status
Simulation time 196116809836 ps
CPU time 4688.33 seconds
Started May 12 02:56:17 PM PDT 24
Finished May 12 04:14:26 PM PDT 24
Peak memory 317276 kb
Host smart-24502150-b0a9-4abb-9f8f-732e058661f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329516371 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.329516371
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3098835878
Short name T288
Test name
Test status
Simulation time 14349081447 ps
CPU time 1236.18 seconds
Started May 12 02:54:39 PM PDT 24
Finished May 12 03:15:16 PM PDT 24
Peak memory 281592 kb
Host smart-60def6c5-2d23-4c3d-8fbb-860efd250cce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098835878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3098835878
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.73521034
Short name T138
Test name
Test status
Simulation time 1680289257 ps
CPU time 201.77 seconds
Started May 12 02:12:07 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 265304 kb
Host smart-cfef057a-e877-4505-8c76-e29154b47203
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73521034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.73521034
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.810179601
Short name T103
Test name
Test status
Simulation time 45138724157 ps
CPU time 3312.74 seconds
Started May 12 02:58:42 PM PDT 24
Finished May 12 03:53:56 PM PDT 24
Peak memory 302456 kb
Host smart-0a3bdb4d-f08b-4d5b-96ec-9f02016e5c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810179601 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.810179601
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2358200585
Short name T604
Test name
Test status
Simulation time 16005159240 ps
CPU time 642.77 seconds
Started May 12 02:54:45 PM PDT 24
Finished May 12 03:05:28 PM PDT 24
Peak memory 247700 kb
Host smart-bdcb80f1-7f32-480f-a0ca-2263a99abbd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358200585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2358200585
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2452113662
Short name T330
Test name
Test status
Simulation time 39825607616 ps
CPU time 1411.55 seconds
Started May 12 02:55:56 PM PDT 24
Finished May 12 03:19:28 PM PDT 24
Peak memory 265244 kb
Host smart-0e2c66bf-d4ef-41f1-9d70-f514882a6344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452113662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2452113662
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1054516079
Short name T131
Test name
Test status
Simulation time 21499433845 ps
CPU time 1377.18 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:34:56 PM PDT 24
Peak memory 272232 kb
Host smart-1f586fbb-33db-4d69-88e0-32d05658c182
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054516079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1054516079
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1590543798
Short name T179
Test name
Test status
Simulation time 223871831141 ps
CPU time 4005.07 seconds
Started May 12 02:55:40 PM PDT 24
Finished May 12 04:02:26 PM PDT 24
Peak memory 302948 kb
Host smart-b8ab1a42-b577-461a-8fc8-9e2726d3be1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590543798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1590543798
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2499842422
Short name T22
Test name
Test status
Simulation time 39743524902 ps
CPU time 2840.95 seconds
Started May 12 02:55:41 PM PDT 24
Finished May 12 03:43:02 PM PDT 24
Peak memory 289208 kb
Host smart-147071c6-9ef2-4f16-a2f4-7528adc766cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499842422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2499842422
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2921541179
Short name T325
Test name
Test status
Simulation time 261320273595 ps
CPU time 2707.71 seconds
Started May 12 02:57:58 PM PDT 24
Finished May 12 03:43:07 PM PDT 24
Peak memory 287396 kb
Host smart-7f8a4bfe-fa17-41cb-a0fe-570a5f89fe9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921541179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2921541179
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3845629220
Short name T299
Test name
Test status
Simulation time 7285016266 ps
CPU time 334.74 seconds
Started May 12 02:56:39 PM PDT 24
Finished May 12 03:02:14 PM PDT 24
Peak memory 248152 kb
Host smart-54865134-c796-4d79-914f-aab842940a25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845629220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3845629220
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2652193399
Short name T65
Test name
Test status
Simulation time 39317137701 ps
CPU time 1537.21 seconds
Started May 12 02:57:38 PM PDT 24
Finished May 12 03:23:16 PM PDT 24
Peak memory 284416 kb
Host smart-943b126c-3683-4e67-a89e-a8b301a861f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652193399 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2652193399
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4003099497
Short name T710
Test name
Test status
Simulation time 19297000 ps
CPU time 1.4 seconds
Started May 12 02:12:09 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 235940 kb
Host smart-77ad1415-e471-4b13-a99e-61db63d706a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003099497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4003099497
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2108033939
Short name T37
Test name
Test status
Simulation time 604817394426 ps
CPU time 2610.09 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 03:38:42 PM PDT 24
Peak memory 288972 kb
Host smart-835b098f-6685-419b-87d7-54e2b848286a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108033939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2108033939
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2730266236
Short name T177
Test name
Test status
Simulation time 289061388 ps
CPU time 3.23 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:11:54 PM PDT 24
Peak memory 235716 kb
Host smart-adeb2969-a03f-4d45-a766-b011b589927e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2730266236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2730266236
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1146304279
Short name T126
Test name
Test status
Simulation time 6930602273 ps
CPU time 237.76 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 265328 kb
Host smart-77f1758d-b443-4d5c-bd69-c687cadf4311
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1146304279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1146304279
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1135341536
Short name T259
Test name
Test status
Simulation time 10066213909 ps
CPU time 966.81 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 03:10:52 PM PDT 24
Peak memory 282444 kb
Host smart-fa952615-963d-472c-bae8-ef1f909d2e9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135341536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1135341536
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4159896996
Short name T144
Test name
Test status
Simulation time 28527070283 ps
CPU time 1089.56 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:30:02 PM PDT 24
Peak memory 265632 kb
Host smart-164c8893-0bb1-44ed-82b5-6ea31657dc67
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159896996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4159896996
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2952598891
Short name T160
Test name
Test status
Simulation time 121908155 ps
CPU time 2.68 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 236832 kb
Host smart-4e6e6ea2-2b1b-411d-b729-92b68d30bc01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2952598891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2952598891
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3645458669
Short name T235
Test name
Test status
Simulation time 53654123058 ps
CPU time 1982.91 seconds
Started May 12 02:55:52 PM PDT 24
Finished May 12 03:28:56 PM PDT 24
Peak memory 287888 kb
Host smart-0328334a-0e81-4bfb-b976-538e6873bc92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645458669 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3645458669
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.185824296
Short name T332
Test name
Test status
Simulation time 20266838906 ps
CPU time 1328.61 seconds
Started May 12 02:58:34 PM PDT 24
Finished May 12 03:20:43 PM PDT 24
Peak memory 272664 kb
Host smart-afd74e4f-8262-4a04-a361-94009e1e5668
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185824296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.185824296
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2808133544
Short name T304
Test name
Test status
Simulation time 5530509827 ps
CPU time 222.54 seconds
Started May 12 02:58:44 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 247260 kb
Host smart-4af307cd-6cb1-41a4-878d-2f0bf1f35438
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808133544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2808133544
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.588894197
Short name T557
Test name
Test status
Simulation time 12449814796 ps
CPU time 456.38 seconds
Started May 12 03:00:17 PM PDT 24
Finished May 12 03:07:54 PM PDT 24
Peak memory 247144 kb
Host smart-3466c429-fe08-40ea-87c0-262e24240a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588894197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.588894197
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1473256931
Short name T49
Test name
Test status
Simulation time 23861081665 ps
CPU time 1864.51 seconds
Started May 12 02:57:59 PM PDT 24
Finished May 12 03:29:04 PM PDT 24
Peak memory 289672 kb
Host smart-9dc0b2fd-dec0-487b-8b39-ca28cdbef292
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473256931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1473256931
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3231820973
Short name T21
Test name
Test status
Simulation time 3089766022 ps
CPU time 42.53 seconds
Started May 12 02:57:03 PM PDT 24
Finished May 12 02:57:46 PM PDT 24
Peak memory 256276 kb
Host smart-b1cfdcb8-b000-49e0-846a-af50b5c5ca91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
20973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3231820973
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.141737191
Short name T207
Test name
Test status
Simulation time 104843050 ps
CPU time 3.42 seconds
Started May 12 02:54:38 PM PDT 24
Finished May 12 02:54:42 PM PDT 24
Peak memory 248924 kb
Host smart-6e23ff1f-4775-44dc-8e2d-89254ad50a78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=141737191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.141737191
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1464885261
Short name T202
Test name
Test status
Simulation time 72509221 ps
CPU time 3.86 seconds
Started May 12 02:54:43 PM PDT 24
Finished May 12 02:54:47 PM PDT 24
Peak memory 248876 kb
Host smart-48fdf776-b3c3-44d1-ab3e-511357a24dea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1464885261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1464885261
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.679634129
Short name T200
Test name
Test status
Simulation time 107952666 ps
CPU time 3.3 seconds
Started May 12 02:56:05 PM PDT 24
Finished May 12 02:56:09 PM PDT 24
Peak memory 248876 kb
Host smart-a2d3a077-f465-40aa-88b2-ce140498a470
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=679634129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.679634129
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3637719445
Short name T203
Test name
Test status
Simulation time 40784800 ps
CPU time 3.62 seconds
Started May 12 02:54:49 PM PDT 24
Finished May 12 02:54:53 PM PDT 24
Peak memory 248904 kb
Host smart-a934a845-6f84-49f8-827e-898e5dc6aaa7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637719445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3637719445
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1891309288
Short name T245
Test name
Test status
Simulation time 17603635444 ps
CPU time 1142.88 seconds
Started May 12 02:56:21 PM PDT 24
Finished May 12 03:15:24 PM PDT 24
Peak memory 272712 kb
Host smart-8a449bb7-2680-45ca-b805-4d303d83354e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891309288 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1891309288
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1148620084
Short name T2
Test name
Test status
Simulation time 12199800279 ps
CPU time 450.95 seconds
Started May 12 02:57:06 PM PDT 24
Finished May 12 03:04:37 PM PDT 24
Peak memory 247200 kb
Host smart-5bd9629b-0147-4495-867e-bd52353f77ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148620084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1148620084
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1000803700
Short name T242
Test name
Test status
Simulation time 320747857 ps
CPU time 21.46 seconds
Started May 12 02:57:04 PM PDT 24
Finished May 12 02:57:26 PM PDT 24
Peak memory 255496 kb
Host smart-091f6a69-3e86-4ac0-877b-348de7e609e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
03700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1000803700
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3452945942
Short name T317
Test name
Test status
Simulation time 9818137446 ps
CPU time 992.79 seconds
Started May 12 02:57:13 PM PDT 24
Finished May 12 03:13:46 PM PDT 24
Peak memory 272524 kb
Host smart-637f2f46-7a68-4a92-aff2-4c43dadac956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452945942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3452945942
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3180082643
Short name T250
Test name
Test status
Simulation time 53483913718 ps
CPU time 2680.47 seconds
Started May 12 02:55:29 PM PDT 24
Finished May 12 03:40:10 PM PDT 24
Peak memory 289236 kb
Host smart-46b560d2-7ac9-4ac7-9268-90dd0a4900fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180082643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3180082643
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4134275574
Short name T129
Test name
Test status
Simulation time 8212401805 ps
CPU time 577.86 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:21:39 PM PDT 24
Peak memory 265320 kb
Host smart-c0d0ffb2-f719-466d-a94e-8b6fd9dc0c29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134275574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.4134275574
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3988613637
Short name T167
Test name
Test status
Simulation time 3649394390 ps
CPU time 69.97 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:13:00 PM PDT 24
Peak memory 239808 kb
Host smart-0ced47cc-95bb-49c6-af76-0303eb3251c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3988613637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3988613637
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3149856846
Short name T145
Test name
Test status
Simulation time 32683096308 ps
CPU time 345.73 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:17:44 PM PDT 24
Peak memory 265308 kb
Host smart-c9bf6b59-e079-4f66-be39-e601c5beba4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3149856846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3149856846
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2125814297
Short name T763
Test name
Test status
Simulation time 18270575 ps
CPU time 1.4 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:11:50 PM PDT 24
Peak memory 236856 kb
Host smart-a4e22469-60ab-497e-9e84-0233241b8a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2125814297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2125814297
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3921948643
Short name T609
Test name
Test status
Simulation time 9866401021 ps
CPU time 414.5 seconds
Started May 12 02:54:35 PM PDT 24
Finished May 12 03:01:30 PM PDT 24
Peak memory 248212 kb
Host smart-9bc58c72-6e59-41b4-b77a-aad2690a2c9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921948643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3921948643
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1417526086
Short name T58
Test name
Test status
Simulation time 65978116460 ps
CPU time 3618.78 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 03:55:03 PM PDT 24
Peak memory 317996 kb
Host smart-f1f66d6c-e62d-4b72-bb20-c5e7798b6e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417526086 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1417526086
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2676610707
Short name T255
Test name
Test status
Simulation time 1854406095 ps
CPU time 43.3 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 02:56:27 PM PDT 24
Peak memory 255052 kb
Host smart-5b91a69b-af96-47c3-a2f6-a1253996f7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26766
10707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2676610707
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2254872305
Short name T76
Test name
Test status
Simulation time 3572294687 ps
CPU time 60.86 seconds
Started May 12 02:56:31 PM PDT 24
Finished May 12 02:57:33 PM PDT 24
Peak memory 256920 kb
Host smart-7809bcca-f399-4a2f-ba01-84a03877cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
72305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2254872305
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1909284715
Short name T329
Test name
Test status
Simulation time 180212760436 ps
CPU time 2946.84 seconds
Started May 12 02:56:50 PM PDT 24
Finished May 12 03:45:58 PM PDT 24
Peak memory 288920 kb
Host smart-91426fc6-c4bb-4fed-9238-3e95b05ca0cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909284715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1909284715
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3777987766
Short name T273
Test name
Test status
Simulation time 161829359699 ps
CPU time 2835.26 seconds
Started May 12 02:57:02 PM PDT 24
Finished May 12 03:44:18 PM PDT 24
Peak memory 289308 kb
Host smart-c1762892-9203-4fde-8fd1-5f44c3adac42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777987766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3777987766
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.216088280
Short name T265
Test name
Test status
Simulation time 38335118508 ps
CPU time 1545.48 seconds
Started May 12 02:57:12 PM PDT 24
Finished May 12 03:22:58 PM PDT 24
Peak memory 289216 kb
Host smart-21b14aa6-8fd2-441a-8695-8e1b32e69178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216088280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.216088280
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.915856897
Short name T75
Test name
Test status
Simulation time 25824850123 ps
CPU time 1738.2 seconds
Started May 12 02:57:28 PM PDT 24
Finished May 12 03:26:27 PM PDT 24
Peak memory 273348 kb
Host smart-64882048-ebff-4534-a748-28d9bd67f389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915856897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.915856897
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2014242780
Short name T274
Test name
Test status
Simulation time 48713798039 ps
CPU time 1248.58 seconds
Started May 12 02:58:10 PM PDT 24
Finished May 12 03:18:59 PM PDT 24
Peak memory 282616 kb
Host smart-b49b56f7-3934-4985-ae10-546171820320
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014242780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2014242780
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.643801466
Short name T24
Test name
Test status
Simulation time 344280301849 ps
CPU time 7513.82 seconds
Started May 12 02:58:14 PM PDT 24
Finished May 12 05:03:29 PM PDT 24
Peak memory 371836 kb
Host smart-5702249e-74a5-4d69-9251-01f60b5edde4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643801466 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.643801466
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2142310485
Short name T66
Test name
Test status
Simulation time 933156219 ps
CPU time 51.06 seconds
Started May 12 02:58:16 PM PDT 24
Finished May 12 02:59:08 PM PDT 24
Peak memory 248736 kb
Host smart-d3aad4f9-3690-497e-a888-24a52129263d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
10485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2142310485
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3550283730
Short name T110
Test name
Test status
Simulation time 40717246116 ps
CPU time 2903.27 seconds
Started May 12 02:58:38 PM PDT 24
Finished May 12 03:47:02 PM PDT 24
Peak memory 289636 kb
Host smart-be7850fa-31e5-4a1b-b814-9ee2537c5a50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550283730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3550283730
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2426915663
Short name T239
Test name
Test status
Simulation time 2243455313 ps
CPU time 43.99 seconds
Started May 12 02:58:39 PM PDT 24
Finished May 12 02:59:24 PM PDT 24
Peak memory 255496 kb
Host smart-f68bfb02-7106-43fc-aa5f-2a24d0b31a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
15663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2426915663
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2200862083
Short name T271
Test name
Test status
Simulation time 4372973120 ps
CPU time 274.65 seconds
Started May 12 02:59:04 PM PDT 24
Finished May 12 03:03:39 PM PDT 24
Peak memory 251956 kb
Host smart-31905570-8964-4e35-848c-d34b1a42893b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200862083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2200862083
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1826945155
Short name T69
Test name
Test status
Simulation time 187889557139 ps
CPU time 9202.7 seconds
Started May 12 02:59:30 PM PDT 24
Finished May 12 05:32:54 PM PDT 24
Peak memory 404068 kb
Host smart-401eb736-4ba7-46e1-824b-5cf956cf2179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826945155 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1826945155
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.587791983
Short name T323
Test name
Test status
Simulation time 52353001628 ps
CPU time 1516.77 seconds
Started May 12 02:59:54 PM PDT 24
Finished May 12 03:25:12 PM PDT 24
Peak memory 271356 kb
Host smart-391b6c2b-7864-4efd-984e-c7b1a13c56af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587791983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.587791983
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.820288998
Short name T248
Test name
Test status
Simulation time 647034150 ps
CPU time 37.75 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 02:55:50 PM PDT 24
Peak memory 248744 kb
Host smart-3413be6e-9f76-4341-bb92-1450d6eb050e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82028
8998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.820288998
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.473393102
Short name T10
Test name
Test status
Simulation time 1246315791 ps
CPU time 19.56 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 02:55:05 PM PDT 24
Peak memory 270128 kb
Host smart-08d81ee7-3929-4811-8512-06e3e7da42d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=473393102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.473393102
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.197789056
Short name T123
Test name
Test status
Simulation time 43337869210 ps
CPU time 363.44 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:18:03 PM PDT 24
Peak memory 272732 kb
Host smart-4b5a6590-1eb5-46f3-9018-eb9c98e0c799
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197789056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.197789056
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3258663836
Short name T172
Test name
Test status
Simulation time 144263826 ps
CPU time 7.94 seconds
Started May 12 02:12:03 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 236812 kb
Host smart-69581510-2bf4-4cf9-b3e4-b680cbd8d82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3258663836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3258663836
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3176827480
Short name T159
Test name
Test status
Simulation time 113664249 ps
CPU time 4.27 seconds
Started May 12 02:11:46 PM PDT 24
Finished May 12 02:11:52 PM PDT 24
Peak memory 236896 kb
Host smart-e122d58f-fbc3-4304-97cb-a84b23673e35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3176827480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3176827480
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3988455697
Short name T173
Test name
Test status
Simulation time 229064142 ps
CPU time 2.54 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 237312 kb
Host smart-16d48a9f-8c60-4671-b958-83bcc5e38c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3988455697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3988455697
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1647267299
Short name T166
Test name
Test status
Simulation time 111931586 ps
CPU time 2.57 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:54 PM PDT 24
Peak memory 235948 kb
Host smart-eb77b55b-b829-4b24-b4dc-3c353e9eeb16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647267299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1647267299
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.627689776
Short name T158
Test name
Test status
Simulation time 123966296 ps
CPU time 6.27 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 237068 kb
Host smart-2af33105-7be6-489e-b267-b2f5af5fc9ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=627689776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.627689776
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2522237482
Short name T168
Test name
Test status
Simulation time 972665713 ps
CPU time 66.44 seconds
Started May 12 02:11:46 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 240380 kb
Host smart-3c5036e1-cabb-4143-ac6b-18f6ffbd3ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2522237482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2522237482
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4151232309
Short name T142
Test name
Test status
Simulation time 5156275688 ps
CPU time 196.94 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:15:12 PM PDT 24
Peak memory 265340 kb
Host smart-4ce16848-f7b5-4bc6-b5af-5417d85ca538
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151232309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4151232309
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4024340678
Short name T165
Test name
Test status
Simulation time 142016871 ps
CPU time 3.02 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:11:57 PM PDT 24
Peak memory 236864 kb
Host smart-52bed0c9-243e-4552-ba6c-d7bc5f4db4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4024340678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4024340678
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2666196976
Short name T171
Test name
Test status
Simulation time 56211003 ps
CPU time 3.73 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:09 PM PDT 24
Peak memory 237484 kb
Host smart-4356042b-82ab-4166-9bc7-1dfa0634e2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2666196976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2666196976
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2047635671
Short name T175
Test name
Test status
Simulation time 146627678 ps
CPU time 7.76 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 236880 kb
Host smart-4ded2fb8-f066-4343-97cb-b0d602e72260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2047635671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2047635671
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.493743253
Short name T169
Test name
Test status
Simulation time 372108218 ps
CPU time 47.71 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 248608 kb
Host smart-5525cf66-843b-4059-8829-00b54474a090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=493743253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.493743253
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.674102827
Short name T164
Test name
Test status
Simulation time 2589758922 ps
CPU time 34.99 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:35 PM PDT 24
Peak memory 245324 kb
Host smart-3de4d0e6-ad57-4e59-b747-fb919ce83b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=674102827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.674102827
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3328784115
Short name T787
Test name
Test status
Simulation time 2257124007 ps
CPU time 139.5 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 239204 kb
Host smart-43a22764-001e-4e58-8d2d-34511e1f877f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3328784115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3328784115
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.397279789
Short name T825
Test name
Test status
Simulation time 1636531318 ps
CPU time 205.63 seconds
Started May 12 02:11:45 PM PDT 24
Finished May 12 02:15:12 PM PDT 24
Peak memory 236752 kb
Host smart-6707553b-b27c-474b-98b8-dc8b61f61151
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=397279789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.397279789
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1434885456
Short name T760
Test name
Test status
Simulation time 220731465 ps
CPU time 5.27 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 240344 kb
Host smart-72ab61c9-0b07-46d4-99bf-7d81844523ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1434885456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1434885456
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3916522551
Short name T737
Test name
Test status
Simulation time 119240087 ps
CPU time 5.6 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 240440 kb
Host smart-d1a74ee4-65e6-449e-8b3c-2479fc39751f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916522551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3916522551
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1584643828
Short name T813
Test name
Test status
Simulation time 14624769 ps
CPU time 1.38 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:11:51 PM PDT 24
Peak memory 235916 kb
Host smart-66d9db0d-97f7-4802-b76f-0444dc5624fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1584643828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1584643828
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1639790752
Short name T767
Test name
Test status
Simulation time 505106591 ps
CPU time 38.71 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:12:29 PM PDT 24
Peak memory 248608 kb
Host smart-3c87f2dc-1d42-4208-9241-f02827ae3361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1639790752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1639790752
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1690389495
Short name T133
Test name
Test status
Simulation time 9354347882 ps
CPU time 171.84 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:14:42 PM PDT 24
Peak memory 257160 kb
Host smart-a0aab866-a369-4911-b31a-d136c56433ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690389495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1690389495
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3392222522
Short name T147
Test name
Test status
Simulation time 9382356675 ps
CPU time 678.18 seconds
Started May 12 02:11:46 PM PDT 24
Finished May 12 02:23:06 PM PDT 24
Peak memory 265360 kb
Host smart-e702f5c6-cb4e-47a7-b061-9c19a3e62892
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392222522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3392222522
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3891485080
Short name T751
Test name
Test status
Simulation time 46571106 ps
CPU time 6.02 seconds
Started May 12 02:11:45 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 247408 kb
Host smart-8c054533-9146-40d9-859d-c3a8b589b8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3891485080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3891485080
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.528112286
Short name T780
Test name
Test status
Simulation time 16804856147 ps
CPU time 228.65 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:15:39 PM PDT 24
Peak memory 240384 kb
Host smart-16ed283f-6816-4d38-86ee-261fe23316bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=528112286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.528112286
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.168301548
Short name T786
Test name
Test status
Simulation time 23712162109 ps
CPU time 372.19 seconds
Started May 12 02:11:46 PM PDT 24
Finished May 12 02:18:00 PM PDT 24
Peak memory 235948 kb
Host smart-420be3af-6972-44e1-9ae5-ad5e843d18ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=168301548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.168301548
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1888327834
Short name T184
Test name
Test status
Simulation time 46964168 ps
CPU time 6.24 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 240340 kb
Host smart-4937024e-9e4d-4237-8f8d-3c1eb386ff7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1888327834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1888327834
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.135468584
Short name T783
Test name
Test status
Simulation time 899507182 ps
CPU time 15.26 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:12:05 PM PDT 24
Peak memory 242784 kb
Host smart-3449d79f-7892-4704-a6cb-28bfa015bd3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135468584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.135468584
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1987409311
Short name T182
Test name
Test status
Simulation time 61379165 ps
CPU time 4.97 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:11:55 PM PDT 24
Peak memory 238632 kb
Host smart-aced53c9-c0a0-4137-955b-d0985984ae98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1987409311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1987409311
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1599130996
Short name T736
Test name
Test status
Simulation time 1410904984 ps
CPU time 26.07 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:12:17 PM PDT 24
Peak memory 245048 kb
Host smart-1e8b339f-b666-40b4-b2aa-b69ab7ef1324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1599130996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1599130996
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.291227506
Short name T152
Test name
Test status
Simulation time 3858693352 ps
CPU time 91.18 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 265348 kb
Host smart-13033194-3554-4af9-85d6-d894344af615
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291227506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.291227506
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.352189183
Short name T124
Test name
Test status
Simulation time 8468526183 ps
CPU time 297.34 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:16:47 PM PDT 24
Peak memory 265456 kb
Host smart-a36a9356-e51b-42bc-8894-07b04c4f0265
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352189183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.352189183
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.709913169
Short name T804
Test name
Test status
Simulation time 82323995 ps
CPU time 4.05 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 240492 kb
Host smart-2c2c0a9d-2614-472e-a5b7-31f114838edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=709913169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.709913169
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2424416899
Short name T717
Test name
Test status
Simulation time 60943548 ps
CPU time 10.54 seconds
Started May 12 02:11:55 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 253628 kb
Host smart-1a30835d-6e01-49c9-a965-981e3226190c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424416899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2424416899
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1642815726
Short name T181
Test name
Test status
Simulation time 20197404 ps
CPU time 3.44 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 239356 kb
Host smart-ee471097-adfe-443c-907a-dccf33ce972b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1642815726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1642815726
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4164736585
Short name T336
Test name
Test status
Simulation time 6590947 ps
CPU time 1.55 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 235864 kb
Host smart-ca6d8c60-59eb-4bef-b8e2-83ef75505b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164736585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4164736585
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.813552107
Short name T748
Test name
Test status
Simulation time 423839012 ps
CPU time 19.6 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:19 PM PDT 24
Peak memory 244140 kb
Host smart-0a20d42c-768c-4313-bd4e-49570fbd9e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=813552107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.813552107
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2811928197
Short name T718
Test name
Test status
Simulation time 76383218 ps
CPU time 10.84 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 253800 kb
Host smart-153136bc-b3fa-4c2a-a8ae-b6bb54ccd4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2811928197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2811928197
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3988788985
Short name T186
Test name
Test status
Simulation time 205351034 ps
CPU time 8.44 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:09 PM PDT 24
Peak memory 240252 kb
Host smart-f505a167-8f91-4981-8c4f-1e09981d12ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988788985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3988788985
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3834168321
Short name T796
Test name
Test status
Simulation time 124781699 ps
CPU time 10.09 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 236688 kb
Host smart-8d43e97a-0274-40ae-8ff7-7420ae11bd7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3834168321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3834168321
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2533056208
Short name T722
Test name
Test status
Simulation time 22161220 ps
CPU time 1.41 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 234844 kb
Host smart-32caa5bb-542e-48a2-8954-9307d7b7e349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2533056208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2533056208
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4029944140
Short name T174
Test name
Test status
Simulation time 90747099 ps
CPU time 10.32 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 248600 kb
Host smart-5dc50c80-dbd6-445a-a6a7-818442d3c663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4029944140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4029944140
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.99065543
Short name T716
Test name
Test status
Simulation time 266024626 ps
CPU time 15.57 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:15 PM PDT 24
Peak memory 248812 kb
Host smart-66f116c0-790f-4f1b-bad1-91b09b6873d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99065543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.99065543
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3191030926
Short name T822
Test name
Test status
Simulation time 72530059 ps
CPU time 5.16 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 237816 kb
Host smart-df9bd10b-27fa-4e08-83e5-f1615c0c8786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191030926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3191030926
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2047136822
Short name T740
Test name
Test status
Simulation time 24078218 ps
CPU time 4.31 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 238680 kb
Host smart-b6c7a3a6-f01b-4944-aa45-442f8161cf4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2047136822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2047136822
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3857675139
Short name T163
Test name
Test status
Simulation time 10620456 ps
CPU time 1.28 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 236852 kb
Host smart-bce66a01-16e0-42dc-a703-fc69b09cec00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857675139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3857675139
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.699500170
Short name T759
Test name
Test status
Simulation time 1461004909 ps
CPU time 45.75 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 248628 kb
Host smart-7a8fc168-e84b-4fce-9cee-870eef01fe66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=699500170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.699500170
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1981318006
Short name T703
Test name
Test status
Simulation time 279129585 ps
CPU time 19.46 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:23 PM PDT 24
Peak memory 254260 kb
Host smart-5db86a6a-729c-46c4-a2cf-56ef67d6e558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981318006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1981318006
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3594681168
Short name T766
Test name
Test status
Simulation time 548374093 ps
CPU time 38.6 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:37 PM PDT 24
Peak memory 239596 kb
Host smart-d01ac14c-b2d9-4e0e-b77a-859b12abc0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3594681168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3594681168
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2495720485
Short name T793
Test name
Test status
Simulation time 584430636 ps
CPU time 12.2 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 248612 kb
Host smart-2e2704e5-bf36-4908-87ba-6e71f3ee6bf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495720485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2495720485
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2616541168
Short name T745
Test name
Test status
Simulation time 34650336 ps
CPU time 6.16 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 235784 kb
Host smart-638d9288-a2ef-4680-9bc9-751a2d73290c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2616541168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2616541168
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.933961890
Short name T714
Test name
Test status
Simulation time 12635530 ps
CPU time 1.64 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:05 PM PDT 24
Peak memory 235968 kb
Host smart-b43d50ad-ba1f-4f10-8220-1382634fd45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=933961890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.933961890
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3017651528
Short name T709
Test name
Test status
Simulation time 358126533 ps
CPU time 11.53 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 248588 kb
Host smart-c08a129e-dab5-4390-bdfb-c91cde66f937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3017651528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3017651528
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2890438746
Short name T344
Test name
Test status
Simulation time 51995087408 ps
CPU time 1015.89 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:28:56 PM PDT 24
Peak memory 265552 kb
Host smart-7809b931-b9d9-4076-b341-8da38a97eaae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890438746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2890438746
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3456460081
Short name T812
Test name
Test status
Simulation time 1348317607 ps
CPU time 12.15 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 248568 kb
Host smart-a5076f08-bfb2-4227-9503-115cf458714c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3456460081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3456460081
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4185702427
Short name T815
Test name
Test status
Simulation time 474155251 ps
CPU time 5.55 seconds
Started May 12 02:12:03 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 240476 kb
Host smart-b1de4038-cb6e-443f-95d8-325db7a44292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185702427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4185702427
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1048534160
Short name T765
Test name
Test status
Simulation time 522743450 ps
CPU time 9.47 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:09 PM PDT 24
Peak memory 236552 kb
Host smart-56487dcc-6274-420b-9846-37941b3d85b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1048534160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1048534160
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1618152831
Short name T339
Test name
Test status
Simulation time 13441742 ps
CPU time 1.63 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 236768 kb
Host smart-94acc28d-be4e-4811-a4b9-08f11885249d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1618152831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1618152831
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.110885146
Short name T791
Test name
Test status
Simulation time 92660373 ps
CPU time 12.43 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 244144 kb
Host smart-99ed4d2f-2c40-435b-862c-9fb34b5fb852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=110885146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.110885146
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1615099573
Short name T137
Test name
Test status
Simulation time 10915266980 ps
CPU time 189.01 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:15:09 PM PDT 24
Peak memory 257168 kb
Host smart-636a34f2-3fec-4cbb-9f02-d619bf573e0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1615099573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1615099573
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1384551246
Short name T744
Test name
Test status
Simulation time 372642679 ps
CPU time 14.15 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:17 PM PDT 24
Peak memory 248620 kb
Host smart-25d43d42-4bd1-4cdc-a095-84a6c1bb39c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1384551246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1384551246
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3319647692
Short name T187
Test name
Test status
Simulation time 313640263 ps
CPU time 6.89 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 240540 kb
Host smart-80f9b095-a761-4391-b910-9024980f4b10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319647692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3319647692
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2376223046
Short name T772
Test name
Test status
Simulation time 19953142 ps
CPU time 3.75 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 235856 kb
Host smart-dbc33288-41b2-45b5-878b-7fd4417f173f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2376223046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2376223046
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1518789238
Short name T790
Test name
Test status
Simulation time 7213319747 ps
CPU time 47.84 seconds
Started May 12 02:12:05 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 248876 kb
Host smart-e29b7955-47ef-4528-b94d-befa7868a3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1518789238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1518789238
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1431499739
Short name T132
Test name
Test status
Simulation time 1107567561 ps
CPU time 89.13 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 257276 kb
Host smart-8d3e9e34-041b-438c-b4f8-5d9d7ecf5bfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1431499739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1431499739
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.30156118
Short name T150
Test name
Test status
Simulation time 14286870832 ps
CPU time 370.91 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:18:11 PM PDT 24
Peak memory 265340 kb
Host smart-00d589fc-b2aa-4a17-8532-eea38886f996
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30156118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.30156118
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2860415459
Short name T752
Test name
Test status
Simulation time 781911280 ps
CPU time 5.13 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 248844 kb
Host smart-28462373-c48e-42a1-a1b1-80cbeca8934d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2860415459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2860415459
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4017033602
Short name T771
Test name
Test status
Simulation time 552178097 ps
CPU time 39.47 seconds
Started May 12 02:12:05 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 239884 kb
Host smart-0d3f5dd4-7ea9-45a6-95c2-1406d4571f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4017033602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4017033602
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2862012000
Short name T818
Test name
Test status
Simulation time 343812536 ps
CPU time 7.94 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 239492 kb
Host smart-7350a703-e507-44c3-b2e1-94028320ff73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862012000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2862012000
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3991706465
Short name T770
Test name
Test status
Simulation time 92856082 ps
CPU time 4.16 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:05 PM PDT 24
Peak memory 238872 kb
Host smart-1ba4f105-ed75-4fdf-ad36-03eff0913625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3991706465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3991706465
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2867691528
Short name T720
Test name
Test status
Simulation time 8230889 ps
CPU time 1.44 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:12:01 PM PDT 24
Peak memory 236840 kb
Host smart-fac5ef84-89de-4994-bb26-1a1763b26217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2867691528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2867691528
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4269190011
Short name T176
Test name
Test status
Simulation time 4731191769 ps
CPU time 23.75 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:27 PM PDT 24
Peak memory 244996 kb
Host smart-d77867f4-633a-4e24-b6ab-fc8751cb8d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4269190011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.4269190011
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3298160627
Short name T130
Test name
Test status
Simulation time 3996667772 ps
CPU time 139.3 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 257172 kb
Host smart-a6c3ccc3-defa-4185-bac2-eae0c20e771a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3298160627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3298160627
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1337024793
Short name T151
Test name
Test status
Simulation time 49210922823 ps
CPU time 991.75 seconds
Started May 12 02:12:05 PM PDT 24
Finished May 12 02:28:37 PM PDT 24
Peak memory 265764 kb
Host smart-094abdd4-0ca9-406f-b917-b9a0200f6674
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337024793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1337024793
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3154647036
Short name T701
Test name
Test status
Simulation time 284851875 ps
CPU time 17.07 seconds
Started May 12 02:12:05 PM PDT 24
Finished May 12 02:12:23 PM PDT 24
Peak memory 240676 kb
Host smart-d5ba6d22-0047-4b46-a3dd-f3b4193f3915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154647036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3154647036
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.992231282
Short name T776
Test name
Test status
Simulation time 2114034085 ps
CPU time 10.48 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 237556 kb
Host smart-ade3dc60-e19b-4af9-b434-59ddb4c818a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992231282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.992231282
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.649570194
Short name T185
Test name
Test status
Simulation time 235334354 ps
CPU time 5.13 seconds
Started May 12 02:12:09 PM PDT 24
Finished May 12 02:12:15 PM PDT 24
Peak memory 236808 kb
Host smart-cbf130dd-6152-4568-9354-db23afae2373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=649570194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.649570194
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3855737962
Short name T725
Test name
Test status
Simulation time 8624047 ps
CPU time 1.56 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 236900 kb
Host smart-7341d75c-8f60-4112-86c8-e3ab87e3e20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3855737962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3855737962
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2578884264
Short name T728
Test name
Test status
Simulation time 333752178 ps
CPU time 23.44 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:12:26 PM PDT 24
Peak memory 245048 kb
Host smart-851e059b-a72b-4751-b4b4-7d3660a93170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2578884264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2578884264
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.164015196
Short name T156
Test name
Test status
Simulation time 1681543464 ps
CPU time 120.99 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 264096 kb
Host smart-ddb41320-79a4-453a-9d09-377b679d0a78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=164015196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.164015196
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2991961119
Short name T149
Test name
Test status
Simulation time 25345799883 ps
CPU time 504.35 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:20:27 PM PDT 24
Peak memory 265304 kb
Host smart-1bd15544-22a6-4208-ab1b-8d89aaabbd28
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991961119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2991961119
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2874781989
Short name T785
Test name
Test status
Simulation time 250907215 ps
CPU time 10.18 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 248132 kb
Host smart-870c694a-9a61-4a52-8ac9-f8087855d416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874781989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2874781989
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4058856424
Short name T824
Test name
Test status
Simulation time 212442613 ps
CPU time 7.79 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 255904 kb
Host smart-8edd8e9a-52ed-4b8c-99cb-13f31dba0232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058856424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4058856424
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2790161856
Short name T731
Test name
Test status
Simulation time 249881384 ps
CPU time 9.03 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 240340 kb
Host smart-ea07625d-75f1-40eb-8c75-11fee60a2e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2790161856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2790161856
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.481937203
Short name T802
Test name
Test status
Simulation time 9655158 ps
CPU time 1.55 seconds
Started May 12 02:12:03 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 234948 kb
Host smart-3a1d3b1c-f844-4c3c-92c9-116fbc5d53af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481937203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.481937203
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.19513983
Short name T713
Test name
Test status
Simulation time 241713222 ps
CPU time 17.82 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:21 PM PDT 24
Peak memory 244144 kb
Host smart-3d87acfb-667b-4358-aa00-ff9ead103c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=19513983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outs
tanding.19513983
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.188712264
Short name T345
Test name
Test status
Simulation time 8650423485 ps
CPU time 629.56 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:22:33 PM PDT 24
Peak memory 269296 kb
Host smart-5d3c6e76-1e01-47dc-aa72-a22a2338ae0f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188712264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.188712264
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3626159347
Short name T808
Test name
Test status
Simulation time 577688603 ps
CPU time 21.19 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:26 PM PDT 24
Peak memory 254308 kb
Host smart-3c57895d-fbba-483c-8633-499185e96a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3626159347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3626159347
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.506198821
Short name T170
Test name
Test status
Simulation time 54093968 ps
CPU time 2.15 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 237308 kb
Host smart-1c1f6aa6-5b35-43ad-bdd7-442a090b090c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=506198821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.506198821
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2448813179
Short name T741
Test name
Test status
Simulation time 127691881 ps
CPU time 10.22 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 250976 kb
Host smart-2c13d9b2-a377-46b9-ab4a-fd02aa3bca07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448813179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2448813179
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.834988055
Short name T341
Test name
Test status
Simulation time 36040281 ps
CPU time 5.83 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 240332 kb
Host smart-e7ee9f0d-d565-4844-894a-479071fb53a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=834988055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.834988055
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3100178708
Short name T161
Test name
Test status
Simulation time 11118442 ps
CPU time 1.64 seconds
Started May 12 02:12:09 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 235972 kb
Host smart-de3ba0ba-48b5-45d4-8420-1668fb9ffc7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3100178708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3100178708
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.995836468
Short name T820
Test name
Test status
Simulation time 183465586 ps
CPU time 20.96 seconds
Started May 12 02:12:03 PM PDT 24
Finished May 12 02:12:25 PM PDT 24
Peak memory 248608 kb
Host smart-eba9efd9-94e0-42b0-a2f9-b74ff353d32c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=995836468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.995836468
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.831841606
Short name T128
Test name
Test status
Simulation time 4111268275 ps
CPU time 198.3 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:15:20 PM PDT 24
Peak memory 271320 kb
Host smart-54e06b5e-58af-49e1-9f72-976dbd7173bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=831841606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.831841606
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1992843701
Short name T135
Test name
Test status
Simulation time 43177158404 ps
CPU time 535.29 seconds
Started May 12 02:12:02 PM PDT 24
Finished May 12 02:20:59 PM PDT 24
Peak memory 265344 kb
Host smart-f13662c0-94fc-4d34-8948-19de41c38b11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992843701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1992843701
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1212865340
Short name T747
Test name
Test status
Simulation time 50944045 ps
CPU time 6.34 seconds
Started May 12 02:12:03 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 248620 kb
Host smart-f7736d2f-63df-4693-b4eb-a8653045c7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1212865340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1212865340
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.983682787
Short name T809
Test name
Test status
Simulation time 1774754624 ps
CPU time 69.79 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 240436 kb
Host smart-85ef20d0-ef98-4693-8a05-5fb5a0f1bb96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=983682787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.983682787
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3624866348
Short name T180
Test name
Test status
Simulation time 4091950786 ps
CPU time 239.01 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 240408 kb
Host smart-5bdef3f5-65de-4091-b41a-74740bd5504f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3624866348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3624866348
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1045579692
Short name T721
Test name
Test status
Simulation time 5948003083 ps
CPU time 384.37 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:18:13 PM PDT 24
Peak memory 237108 kb
Host smart-307db18a-f08e-432c-b9e4-78d22fdc7d89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1045579692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1045579692
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1876104377
Short name T768
Test name
Test status
Simulation time 84957769 ps
CPU time 5.4 seconds
Started May 12 02:11:46 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 240340 kb
Host smart-e8cf491a-858a-4bec-b34d-4ca6ef673033
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1876104377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1876104377
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3816864482
Short name T755
Test name
Test status
Simulation time 53102975 ps
CPU time 4.76 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 239864 kb
Host smart-a6046d90-934b-4e70-9473-82b9234a6a7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816864482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3816864482
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3575876948
Short name T823
Test name
Test status
Simulation time 34709992 ps
CPU time 5.92 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:11:55 PM PDT 24
Peak memory 236748 kb
Host smart-d7fe18c5-7391-47e7-bef9-538a7efa08d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3575876948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3575876948
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3228485623
Short name T337
Test name
Test status
Simulation time 13090719 ps
CPU time 1.75 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:11:54 PM PDT 24
Peak memory 236892 kb
Host smart-f560c52a-448b-4de2-af21-e8df63dfe664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3228485623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3228485623
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3512234764
Short name T738
Test name
Test status
Simulation time 98320975 ps
CPU time 11.77 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 244972 kb
Host smart-e3f027c2-44d8-40bd-b65f-18758a2c3a7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3512234764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3512234764
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3389523123
Short name T154
Test name
Test status
Simulation time 7134614849 ps
CPU time 201.47 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:15:11 PM PDT 24
Peak memory 265356 kb
Host smart-9d3b9b8c-7cf4-43d6-80ad-2a48e70939ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3389523123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3389523123
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1277801939
Short name T125
Test name
Test status
Simulation time 12719487774 ps
CPU time 527.67 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:20:36 PM PDT 24
Peak memory 265552 kb
Host smart-f120c9b3-db83-415c-a80b-a48e4db36389
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277801939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1277801939
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1031967675
Short name T735
Test name
Test status
Simulation time 422502434 ps
CPU time 18.42 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 247856 kb
Host smart-3428d1af-8c48-446f-8a63-7b1f75f95476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1031967675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1031967675
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3385381581
Short name T734
Test name
Test status
Simulation time 37472134 ps
CPU time 2.41 seconds
Started May 12 02:11:48 PM PDT 24
Finished May 12 02:11:52 PM PDT 24
Peak memory 236980 kb
Host smart-1afd92dc-138a-4489-b2c6-55bd14af8b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3385381581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3385381581
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3602759527
Short name T761
Test name
Test status
Simulation time 32103746 ps
CPU time 1.48 seconds
Started May 12 02:12:07 PM PDT 24
Finished May 12 02:12:09 PM PDT 24
Peak memory 236880 kb
Host smart-358ee77f-c101-433c-9a50-fa4dfffef00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3602759527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3602759527
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4033579910
Short name T798
Test name
Test status
Simulation time 15818982 ps
CPU time 1.46 seconds
Started May 12 02:12:01 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 235964 kb
Host smart-56533206-a749-4d32-9067-979ac66890c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033579910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4033579910
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3219403556
Short name T723
Test name
Test status
Simulation time 6879277 ps
CPU time 1.48 seconds
Started May 12 02:12:13 PM PDT 24
Finished May 12 02:12:15 PM PDT 24
Peak memory 235972 kb
Host smart-6cc7e41d-c241-432d-93ad-1d2eae370033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219403556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3219403556
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3416036278
Short name T810
Test name
Test status
Simulation time 8103372 ps
CPU time 1.44 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 236876 kb
Host smart-acb2c1d8-bd29-4bf1-bf9c-108ba59b284b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416036278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3416036278
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3115928742
Short name T705
Test name
Test status
Simulation time 10778334 ps
CPU time 1.27 seconds
Started May 12 02:12:09 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 234944 kb
Host smart-432d1bb9-e999-4278-9cfc-379ee2519ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3115928742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3115928742
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.701468364
Short name T816
Test name
Test status
Simulation time 9339751 ps
CPU time 1.27 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 235876 kb
Host smart-fe95bc38-8cc2-4478-95a2-7665d606491e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701468364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.701468364
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3142948241
Short name T753
Test name
Test status
Simulation time 8157576 ps
CPU time 1.59 seconds
Started May 12 02:12:09 PM PDT 24
Finished May 12 02:12:11 PM PDT 24
Peak memory 235916 kb
Host smart-f30cfbbb-2918-415d-b439-77bfa1fdcf88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3142948241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3142948241
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.695741805
Short name T234
Test name
Test status
Simulation time 12637303 ps
CPU time 1.32 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 236892 kb
Host smart-116bdd04-64b6-4324-bbf5-9ffc59e81ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=695741805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.695741805
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4104508830
Short name T784
Test name
Test status
Simulation time 8707208 ps
CPU time 1.38 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 235976 kb
Host smart-c39b9a41-a553-4c1f-9d03-682b13b2a55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4104508830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4104508830
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.767726232
Short name T183
Test name
Test status
Simulation time 7450963543 ps
CPU time 346.25 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:17:39 PM PDT 24
Peak memory 240788 kb
Host smart-44205274-b44b-400d-83c7-4e73f5f87dd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=767726232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.767726232
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3237353376
Short name T742
Test name
Test status
Simulation time 30766294105 ps
CPU time 477.46 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:19:49 PM PDT 24
Peak memory 235936 kb
Host smart-8dc5cfa7-df74-4203-b471-17a201d24a71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3237353376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3237353376
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1135293964
Short name T762
Test name
Test status
Simulation time 81203115 ps
CPU time 4.17 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:11:57 PM PDT 24
Peak memory 240324 kb
Host smart-8fb63312-c7b6-4c8b-82d3-640a6bf227fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1135293964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1135293964
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.343366594
Short name T814
Test name
Test status
Simulation time 96817937 ps
CPU time 5.83 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:57 PM PDT 24
Peak memory 238984 kb
Host smart-6b019fe7-da6e-46cb-acd8-2ece3c777395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343366594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.343366594
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1994857458
Short name T749
Test name
Test status
Simulation time 133085377 ps
CPU time 5.34 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:00 PM PDT 24
Peak memory 236696 kb
Host smart-b1690f93-41a2-43a0-adf3-f87dbed4e5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1994857458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1994857458
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3662252612
Short name T769
Test name
Test status
Simulation time 34572776 ps
CPU time 1.48 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 236892 kb
Host smart-ccd9b71d-931d-4556-b622-88a6e4a5cc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3662252612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3662252612
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3873581147
Short name T704
Test name
Test status
Simulation time 261179629 ps
CPU time 12.42 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:12:05 PM PDT 24
Peak memory 245108 kb
Host smart-83955cdc-8ce9-4dc0-b453-40bf6a8874d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3873581147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3873581147
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1783155451
Short name T148
Test name
Test status
Simulation time 779627975 ps
CPU time 93.08 seconds
Started May 12 02:11:47 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 257132 kb
Host smart-5410e19e-70b0-4074-97e5-1eb3a9b36702
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783155451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1783155451
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.98297929
Short name T155
Test name
Test status
Simulation time 26692948143 ps
CPU time 518.06 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:20:29 PM PDT 24
Peak memory 265464 kb
Host smart-898feece-c015-4228-9405-07930a74db41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98297929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.98297929
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3349151901
Short name T795
Test name
Test status
Simulation time 370366599 ps
CPU time 25.79 seconds
Started May 12 02:11:49 PM PDT 24
Finished May 12 02:12:16 PM PDT 24
Peak memory 251984 kb
Host smart-d6df9e4f-e953-47e9-9668-af87b371bf40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3349151901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3349151901
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1851986782
Short name T162
Test name
Test status
Simulation time 12917120 ps
CPU time 1.75 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 237112 kb
Host smart-94b20c11-cbfa-4460-816f-d7d2d5ebd30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851986782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1851986782
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4065451884
Short name T799
Test name
Test status
Simulation time 9373962 ps
CPU time 1.44 seconds
Started May 12 02:12:12 PM PDT 24
Finished May 12 02:12:14 PM PDT 24
Peak memory 236900 kb
Host smart-3cf834be-ef7e-47f7-88fc-eddc99e3d1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065451884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4065451884
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1950982337
Short name T727
Test name
Test status
Simulation time 6857370 ps
CPU time 1.47 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 235868 kb
Host smart-bcf28d4b-b298-4664-83d1-1331e4ed0621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1950982337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1950982337
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1371846777
Short name T334
Test name
Test status
Simulation time 8667685 ps
CPU time 1.41 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 236900 kb
Host smart-b9f0a0bb-6558-4d54-ad22-c0e2b9f68624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371846777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1371846777
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.190888621
Short name T777
Test name
Test status
Simulation time 15198496 ps
CPU time 1.7 seconds
Started May 12 02:12:06 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 235984 kb
Host smart-0f872a7f-8ab3-4f54-b2c2-0e0ffe5d6249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190888621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.190888621
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2507492159
Short name T819
Test name
Test status
Simulation time 7622926 ps
CPU time 1.3 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:14 PM PDT 24
Peak memory 235960 kb
Host smart-84c90a19-7deb-482f-9b76-b9359df6f638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2507492159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2507492159
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3430754033
Short name T743
Test name
Test status
Simulation time 25076809 ps
CPU time 1.24 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 234824 kb
Host smart-1b009bae-98ca-4906-ba54-2e0215976f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430754033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3430754033
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1588057679
Short name T764
Test name
Test status
Simulation time 7810078 ps
CPU time 1.37 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 235944 kb
Host smart-faaa0b59-9070-4e43-9a19-349935155579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1588057679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1588057679
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1893041990
Short name T775
Test name
Test status
Simulation time 12480433 ps
CPU time 1.34 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 235956 kb
Host smart-618eb252-6c0b-4b61-b494-bb23ca367503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1893041990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1893041990
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3031290106
Short name T803
Test name
Test status
Simulation time 19916255 ps
CPU time 1.47 seconds
Started May 12 02:12:13 PM PDT 24
Finished May 12 02:12:15 PM PDT 24
Peak memory 236888 kb
Host smart-823f35dd-c569-4c79-b97a-121482d2c375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031290106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3031290106
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1651611169
Short name T807
Test name
Test status
Simulation time 4639120012 ps
CPU time 149.58 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:14:24 PM PDT 24
Peak memory 240404 kb
Host smart-5fe5946c-894e-4dcf-91a9-964faf05bb9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1651611169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1651611169
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2790879092
Short name T811
Test name
Test status
Simulation time 5710547883 ps
CPU time 389.66 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:18:23 PM PDT 24
Peak memory 236888 kb
Host smart-65171e05-a875-4f8f-bd1b-21a71428d90a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2790879092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2790879092
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.761856731
Short name T708
Test name
Test status
Simulation time 69892332 ps
CPU time 5.84 seconds
Started May 12 02:11:55 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 240320 kb
Host smart-3ace339a-b22e-4fe4-8fde-7990795f75d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=761856731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.761856731
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.721607947
Short name T826
Test name
Test status
Simulation time 74491009 ps
CPU time 5.81 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:57 PM PDT 24
Peak memory 240348 kb
Host smart-f935b63a-1538-4b3a-b9be-61331c118633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721607947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.721607947
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.765225238
Short name T779
Test name
Test status
Simulation time 778280375 ps
CPU time 7.59 seconds
Started May 12 02:11:55 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 236776 kb
Host smart-5501b19e-d64c-4b1d-8b3b-e9a2316da1fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=765225238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.765225238
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2978031911
Short name T792
Test name
Test status
Simulation time 7965797 ps
CPU time 1.45 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 235924 kb
Host smart-51c1c7b0-ccf1-4dde-b36a-58dfaf2e430f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2978031911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2978031911
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2560457347
Short name T801
Test name
Test status
Simulation time 428954071 ps
CPU time 15 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:20 PM PDT 24
Peak memory 248820 kb
Host smart-aa6e41b5-6fb4-490d-82b4-40ec83afab9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2560457347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2560457347
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2222468256
Short name T146
Test name
Test status
Simulation time 9096029255 ps
CPU time 331.84 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:17:24 PM PDT 24
Peak memory 265328 kb
Host smart-9aef1a5e-7340-477b-9721-f0eaf336f007
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222468256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2222468256
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.843744478
Short name T733
Test name
Test status
Simulation time 921637424 ps
CPU time 16.54 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:18 PM PDT 24
Peak memory 249912 kb
Host smart-1c698c78-ac87-4041-8c8c-08a3e73b5110
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=843744478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.843744478
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3229720626
Short name T729
Test name
Test status
Simulation time 7444171 ps
CPU time 1.42 seconds
Started May 12 02:12:08 PM PDT 24
Finished May 12 02:12:10 PM PDT 24
Peak memory 236860 kb
Host smart-aba7b63d-2c3e-4319-aafe-8b8286affcd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3229720626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3229720626
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2586788761
Short name T757
Test name
Test status
Simulation time 8377133 ps
CPU time 1.58 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 236908 kb
Host smart-83df662b-1a44-41ec-8d60-63e889bc654c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2586788761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2586788761
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2414299012
Short name T806
Test name
Test status
Simulation time 7514317 ps
CPU time 1.33 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 235944 kb
Host smart-529507ee-e810-47df-a8f3-b732090f64d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2414299012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2414299012
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1098759695
Short name T711
Test name
Test status
Simulation time 22076245 ps
CPU time 1.29 seconds
Started May 12 02:12:05 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 234904 kb
Host smart-fc5ac386-5789-4cc2-9e0d-0669cb0de748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098759695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1098759695
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4266071648
Short name T797
Test name
Test status
Simulation time 9991000 ps
CPU time 1.49 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:06 PM PDT 24
Peak memory 236888 kb
Host smart-bbbe70a0-3f5e-467b-b734-fbf396fb60c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4266071648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4266071648
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.229841038
Short name T794
Test name
Test status
Simulation time 23765149 ps
CPU time 1.37 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 236768 kb
Host smart-58ee7f20-482f-4aa1-b192-7970fd8dd8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229841038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.229841038
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.34565336
Short name T719
Test name
Test status
Simulation time 16388064 ps
CPU time 1.31 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 234928 kb
Host smart-31e77858-261c-4304-bd82-7c8273d797cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34565336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.34565336
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2200876484
Short name T338
Test name
Test status
Simulation time 8201091 ps
CPU time 1.52 seconds
Started May 12 02:12:06 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 234928 kb
Host smart-b125276e-1f69-4a72-af36-425342f93d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2200876484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2200876484
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1829833040
Short name T750
Test name
Test status
Simulation time 19196496 ps
CPU time 1.4 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 236840 kb
Host smart-b7b208ce-4fc9-41af-81c4-3ab9164c897c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1829833040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1829833040
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2667421615
Short name T756
Test name
Test status
Simulation time 11551356 ps
CPU time 1.35 seconds
Started May 12 02:12:16 PM PDT 24
Finished May 12 02:12:18 PM PDT 24
Peak memory 236900 kb
Host smart-81cf837f-5237-49ae-96c3-6052d1d996f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2667421615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2667421615
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1963432576
Short name T821
Test name
Test status
Simulation time 232546489 ps
CPU time 5.46 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:11:59 PM PDT 24
Peak memory 237108 kb
Host smart-1d5cd86e-9964-47a2-bde0-a79a33b4f29d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963432576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1963432576
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.150352021
Short name T774
Test name
Test status
Simulation time 23036425 ps
CPU time 3.67 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:00 PM PDT 24
Peak memory 239492 kb
Host smart-c57e4e7a-9066-42ea-b761-33105f402112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=150352021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.150352021
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2912823422
Short name T746
Test name
Test status
Simulation time 6477438 ps
CPU time 1.43 seconds
Started May 12 02:11:50 PM PDT 24
Finished May 12 02:11:53 PM PDT 24
Peak memory 235916 kb
Host smart-1cc41855-2dc1-4f88-b2a4-ca1accb236f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2912823422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2912823422
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1482966626
Short name T706
Test name
Test status
Simulation time 4764334149 ps
CPU time 19.57 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:15 PM PDT 24
Peak memory 248580 kb
Host smart-f857d237-64ca-4637-b8cc-04dfe17288bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1482966626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1482966626
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3589794344
Short name T139
Test name
Test status
Simulation time 747137492 ps
CPU time 82.64 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 256904 kb
Host smart-1a3e55de-c93b-4e95-9798-d1005536bb83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3589794344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3589794344
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1604905230
Short name T726
Test name
Test status
Simulation time 1331821394 ps
CPU time 8.46 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 248752 kb
Host smart-23145ca7-d294-435c-b0b3-ea243565fdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1604905230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1604905230
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1262880260
Short name T805
Test name
Test status
Simulation time 122056363 ps
CPU time 9.65 seconds
Started May 12 02:11:52 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 240516 kb
Host smart-4e3398e2-9c1d-4ae8-a446-9313c70a6ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262880260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1262880260
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1954994175
Short name T778
Test name
Test status
Simulation time 496186166 ps
CPU time 9.5 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:12:02 PM PDT 24
Peak memory 236736 kb
Host smart-08d05732-30bd-4e24-bf0d-848a2725b9bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1954994175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1954994175
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2851397902
Short name T758
Test name
Test status
Simulation time 13234425 ps
CPU time 1.44 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 235956 kb
Host smart-b60d4883-a9c7-416f-a405-91aa5e3ff1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2851397902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2851397902
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3331622729
Short name T732
Test name
Test status
Simulation time 337110208 ps
CPU time 10.87 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 244020 kb
Host smart-b802fd55-f50b-4731-9880-db9909e142cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3331622729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3331622729
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3129739742
Short name T702
Test name
Test status
Simulation time 433320018 ps
CPU time 8.28 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 250872 kb
Host smart-04baa439-f4ec-423e-9bae-24d14441753f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3129739742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3129739742
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.715066823
Short name T343
Test name
Test status
Simulation time 69597981 ps
CPU time 6.11 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 237896 kb
Host smart-70d2aae7-a912-477d-8d01-8de6fad8c6eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715066823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.715066823
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.791760624
Short name T724
Test name
Test status
Simulation time 105644709 ps
CPU time 6.63 seconds
Started May 12 02:11:55 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 236784 kb
Host smart-22d221f2-a6ea-4afe-8c06-0017181abfa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=791760624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.791760624
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2764656659
Short name T730
Test name
Test status
Simulation time 15951424 ps
CPU time 1.32 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:11:56 PM PDT 24
Peak memory 234852 kb
Host smart-9d9159cd-eaef-41f4-a34a-5f17d06b5d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764656659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2764656659
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1088764736
Short name T754
Test name
Test status
Simulation time 178328301 ps
CPU time 11.42 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 244160 kb
Host smart-a099b27a-dafb-4c48-84b4-f7e3f961f78c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1088764736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1088764736
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2647704905
Short name T157
Test name
Test status
Simulation time 1955434188 ps
CPU time 131.95 seconds
Started May 12 02:11:51 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 257120 kb
Host smart-6c5ee591-3dc2-44b7-925e-988b7dab1ce9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2647704905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2647704905
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3498781663
Short name T782
Test name
Test status
Simulation time 492837938 ps
CPU time 10.02 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 248588 kb
Host smart-91ef8801-89d8-49af-a66a-16f09be1b6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3498781663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3498781663
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3598050484
Short name T788
Test name
Test status
Simulation time 139300634 ps
CPU time 5.83 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 242436 kb
Host smart-9e0e712a-cde8-4a99-82d2-d92018c7f18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598050484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3598050484
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.996782323
Short name T800
Test name
Test status
Simulation time 115097334 ps
CPU time 6.57 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 237000 kb
Host smart-a78c9a45-b3f9-427a-944d-3b718cd5c79d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=996782323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.996782323
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1934276132
Short name T781
Test name
Test status
Simulation time 11897308 ps
CPU time 1.35 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:11:58 PM PDT 24
Peak memory 235940 kb
Host smart-421e169c-bb72-4ce5-b4c4-902f1f243d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1934276132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1934276132
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2229413672
Short name T817
Test name
Test status
Simulation time 622794109 ps
CPU time 45.51 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 244116 kb
Host smart-7761671e-cda1-40e5-8025-b34eb2178b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2229413672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2229413672
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3493006909
Short name T141
Test name
Test status
Simulation time 70819444897 ps
CPU time 370.19 seconds
Started May 12 02:11:58 PM PDT 24
Finished May 12 02:18:11 PM PDT 24
Peak memory 265388 kb
Host smart-2496f43b-d8ac-4aed-a9d3-ff2fee70d631
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3493006909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3493006909
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2466651331
Short name T712
Test name
Test status
Simulation time 821788002 ps
CPU time 12.77 seconds
Started May 12 02:11:59 PM PDT 24
Finished May 12 02:12:14 PM PDT 24
Peak memory 248760 kb
Host smart-7d090e77-898e-45ad-82cb-084ed5adfd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2466651331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2466651331
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.175149596
Short name T789
Test name
Test status
Simulation time 56231456 ps
CPU time 4.16 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:01 PM PDT 24
Peak memory 236820 kb
Host smart-9e5a0c5e-0eb8-47af-abb1-2253fbccc853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=175149596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.175149596
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.831919694
Short name T342
Test name
Test status
Simulation time 1026192517 ps
CPU time 8.94 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:04 PM PDT 24
Peak memory 238672 kb
Host smart-d4e05f27-e061-4553-94a4-e62a45fee7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831919694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.831919694
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.258600659
Short name T739
Test name
Test status
Simulation time 65209548 ps
CPU time 5.04 seconds
Started May 12 02:11:56 PM PDT 24
Finished May 12 02:12:03 PM PDT 24
Peak memory 236804 kb
Host smart-0aa387df-ea08-49a1-8156-48ef29bdd410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=258600659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.258600659
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2607663365
Short name T715
Test name
Test status
Simulation time 15572255 ps
CPU time 1.52 seconds
Started May 12 02:12:04 PM PDT 24
Finished May 12 02:12:07 PM PDT 24
Peak memory 236152 kb
Host smart-4a1d1de7-4c5e-4a3e-809e-b63e1fa8a19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2607663365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2607663365
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1735375555
Short name T773
Test name
Test status
Simulation time 578654106 ps
CPU time 39.6 seconds
Started May 12 02:11:53 PM PDT 24
Finished May 12 02:12:34 PM PDT 24
Peak memory 244116 kb
Host smart-eaf195a3-9cd3-4447-982b-d280bc717184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1735375555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1735375555
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1465294146
Short name T140
Test name
Test status
Simulation time 1590574059 ps
CPU time 101.42 seconds
Started May 12 02:11:55 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 256828 kb
Host smart-6d10aa03-b71c-49a6-a426-d6e06a1fe93e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465294146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1465294146
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.659363709
Short name T153
Test name
Test status
Simulation time 6033191464 ps
CPU time 524.03 seconds
Started May 12 02:11:57 PM PDT 24
Finished May 12 02:20:43 PM PDT 24
Peak memory 265432 kb
Host smart-8711fadd-25ed-4f41-bc12-70e26d95f732
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659363709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.659363709
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1514839531
Short name T707
Test name
Test status
Simulation time 97758186 ps
CPU time 12.3 seconds
Started May 12 02:11:54 PM PDT 24
Finished May 12 02:12:08 PM PDT 24
Peak memory 248164 kb
Host smart-64f5fec7-5f4c-4734-b4ea-53106d4d1827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1514839531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1514839531
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.168853779
Short name T679
Test name
Test status
Simulation time 36641129949 ps
CPU time 1063.49 seconds
Started May 12 02:54:35 PM PDT 24
Finished May 12 03:12:19 PM PDT 24
Peak memory 273372 kb
Host smart-ec0bd488-21b1-41a0-9bf1-01a227a6ebbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168853779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.168853779
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1990864900
Short name T573
Test name
Test status
Simulation time 2155957892 ps
CPU time 24.27 seconds
Started May 12 02:54:39 PM PDT 24
Finished May 12 02:55:04 PM PDT 24
Peak memory 240744 kb
Host smart-17ff484d-55a4-4c04-b35d-e112f52a2fc4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1990864900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1990864900
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2878589770
Short name T442
Test name
Test status
Simulation time 2406194596 ps
CPU time 121.7 seconds
Started May 12 02:54:35 PM PDT 24
Finished May 12 02:56:37 PM PDT 24
Peak memory 256820 kb
Host smart-b8852877-65d9-40e9-8983-030c7e421b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28785
89770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2878589770
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.578987916
Short name T581
Test name
Test status
Simulation time 103566559 ps
CPU time 7.2 seconds
Started May 12 02:54:35 PM PDT 24
Finished May 12 02:54:43 PM PDT 24
Peak memory 252256 kb
Host smart-892f46a8-ee46-4d7e-a6b8-4be1e5199595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57898
7916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.578987916
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.122821552
Short name T578
Test name
Test status
Simulation time 12839836911 ps
CPU time 1108.99 seconds
Started May 12 02:54:38 PM PDT 24
Finished May 12 03:13:08 PM PDT 24
Peak memory 269276 kb
Host smart-1ce8e4b2-14ca-4366-b954-6ea5f128ff17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122821552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.122821552
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3372468997
Short name T361
Test name
Test status
Simulation time 2264363850 ps
CPU time 43.68 seconds
Started May 12 02:54:32 PM PDT 24
Finished May 12 02:55:16 PM PDT 24
Peak memory 248808 kb
Host smart-b6768cbf-2c43-495e-beee-9f3952227aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
68997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3372468997
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3473394921
Short name T577
Test name
Test status
Simulation time 1047806985 ps
CPU time 53.54 seconds
Started May 12 02:54:32 PM PDT 24
Finished May 12 02:55:26 PM PDT 24
Peak memory 249060 kb
Host smart-268bc9f9-0fdc-4c05-8448-708b536e611d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34733
94921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3473394921
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.639511375
Short name T531
Test name
Test status
Simulation time 376377639 ps
CPU time 14.63 seconds
Started May 12 02:54:35 PM PDT 24
Finished May 12 02:54:50 PM PDT 24
Peak memory 248768 kb
Host smart-5c247631-a0fc-42f9-b533-3c0e210d8b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63951
1375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.639511375
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3336359599
Short name T220
Test name
Test status
Simulation time 244611722 ps
CPU time 15.92 seconds
Started May 12 02:54:33 PM PDT 24
Finished May 12 02:54:49 PM PDT 24
Peak memory 254884 kb
Host smart-f89b1296-b8fd-48a5-871e-0c13c5567cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
59599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3336359599
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.871001485
Short name T261
Test name
Test status
Simulation time 19868538008 ps
CPU time 1011.21 seconds
Started May 12 02:54:45 PM PDT 24
Finished May 12 03:11:37 PM PDT 24
Peak memory 265156 kb
Host smart-3ca49ab1-345a-4e7c-aa50-ffcfca6f6edf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871001485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.871001485
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1578702067
Short name T99
Test name
Test status
Simulation time 76334444854 ps
CPU time 7676.61 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 05:02:40 PM PDT 24
Peak memory 395100 kb
Host smart-a861a38e-3230-40fa-8d0f-f186dc7fde03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578702067 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1578702067
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3515437447
Short name T529
Test name
Test status
Simulation time 191356767684 ps
CPU time 1946.66 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 03:27:09 PM PDT 24
Peak memory 273380 kb
Host smart-2435f4d9-f423-41f1-8537-994ac6fce588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515437447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3515437447
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.210439467
Short name T219
Test name
Test status
Simulation time 186103835 ps
CPU time 11.45 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 02:54:57 PM PDT 24
Peak memory 248724 kb
Host smart-1189e6ee-71ed-49dd-9306-d2753ef15f91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=210439467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.210439467
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1016022771
Short name T515
Test name
Test status
Simulation time 372246076 ps
CPU time 27.4 seconds
Started May 12 02:54:43 PM PDT 24
Finished May 12 02:55:11 PM PDT 24
Peak memory 256024 kb
Host smart-62e234f8-1721-474d-ad7b-e3d3860e6fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
22771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1016022771
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3962091968
Short name T489
Test name
Test status
Simulation time 820695244 ps
CPU time 27.43 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 02:55:09 PM PDT 24
Peak memory 248784 kb
Host smart-9ff01f93-0fa7-4f61-9ba9-0a82319a2085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39620
91968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3962091968
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1896171749
Short name T492
Test name
Test status
Simulation time 162629391754 ps
CPU time 2692.75 seconds
Started May 12 02:54:45 PM PDT 24
Finished May 12 03:39:38 PM PDT 24
Peak memory 283372 kb
Host smart-146b8a27-bf50-488c-9c7a-e87d778d7344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896171749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1896171749
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3459746021
Short name T575
Test name
Test status
Simulation time 96155173149 ps
CPU time 3097.75 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 03:46:21 PM PDT 24
Peak memory 288400 kb
Host smart-2b5e9738-77cd-46fc-a1f9-fbfc9deb7377
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459746021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3459746021
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1617753328
Short name T619
Test name
Test status
Simulation time 284330658 ps
CPU time 11.88 seconds
Started May 12 02:54:43 PM PDT 24
Finished May 12 02:54:55 PM PDT 24
Peak memory 248720 kb
Host smart-e38bc213-f58e-4ae6-b169-fc8550fa1ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16177
53328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1617753328
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2048854295
Short name T652
Test name
Test status
Simulation time 2275899227 ps
CPU time 13.58 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 02:54:56 PM PDT 24
Peak memory 248804 kb
Host smart-cdd00855-ee0c-4912-9f83-425deef0e115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
54295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2048854295
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2809727068
Short name T566
Test name
Test status
Simulation time 63889605 ps
CPU time 9.04 seconds
Started May 12 02:54:42 PM PDT 24
Finished May 12 02:54:52 PM PDT 24
Peak memory 252712 kb
Host smart-b53c31a1-ad7f-44ee-9e09-9c44c8c4fb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
27068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2809727068
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3609607371
Short name T563
Test name
Test status
Simulation time 834867784 ps
CPU time 18.15 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 02:55:03 PM PDT 24
Peak memory 248712 kb
Host smart-6633d63b-db92-40ce-8ed5-b6e8d43638b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
07371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3609607371
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.569674066
Short name T205
Test name
Test status
Simulation time 38821165 ps
CPU time 2.29 seconds
Started May 12 02:55:40 PM PDT 24
Finished May 12 02:55:43 PM PDT 24
Peak memory 248916 kb
Host smart-5026c9b4-0c49-482a-b47e-9842ebddc39c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=569674066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.569674066
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3142179557
Short name T413
Test name
Test status
Simulation time 114182616 ps
CPU time 7.51 seconds
Started May 12 02:55:40 PM PDT 24
Finished May 12 02:55:48 PM PDT 24
Peak memory 248708 kb
Host smart-4254c0c5-3a49-4c31-955c-fa83e0f26637
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3142179557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3142179557
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.262371144
Short name T415
Test name
Test status
Simulation time 244169176 ps
CPU time 23.26 seconds
Started May 12 02:55:39 PM PDT 24
Finished May 12 02:56:03 PM PDT 24
Peak memory 256404 kb
Host smart-b06f5887-0525-4260-9c46-b3c6f951e878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26237
1144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.262371144
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2021184280
Short name T358
Test name
Test status
Simulation time 1411990714 ps
CPU time 26.33 seconds
Started May 12 02:55:35 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 248776 kb
Host smart-cbd0d899-9e07-43e5-8150-3ad826711cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
84280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2021184280
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.651689723
Short name T359
Test name
Test status
Simulation time 79392290122 ps
CPU time 1524.04 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 03:21:08 PM PDT 24
Peak memory 266736 kb
Host smart-8bf35a27-45bc-434a-997a-d8ed3043af4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651689723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.651689723
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1232459765
Short name T294
Test name
Test status
Simulation time 8167684914 ps
CPU time 334.51 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 03:01:18 PM PDT 24
Peak memory 247928 kb
Host smart-6d159a8a-3749-4152-a83a-bd926a6bbf10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232459765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1232459765
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.153871937
Short name T111
Test name
Test status
Simulation time 1599899262 ps
CPU time 16.9 seconds
Started May 12 02:55:37 PM PDT 24
Finished May 12 02:55:55 PM PDT 24
Peak memory 248708 kb
Host smart-b3a2bfb8-8d63-4352-b0bf-21420cc353d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
1937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.153871937
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4173842767
Short name T114
Test name
Test status
Simulation time 3298108723 ps
CPU time 58.05 seconds
Started May 12 02:55:37 PM PDT 24
Finished May 12 02:56:36 PM PDT 24
Peak memory 248744 kb
Host smart-0b8a8380-a64d-423b-95db-6ad1c6fadce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41738
42767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4173842767
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1844996149
Short name T384
Test name
Test status
Simulation time 872135752 ps
CPU time 16.85 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 02:56:00 PM PDT 24
Peak memory 248716 kb
Host smart-b1e1135f-7f8f-49c4-886d-2b67bcc94d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18449
96149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1844996149
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3884321579
Short name T409
Test name
Test status
Simulation time 439797210631 ps
CPU time 3429.24 seconds
Started May 12 02:55:39 PM PDT 24
Finished May 12 03:52:50 PM PDT 24
Peak memory 289420 kb
Host smart-05487402-b2de-42ca-81e5-8bfdb812ac27
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884321579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3884321579
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.667061310
Short name T198
Test name
Test status
Simulation time 58535306 ps
CPU time 3.11 seconds
Started May 12 02:55:44 PM PDT 24
Finished May 12 02:55:47 PM PDT 24
Peak memory 248864 kb
Host smart-2b8ff75a-9c89-40ad-a300-f9bb6081603e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=667061310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.667061310
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.508863650
Short name T693
Test name
Test status
Simulation time 77515348648 ps
CPU time 1227.28 seconds
Started May 12 02:55:45 PM PDT 24
Finished May 12 03:16:13 PM PDT 24
Peak memory 281608 kb
Host smart-d996d9a6-e8b4-40ab-b8f1-fdf562774b59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508863650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.508863650
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2703852093
Short name T562
Test name
Test status
Simulation time 2881356209 ps
CPU time 158.57 seconds
Started May 12 02:55:53 PM PDT 24
Finished May 12 02:58:32 PM PDT 24
Peak memory 256708 kb
Host smart-bdd32823-a71f-404d-91f1-3eb0a4034555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27038
52093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2703852093
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.475894167
Short name T253
Test name
Test status
Simulation time 7740224397 ps
CPU time 49.34 seconds
Started May 12 02:55:52 PM PDT 24
Finished May 12 02:56:42 PM PDT 24
Peak memory 249004 kb
Host smart-10882cbc-23a3-4e30-98f1-e699d410c67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47589
4167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.475894167
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1791819479
Short name T291
Test name
Test status
Simulation time 47496536365 ps
CPU time 1657.04 seconds
Started May 12 02:55:52 PM PDT 24
Finished May 12 03:23:30 PM PDT 24
Peak memory 267224 kb
Host smart-91577548-4866-451c-a693-c553d695373f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791819479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1791819479
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2970349793
Short name T392
Test name
Test status
Simulation time 143606036414 ps
CPU time 2349.59 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 03:34:53 PM PDT 24
Peak memory 272972 kb
Host smart-969c66ab-c99d-449e-8ffe-dcda2b854e70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970349793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2970349793
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2549889171
Short name T641
Test name
Test status
Simulation time 14096379870 ps
CPU time 537.34 seconds
Started May 12 02:55:52 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 248180 kb
Host smart-f4dbafc2-942a-498c-a669-2d1280f91467
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549889171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2549889171
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2241975650
Short name T556
Test name
Test status
Simulation time 470836084 ps
CPU time 9.55 seconds
Started May 12 02:55:45 PM PDT 24
Finished May 12 02:55:55 PM PDT 24
Peak memory 248744 kb
Host smart-8bdd97d8-c4b9-4d7f-ac5a-646ece9536f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
75650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2241975650
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.81711546
Short name T483
Test name
Test status
Simulation time 1247940287 ps
CPU time 68.39 seconds
Started May 12 02:55:42 PM PDT 24
Finished May 12 02:56:51 PM PDT 24
Peak memory 256080 kb
Host smart-ec946683-8899-40b9-8155-fb3f50a5eb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81711
546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.81711546
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4228838821
Short name T246
Test name
Test status
Simulation time 1138792584 ps
CPU time 30.21 seconds
Started May 12 02:55:45 PM PDT 24
Finished May 12 02:56:15 PM PDT 24
Peak memory 247552 kb
Host smart-368145c1-deab-4390-a05d-2826aeb39218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42288
38821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4228838821
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1899445665
Short name T673
Test name
Test status
Simulation time 628411520 ps
CPU time 37.66 seconds
Started May 12 02:55:44 PM PDT 24
Finished May 12 02:56:22 PM PDT 24
Peak memory 248744 kb
Host smart-7393fe05-91a0-4791-b4f7-6464f7e66978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
45665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1899445665
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3880789014
Short name T104
Test name
Test status
Simulation time 47173164183 ps
CPU time 2969.88 seconds
Started May 12 02:55:44 PM PDT 24
Finished May 12 03:45:15 PM PDT 24
Peak memory 281604 kb
Host smart-94137bbe-d5dd-421c-aa55-fd16e8b55e61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880789014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3880789014
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1683666990
Short name T201
Test name
Test status
Simulation time 84982579 ps
CPU time 4.03 seconds
Started May 12 02:55:54 PM PDT 24
Finished May 12 02:55:58 PM PDT 24
Peak memory 248900 kb
Host smart-27058f1c-a9ca-40e2-ba69-ee891428b4eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683666990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1683666990
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1624365191
Short name T549
Test name
Test status
Simulation time 16551227792 ps
CPU time 1425.43 seconds
Started May 12 02:55:46 PM PDT 24
Finished May 12 03:19:33 PM PDT 24
Peak memory 288428 kb
Host smart-d8011ab6-17c9-4457-803d-631d04aad1bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624365191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1624365191
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1027674284
Short name T502
Test name
Test status
Simulation time 2199629969 ps
CPU time 27.28 seconds
Started May 12 02:55:51 PM PDT 24
Finished May 12 02:56:19 PM PDT 24
Peak memory 248812 kb
Host smart-a6885aa1-f341-4d20-9f5d-71d93f5b6d6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1027674284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1027674284
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2255741498
Short name T487
Test name
Test status
Simulation time 18601623216 ps
CPU time 295.27 seconds
Started May 12 02:55:46 PM PDT 24
Finished May 12 03:00:42 PM PDT 24
Peak memory 250216 kb
Host smart-e0a84614-d888-4f58-b655-d24c2f7b0aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
41498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2255741498
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.902185045
Short name T404
Test name
Test status
Simulation time 3179926322 ps
CPU time 53.63 seconds
Started May 12 02:55:47 PM PDT 24
Finished May 12 02:56:41 PM PDT 24
Peak memory 248828 kb
Host smart-bda996e3-14bb-43a2-9f65-cc720952df3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90218
5045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.902185045
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3853146995
Short name T629
Test name
Test status
Simulation time 47234042374 ps
CPU time 1634.57 seconds
Started May 12 02:55:52 PM PDT 24
Finished May 12 03:23:08 PM PDT 24
Peak memory 289644 kb
Host smart-1b9411c9-2aae-4b3d-8576-36f8f3c5880a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853146995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3853146995
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4121230816
Short name T697
Test name
Test status
Simulation time 131188497811 ps
CPU time 2609.77 seconds
Started May 12 02:55:54 PM PDT 24
Finished May 12 03:39:25 PM PDT 24
Peak memory 281532 kb
Host smart-38b8a7ef-4540-4382-bbdb-bba1066e24ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121230816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4121230816
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.388886473
Short name T224
Test name
Test status
Simulation time 9516604401 ps
CPU time 380.81 seconds
Started May 12 02:55:47 PM PDT 24
Finished May 12 03:02:09 PM PDT 24
Peak memory 248352 kb
Host smart-418ddf7b-78be-4b10-856f-7a6019a0767c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388886473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.388886473
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1092993031
Short name T221
Test name
Test status
Simulation time 2019777290 ps
CPU time 53.71 seconds
Started May 12 02:55:47 PM PDT 24
Finished May 12 02:56:42 PM PDT 24
Peak memory 256296 kb
Host smart-37c25ddc-0a62-456d-9143-04f798b52d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
93031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1092993031
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4280034545
Short name T583
Test name
Test status
Simulation time 334368152 ps
CPU time 20.46 seconds
Started May 12 02:55:48 PM PDT 24
Finished May 12 02:56:09 PM PDT 24
Peak memory 256248 kb
Host smart-f12cfa69-78b6-4789-b5e7-c4a2e5dcd1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
34545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4280034545
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.533302545
Short name T84
Test name
Test status
Simulation time 937649875 ps
CPU time 35.01 seconds
Started May 12 02:55:47 PM PDT 24
Finished May 12 02:56:23 PM PDT 24
Peak memory 248828 kb
Host smart-c52c42f2-e2d9-4212-860b-abaece6df71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53330
2545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.533302545
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2445275660
Short name T396
Test name
Test status
Simulation time 1558921751 ps
CPU time 57.85 seconds
Started May 12 02:55:46 PM PDT 24
Finished May 12 02:56:44 PM PDT 24
Peak memory 248752 kb
Host smart-be97b24a-b8c5-4de2-a6c5-6d0a7ee1bbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
75660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2445275660
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3426734085
Short name T270
Test name
Test status
Simulation time 5131774229 ps
CPU time 243.92 seconds
Started May 12 02:55:50 PM PDT 24
Finished May 12 02:59:55 PM PDT 24
Peak memory 256672 kb
Host smart-a11292bd-eacf-4434-a5ed-8d0a7fc6cbf4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426734085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3426734085
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3176516094
Short name T212
Test name
Test status
Simulation time 433943434 ps
CPU time 3.44 seconds
Started May 12 02:55:58 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 248940 kb
Host smart-d699432b-2301-46d1-bb1e-02d1f5f7640d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3176516094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3176516094
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.157453537
Short name T646
Test name
Test status
Simulation time 22825909297 ps
CPU time 1027.57 seconds
Started May 12 02:55:56 PM PDT 24
Finished May 12 03:13:04 PM PDT 24
Peak memory 268408 kb
Host smart-df4af8c5-eb26-4762-9eed-390c4d88ebc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157453537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.157453537
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1677785532
Short name T614
Test name
Test status
Simulation time 344078547 ps
CPU time 16.23 seconds
Started May 12 02:55:58 PM PDT 24
Finished May 12 02:56:15 PM PDT 24
Peak memory 240504 kb
Host smart-446b6382-b5d4-49b2-ba0d-4305194fa6b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1677785532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1677785532
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2669469383
Short name T431
Test name
Test status
Simulation time 290474198 ps
CPU time 20.13 seconds
Started May 12 02:55:54 PM PDT 24
Finished May 12 02:56:15 PM PDT 24
Peak memory 248748 kb
Host smart-16d836d9-cd47-4fca-bba5-b358004e5f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26694
69383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2669469383
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1181951954
Short name T637
Test name
Test status
Simulation time 1417751311 ps
CPU time 42.25 seconds
Started May 12 02:55:55 PM PDT 24
Finished May 12 02:56:38 PM PDT 24
Peak memory 255576 kb
Host smart-8dbe5556-18a7-456b-9399-962404eca32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11819
51954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1181951954
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.442815959
Short name T567
Test name
Test status
Simulation time 40931767483 ps
CPU time 1123.96 seconds
Started May 12 02:55:56 PM PDT 24
Finished May 12 03:14:41 PM PDT 24
Peak memory 265220 kb
Host smart-77f92600-8baf-45ec-a739-93e45a80dd68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442815959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.442815959
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4049543073
Short name T306
Test name
Test status
Simulation time 12572312905 ps
CPU time 139.72 seconds
Started May 12 02:55:56 PM PDT 24
Finished May 12 02:58:16 PM PDT 24
Peak memory 248236 kb
Host smart-070f48df-2895-499c-8f2b-4624b66b5f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049543073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4049543073
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2272411573
Short name T429
Test name
Test status
Simulation time 2082575952 ps
CPU time 30.74 seconds
Started May 12 02:55:53 PM PDT 24
Finished May 12 02:56:24 PM PDT 24
Peak memory 248728 kb
Host smart-bd721f6c-b053-4122-a429-42e886fe73e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22724
11573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2272411573
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2703721013
Short name T680
Test name
Test status
Simulation time 2978524261 ps
CPU time 31.58 seconds
Started May 12 02:55:54 PM PDT 24
Finished May 12 02:56:27 PM PDT 24
Peak memory 248760 kb
Host smart-bfc897bc-bffd-4146-ac5e-6643bb9d2391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
21013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2703721013
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3934517087
Short name T45
Test name
Test status
Simulation time 51781217 ps
CPU time 7.67 seconds
Started May 12 02:55:54 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 247436 kb
Host smart-58b0226a-db17-4dca-8bf8-a8c80fd91548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345
17087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3934517087
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1542574517
Short name T475
Test name
Test status
Simulation time 721925119 ps
CPU time 19.25 seconds
Started May 12 02:55:50 PM PDT 24
Finished May 12 02:56:10 PM PDT 24
Peak memory 248776 kb
Host smart-96e3fc6f-4771-4cb7-b886-81b82c7e0449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15425
74517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1542574517
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3904083352
Short name T278
Test name
Test status
Simulation time 13625691673 ps
CPU time 1334.04 seconds
Started May 12 02:55:59 PM PDT 24
Finished May 12 03:18:13 PM PDT 24
Peak memory 289052 kb
Host smart-cbb0b875-0787-4bb7-ac03-8ac95b5e1af6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904083352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3904083352
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3234700412
Short name T512
Test name
Test status
Simulation time 46939321786 ps
CPU time 1416.74 seconds
Started May 12 02:56:01 PM PDT 24
Finished May 12 03:19:38 PM PDT 24
Peak memory 289712 kb
Host smart-fff7d52b-089c-46f7-85cc-dfcd14959e4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234700412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3234700412
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1226016779
Short name T659
Test name
Test status
Simulation time 462888456 ps
CPU time 12.31 seconds
Started May 12 02:56:05 PM PDT 24
Finished May 12 02:56:17 PM PDT 24
Peak memory 248764 kb
Host smart-705d7212-2793-438e-9ebf-549214097741
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1226016779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1226016779
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2940830820
Short name T374
Test name
Test status
Simulation time 35531249498 ps
CPU time 172.77 seconds
Started May 12 02:55:58 PM PDT 24
Finished May 12 02:58:51 PM PDT 24
Peak memory 256928 kb
Host smart-fe30b467-93c3-4fb0-a6bb-476e8362b163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
30820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2940830820
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3142964955
Short name T476
Test name
Test status
Simulation time 222915767 ps
CPU time 14.92 seconds
Started May 12 02:55:58 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 249088 kb
Host smart-0293b3fd-3af8-4c7c-922d-d446852668e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
64955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3142964955
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3637723691
Short name T640
Test name
Test status
Simulation time 42932169314 ps
CPU time 1233.48 seconds
Started May 12 02:56:00 PM PDT 24
Finished May 12 03:16:34 PM PDT 24
Peak memory 288900 kb
Host smart-a8433919-0f6a-4e7c-a8ac-4001f61de601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637723691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3637723691
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4276732378
Short name T667
Test name
Test status
Simulation time 58437623027 ps
CPU time 1729.09 seconds
Started May 12 02:56:03 PM PDT 24
Finished May 12 03:24:53 PM PDT 24
Peak memory 288168 kb
Host smart-c6b168e8-9c1a-403f-b872-dd2351e59002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276732378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4276732378
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1127843217
Short name T295
Test name
Test status
Simulation time 9041402354 ps
CPU time 408.07 seconds
Started May 12 02:56:00 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 255340 kb
Host smart-358d4da4-36f7-48a8-bd56-07112835ee5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127843217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1127843217
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3598043359
Short name T229
Test name
Test status
Simulation time 121037392 ps
CPU time 4.65 seconds
Started May 12 02:55:57 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 248760 kb
Host smart-6befd5f4-6460-4834-a748-b5a1c1717f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
43359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3598043359
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4137903129
Short name T93
Test name
Test status
Simulation time 93783872 ps
CPU time 8.66 seconds
Started May 12 02:55:58 PM PDT 24
Finished May 12 02:56:08 PM PDT 24
Peak memory 254032 kb
Host smart-dfc14003-77f8-4808-8eb4-655c44f87e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41379
03129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4137903129
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2134005689
Short name T394
Test name
Test status
Simulation time 82097368 ps
CPU time 11.01 seconds
Started May 12 02:55:57 PM PDT 24
Finished May 12 02:56:09 PM PDT 24
Peak memory 248916 kb
Host smart-b747f2fb-7a86-4e26-999c-9d2edfd435b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
05689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2134005689
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1136825605
Short name T47
Test name
Test status
Simulation time 94357795795 ps
CPU time 1743.23 seconds
Started May 12 02:56:04 PM PDT 24
Finished May 12 03:25:08 PM PDT 24
Peak memory 272808 kb
Host smart-9d08c0e1-4859-4692-9140-c9bd7d13c3ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136825605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1136825605
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3664979366
Short name T204
Test name
Test status
Simulation time 41186683 ps
CPU time 3.96 seconds
Started May 12 02:56:14 PM PDT 24
Finished May 12 02:56:18 PM PDT 24
Peak memory 248900 kb
Host smart-581b3916-dc88-481a-aad7-1a41d645540b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3664979366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3664979366
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2942311875
Short name T410
Test name
Test status
Simulation time 7036238681 ps
CPU time 778.88 seconds
Started May 12 02:56:12 PM PDT 24
Finished May 12 03:09:12 PM PDT 24
Peak memory 272812 kb
Host smart-98a02194-6274-4a20-ba32-64e062e9ec07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942311875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2942311875
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2654126217
Short name T351
Test name
Test status
Simulation time 3942996763 ps
CPU time 42.9 seconds
Started May 12 02:56:14 PM PDT 24
Finished May 12 02:56:57 PM PDT 24
Peak memory 248780 kb
Host smart-8d70e3a8-7b44-4544-969f-be5fd78351fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2654126217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2654126217
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2010683233
Short name T352
Test name
Test status
Simulation time 8082778784 ps
CPU time 158.86 seconds
Started May 12 02:56:11 PM PDT 24
Finished May 12 02:58:51 PM PDT 24
Peak memory 251016 kb
Host smart-e82bafb7-33bb-43ca-ab83-92036144a5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
83233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2010683233
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1752416126
Short name T660
Test name
Test status
Simulation time 430164371 ps
CPU time 37.15 seconds
Started May 12 02:56:10 PM PDT 24
Finished May 12 02:56:48 PM PDT 24
Peak memory 256040 kb
Host smart-cbc8365d-d326-41a8-8aa8-a632394c5705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17524
16126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1752416126
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.655191917
Short name T326
Test name
Test status
Simulation time 19751565463 ps
CPU time 1061.27 seconds
Started May 12 02:56:10 PM PDT 24
Finished May 12 03:13:52 PM PDT 24
Peak memory 267264 kb
Host smart-e3e19fd7-da67-41a0-8051-a6b59eb2f41e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655191917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.655191917
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1932722584
Short name T376
Test name
Test status
Simulation time 20301275050 ps
CPU time 1305.69 seconds
Started May 12 02:56:13 PM PDT 24
Finished May 12 03:17:59 PM PDT 24
Peak memory 273056 kb
Host smart-55afd095-3340-4310-9a08-620527414fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932722584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1932722584
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3228576599
Short name T547
Test name
Test status
Simulation time 1585874105 ps
CPU time 79.01 seconds
Started May 12 02:56:11 PM PDT 24
Finished May 12 02:57:30 PM PDT 24
Peak memory 248296 kb
Host smart-37315bb7-8c9a-45f2-9e0b-1ed4b9382ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228576599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3228576599
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.440889666
Short name T403
Test name
Test status
Simulation time 106695233 ps
CPU time 15.06 seconds
Started May 12 02:56:09 PM PDT 24
Finished May 12 02:56:24 PM PDT 24
Peak memory 248724 kb
Host smart-aefedbce-aefb-438d-8c47-52c15059f043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44088
9666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.440889666
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3494315945
Short name T353
Test name
Test status
Simulation time 400794749 ps
CPU time 26.96 seconds
Started May 12 02:56:12 PM PDT 24
Finished May 12 02:56:39 PM PDT 24
Peak memory 255576 kb
Host smart-a751f3ac-af27-48f0-aea6-0c399bae4927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
15945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3494315945
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2065881171
Short name T363
Test name
Test status
Simulation time 1557401176 ps
CPU time 37.96 seconds
Started May 12 02:56:11 PM PDT 24
Finished May 12 02:56:50 PM PDT 24
Peak memory 255760 kb
Host smart-d1db683b-0ee6-4673-8da3-09b1d60907a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
81171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2065881171
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2541030065
Short name T587
Test name
Test status
Simulation time 6168968573 ps
CPU time 47.88 seconds
Started May 12 02:56:03 PM PDT 24
Finished May 12 02:56:51 PM PDT 24
Peak memory 248928 kb
Host smart-ad9d6898-2ebb-4e8b-a849-2f92f8d5ed41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
30065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2541030065
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3190791883
Short name T268
Test name
Test status
Simulation time 78343603420 ps
CPU time 2200.98 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 03:33:00 PM PDT 24
Peak memory 305816 kb
Host smart-653efa09-6700-4194-ae1b-8e97ced1d472
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190791883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3190791883
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2356484415
Short name T216
Test name
Test status
Simulation time 93908769 ps
CPU time 2.96 seconds
Started May 12 02:56:21 PM PDT 24
Finished May 12 02:56:24 PM PDT 24
Peak memory 248876 kb
Host smart-978bc6f4-7089-45bc-bf1b-d19728757626
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2356484415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2356484415
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1519031491
Short name T599
Test name
Test status
Simulation time 420726119775 ps
CPU time 2319.58 seconds
Started May 12 02:56:21 PM PDT 24
Finished May 12 03:35:01 PM PDT 24
Peak memory 281604 kb
Host smart-349da0fd-9a43-4368-b564-898eec7b1bae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519031491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1519031491
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3623244020
Short name T368
Test name
Test status
Simulation time 165905790 ps
CPU time 9.53 seconds
Started May 12 02:56:24 PM PDT 24
Finished May 12 02:56:34 PM PDT 24
Peak memory 248728 kb
Host smart-917b4b93-a23d-4b9a-8a78-8a98ca96bea7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3623244020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3623244020
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3095080321
Short name T31
Test name
Test status
Simulation time 1282764617 ps
CPU time 86.79 seconds
Started May 12 02:56:25 PM PDT 24
Finished May 12 02:57:52 PM PDT 24
Peak memory 256756 kb
Host smart-4670f25b-70c0-4185-b99f-9da4c928bfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30950
80321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3095080321
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2548862949
Short name T117
Test name
Test status
Simulation time 906999208 ps
CPU time 62.71 seconds
Started May 12 02:56:24 PM PDT 24
Finished May 12 02:57:28 PM PDT 24
Peak memory 255980 kb
Host smart-ec026e0c-24a3-4e75-8ff3-5a30f7f42663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25488
62949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2548862949
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.852828601
Short name T695
Test name
Test status
Simulation time 39826852192 ps
CPU time 921.76 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 03:11:42 PM PDT 24
Peak memory 265224 kb
Host smart-6a5ee0c4-45d6-4cd6-92ba-2e891b791eee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852828601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.852828601
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4079765080
Short name T516
Test name
Test status
Simulation time 43632270160 ps
CPU time 2650.61 seconds
Started May 12 02:56:24 PM PDT 24
Finished May 12 03:40:36 PM PDT 24
Peak memory 289080 kb
Host smart-7dff2d12-1a5b-4d05-bcf8-3331b5145cdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079765080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4079765080
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1560761482
Short name T298
Test name
Test status
Simulation time 43959030250 ps
CPU time 421.15 seconds
Started May 12 02:56:18 PM PDT 24
Finished May 12 03:03:19 PM PDT 24
Peak memory 248232 kb
Host smart-07699518-ce30-4f1e-9664-a99296ee837a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560761482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1560761482
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2016310608
Short name T469
Test name
Test status
Simulation time 210769352 ps
CPU time 22.95 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 02:56:42 PM PDT 24
Peak memory 248776 kb
Host smart-22db233d-5614-43b7-9c7a-4f1657e3cc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20163
10608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2016310608
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3938670602
Short name T666
Test name
Test status
Simulation time 1427465214 ps
CPU time 13.07 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 02:56:33 PM PDT 24
Peak memory 248872 kb
Host smart-96a3d157-0ef7-4d32-b53e-1fe00d206e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39386
70602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3938670602
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2049079235
Short name T622
Test name
Test status
Simulation time 82920659 ps
CPU time 12.19 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 02:56:32 PM PDT 24
Peak memory 248776 kb
Host smart-fac0f724-a328-45f8-be72-37318ffefd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
79235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2049079235
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2035173702
Short name T448
Test name
Test status
Simulation time 1311571126 ps
CPU time 24.72 seconds
Started May 12 02:56:19 PM PDT 24
Finished May 12 02:56:44 PM PDT 24
Peak memory 256040 kb
Host smart-030118d8-c31e-4e2e-8b4d-bf193d68b8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20351
73702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2035173702
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.902896091
Short name T628
Test name
Test status
Simulation time 41663313660 ps
CPU time 2771.87 seconds
Started May 12 02:56:22 PM PDT 24
Finished May 12 03:42:34 PM PDT 24
Peak memory 289500 kb
Host smart-1508babc-d6f3-4074-8b86-280d01df271b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902896091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.902896091
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2874963281
Short name T209
Test name
Test status
Simulation time 369725983 ps
CPU time 3.45 seconds
Started May 12 02:56:27 PM PDT 24
Finished May 12 02:56:31 PM PDT 24
Peak memory 248864 kb
Host smart-37735434-4c40-4eca-834a-7ca6971b470b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2874963281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2874963281
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1148402034
Short name T463
Test name
Test status
Simulation time 53759303268 ps
CPU time 1810.46 seconds
Started May 12 02:56:26 PM PDT 24
Finished May 12 03:26:38 PM PDT 24
Peak memory 272528 kb
Host smart-971cd1b3-7e85-4a06-9dd9-9aaa56025fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148402034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1148402034
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1727265637
Short name T615
Test name
Test status
Simulation time 528247280 ps
CPU time 9.05 seconds
Started May 12 02:56:29 PM PDT 24
Finished May 12 02:56:39 PM PDT 24
Peak memory 240504 kb
Host smart-1d579699-380b-4988-b952-fb8de45f8228
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1727265637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1727265637
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3773438204
Short name T681
Test name
Test status
Simulation time 973309217 ps
CPU time 65.89 seconds
Started May 12 02:56:26 PM PDT 24
Finished May 12 02:57:32 PM PDT 24
Peak memory 255656 kb
Host smart-8ef2fc85-26d7-4d27-87ee-6faea86a2010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37734
38204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3773438204
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3867587890
Short name T231
Test name
Test status
Simulation time 4545442175 ps
CPU time 40.91 seconds
Started May 12 02:56:25 PM PDT 24
Finished May 12 02:57:07 PM PDT 24
Peak memory 257016 kb
Host smart-705c259b-8705-4ba1-bafe-a41528067c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
87890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3867587890
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2484249780
Short name T314
Test name
Test status
Simulation time 26291330590 ps
CPU time 1830.2 seconds
Started May 12 02:56:38 PM PDT 24
Finished May 12 03:27:08 PM PDT 24
Peak memory 272628 kb
Host smart-069b536f-e54d-4aff-8c8c-3737c16b8d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484249780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2484249780
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1781763573
Short name T91
Test name
Test status
Simulation time 7200933109 ps
CPU time 755.09 seconds
Started May 12 02:56:29 PM PDT 24
Finished May 12 03:09:04 PM PDT 24
Peak memory 273308 kb
Host smart-4948efa9-831b-40bc-9077-48f8ed57ff18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781763573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1781763573
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.231816810
Short name T9
Test name
Test status
Simulation time 75196916780 ps
CPU time 355.41 seconds
Started May 12 02:56:25 PM PDT 24
Finished May 12 03:02:21 PM PDT 24
Peak memory 247748 kb
Host smart-3fc9ca7d-1f11-4384-8bc9-8d3c95d71d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231816810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.231816810
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.30467876
Short name T453
Test name
Test status
Simulation time 174206659 ps
CPU time 15.55 seconds
Started May 12 02:56:21 PM PDT 24
Finished May 12 02:56:37 PM PDT 24
Peak memory 248752 kb
Host smart-52a7cdcc-5c35-46d7-9f7c-891e32f7b6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467
876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.30467876
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2468973237
Short name T51
Test name
Test status
Simulation time 81457056 ps
CPU time 7.3 seconds
Started May 12 02:56:27 PM PDT 24
Finished May 12 02:56:35 PM PDT 24
Peak memory 252040 kb
Host smart-5f02621e-42c3-48bf-8c28-cf2280cf2053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
73237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2468973237
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2355293612
Short name T56
Test name
Test status
Simulation time 2617985567 ps
CPU time 37.11 seconds
Started May 12 02:56:25 PM PDT 24
Finished May 12 02:57:03 PM PDT 24
Peak memory 255600 kb
Host smart-492241d8-7d9c-43bb-8990-e42651663dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
93612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2355293612
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3865719356
Short name T17
Test name
Test status
Simulation time 835578875 ps
CPU time 54.48 seconds
Started May 12 02:56:22 PM PDT 24
Finished May 12 02:57:17 PM PDT 24
Peak memory 248720 kb
Host smart-797431bb-d6b2-4f19-81bf-b6b19cf98067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
19356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3865719356
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2087180444
Short name T210
Test name
Test status
Simulation time 47497817 ps
CPU time 4.22 seconds
Started May 12 02:56:31 PM PDT 24
Finished May 12 02:56:36 PM PDT 24
Peak memory 248940 kb
Host smart-171b978c-3f08-4680-bb5d-c683c6bf4e27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2087180444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2087180444
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3531085390
Short name T511
Test name
Test status
Simulation time 148831742638 ps
CPU time 1628.19 seconds
Started May 12 02:56:38 PM PDT 24
Finished May 12 03:23:47 PM PDT 24
Peak memory 287964 kb
Host smart-c78e44a5-833d-4d89-a877-a518d55ef64c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531085390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3531085390
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1353515083
Short name T678
Test name
Test status
Simulation time 569998622 ps
CPU time 9.36 seconds
Started May 12 02:56:32 PM PDT 24
Finished May 12 02:56:42 PM PDT 24
Peak memory 240532 kb
Host smart-50ef44b0-7e13-4a50-8bd1-18eb063d120b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1353515083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1353515083
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3116871537
Short name T457
Test name
Test status
Simulation time 3667626971 ps
CPU time 251.44 seconds
Started May 12 02:56:32 PM PDT 24
Finished May 12 03:00:44 PM PDT 24
Peak memory 249836 kb
Host smart-1a83dda1-01ca-4234-8a26-00f8aaff5064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
71537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3116871537
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3688500463
Short name T560
Test name
Test status
Simulation time 617974826 ps
CPU time 13.47 seconds
Started May 12 02:56:28 PM PDT 24
Finished May 12 02:56:42 PM PDT 24
Peak memory 248808 kb
Host smart-6e1af3dc-bbcd-4b5e-99ba-2fa1fd62ce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
00463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3688500463
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4095916375
Short name T324
Test name
Test status
Simulation time 652407500111 ps
CPU time 3218.03 seconds
Started May 12 02:56:32 PM PDT 24
Finished May 12 03:50:11 PM PDT 24
Peak memory 288796 kb
Host smart-60263df5-deb7-4c0e-b4e9-c11bed3ceba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095916375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4095916375
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2431667981
Short name T350
Test name
Test status
Simulation time 176967475330 ps
CPU time 1282.05 seconds
Started May 12 02:56:38 PM PDT 24
Finished May 12 03:18:00 PM PDT 24
Peak memory 289632 kb
Host smart-505b9a01-6047-4114-b858-98dc82046eba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431667981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2431667981
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4193785714
Short name T293
Test name
Test status
Simulation time 25662705274 ps
CPU time 301.26 seconds
Started May 12 02:56:30 PM PDT 24
Finished May 12 03:01:31 PM PDT 24
Peak memory 248364 kb
Host smart-8446a649-b1e0-4f59-ab81-c6bd0603597d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193785714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4193785714
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2590084619
Short name T267
Test name
Test status
Simulation time 2287232971 ps
CPU time 29.29 seconds
Started May 12 02:56:27 PM PDT 24
Finished May 12 02:56:57 PM PDT 24
Peak memory 248796 kb
Host smart-1d7c7344-2452-455c-9540-6230541fcfec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25900
84619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2590084619
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2389495875
Short name T503
Test name
Test status
Simulation time 247654525 ps
CPU time 25.58 seconds
Started May 12 02:56:29 PM PDT 24
Finished May 12 02:56:55 PM PDT 24
Peak memory 248708 kb
Host smart-f10294dc-ee98-41af-8774-e330156af501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
95875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2389495875
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2691801906
Short name T569
Test name
Test status
Simulation time 317127270 ps
CPU time 29.77 seconds
Started May 12 02:56:32 PM PDT 24
Finished May 12 02:57:03 PM PDT 24
Peak memory 248716 kb
Host smart-be49787d-e089-4138-a58d-3139f4240a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
01906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2691801906
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3256409712
Short name T656
Test name
Test status
Simulation time 14310999040 ps
CPU time 1252.27 seconds
Started May 12 02:56:33 PM PDT 24
Finished May 12 03:17:26 PM PDT 24
Peak memory 289432 kb
Host smart-44c23822-3966-4ab6-931a-4eac3eb8c17e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256409712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3256409712
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4094596411
Short name T197
Test name
Test status
Simulation time 45934037 ps
CPU time 3.88 seconds
Started May 12 02:56:40 PM PDT 24
Finished May 12 02:56:45 PM PDT 24
Peak memory 248904 kb
Host smart-ce0c2fa5-8a0b-4cf2-bb57-6b93086d710a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4094596411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4094596411
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1484089194
Short name T624
Test name
Test status
Simulation time 28540374420 ps
CPU time 1184.1 seconds
Started May 12 02:56:37 PM PDT 24
Finished May 12 03:16:22 PM PDT 24
Peak memory 265232 kb
Host smart-64925680-ff3f-41d6-90f5-c5f74b633280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484089194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1484089194
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3833961071
Short name T443
Test name
Test status
Simulation time 1711285927 ps
CPU time 68.05 seconds
Started May 12 02:56:37 PM PDT 24
Finished May 12 02:57:45 PM PDT 24
Peak memory 248760 kb
Host smart-4ef5d693-7c63-48dd-9c71-81a5f830682e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3833961071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3833961071
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3953861445
Short name T434
Test name
Test status
Simulation time 3079912411 ps
CPU time 103.39 seconds
Started May 12 02:56:35 PM PDT 24
Finished May 12 02:58:19 PM PDT 24
Peak memory 256884 kb
Host smart-aa1f391d-ded6-417f-ae02-fe0597067023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39538
61445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3953861445
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1048273351
Short name T473
Test name
Test status
Simulation time 3750159768 ps
CPU time 41.04 seconds
Started May 12 02:56:37 PM PDT 24
Finished May 12 02:57:18 PM PDT 24
Peak memory 255972 kb
Host smart-52d39171-a027-46e7-85d9-4b10c9eb5afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10482
73351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1048273351
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1537244549
Short name T285
Test name
Test status
Simulation time 42137581400 ps
CPU time 1811.58 seconds
Started May 12 02:56:36 PM PDT 24
Finished May 12 03:26:49 PM PDT 24
Peak memory 289312 kb
Host smart-b0741818-1061-442e-b3b3-8d4e5075c7a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537244549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1537244549
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1151480392
Short name T33
Test name
Test status
Simulation time 20128361303 ps
CPU time 1343.64 seconds
Started May 12 02:56:37 PM PDT 24
Finished May 12 03:19:02 PM PDT 24
Peak memory 273400 kb
Host smart-2be3e4df-fe15-4080-922a-833fc87aaef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151480392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1151480392
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2519904344
Short name T550
Test name
Test status
Simulation time 1840790755 ps
CPU time 26.86 seconds
Started May 12 02:56:35 PM PDT 24
Finished May 12 02:57:03 PM PDT 24
Peak memory 255912 kb
Host smart-5ad16522-d804-4f21-9a37-0ba43dc4a153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25199
04344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2519904344
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4151911879
Short name T108
Test name
Test status
Simulation time 829279339 ps
CPU time 17.94 seconds
Started May 12 02:56:34 PM PDT 24
Finished May 12 02:56:53 PM PDT 24
Peak memory 248616 kb
Host smart-39118385-f688-433d-a11f-88f358d22ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41519
11879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4151911879
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.202992491
Short name T576
Test name
Test status
Simulation time 156235044 ps
CPU time 6.32 seconds
Started May 12 02:56:34 PM PDT 24
Finished May 12 02:56:40 PM PDT 24
Peak memory 253716 kb
Host smart-7b724bfb-5f4b-492f-889a-36f545d83857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20299
2491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.202992491
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.259610951
Short name T692
Test name
Test status
Simulation time 529913210 ps
CPU time 10.71 seconds
Started May 12 02:56:32 PM PDT 24
Finished May 12 02:56:44 PM PDT 24
Peak memory 248716 kb
Host smart-5b759ff5-78ea-4124-a570-a74ce151fbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
0951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.259610951
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.309495745
Short name T510
Test name
Test status
Simulation time 14502160381 ps
CPU time 1640.39 seconds
Started May 12 02:56:38 PM PDT 24
Finished May 12 03:24:00 PM PDT 24
Peak memory 289652 kb
Host smart-63165532-4fcb-4003-9425-0b8113cf3ef9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309495745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.309495745
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.955026741
Short name T496
Test name
Test status
Simulation time 70434168598 ps
CPU time 1031.79 seconds
Started May 12 02:54:49 PM PDT 24
Finished May 12 03:12:02 PM PDT 24
Peak memory 272160 kb
Host smart-30b4b597-7254-448c-be8b-17c9b7ba4565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955026741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.955026741
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.926721485
Short name T195
Test name
Test status
Simulation time 583407585 ps
CPU time 24.56 seconds
Started May 12 02:54:48 PM PDT 24
Finished May 12 02:55:13 PM PDT 24
Peak memory 248772 kb
Host smart-bdb6d6e0-a5b6-4af2-a430-f07028f56340
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=926721485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.926721485
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.997487189
Short name T373
Test name
Test status
Simulation time 36154589472 ps
CPU time 182.75 seconds
Started May 12 02:54:49 PM PDT 24
Finished May 12 02:57:52 PM PDT 24
Peak memory 256932 kb
Host smart-7e4d24b6-5d2d-482d-aed1-2d634d281888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99748
7189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.997487189
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3011228222
Short name T249
Test name
Test status
Simulation time 1335242673 ps
CPU time 17.99 seconds
Started May 12 02:54:49 PM PDT 24
Finished May 12 02:55:07 PM PDT 24
Peak memory 248748 kb
Host smart-411e7658-b3e2-4547-bfb2-6f99c9147d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30112
28222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3011228222
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.418847604
Short name T625
Test name
Test status
Simulation time 12674182946 ps
CPU time 1336.62 seconds
Started May 12 02:54:47 PM PDT 24
Finished May 12 03:17:05 PM PDT 24
Peak memory 289124 kb
Host smart-362b9b25-08ab-45b0-8550-bdf1b5729ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418847604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.418847604
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3140817747
Short name T106
Test name
Test status
Simulation time 19224793220 ps
CPU time 1697.12 seconds
Started May 12 02:54:48 PM PDT 24
Finished May 12 03:23:06 PM PDT 24
Peak memory 289284 kb
Host smart-eccf5f20-ad72-4b3d-802a-87a87d538188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140817747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3140817747
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1998372057
Short name T300
Test name
Test status
Simulation time 10547197030 ps
CPU time 450.04 seconds
Started May 12 02:54:48 PM PDT 24
Finished May 12 03:02:18 PM PDT 24
Peak memory 247872 kb
Host smart-b3b38119-0f5f-4900-9761-c7a723040678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998372057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1998372057
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2353782204
Short name T654
Test name
Test status
Simulation time 348733859 ps
CPU time 8.28 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 02:54:53 PM PDT 24
Peak memory 256940 kb
Host smart-c8a1cb46-b7ed-42ed-a355-63a02a1791be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23537
82204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2353782204
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1484208430
Short name T391
Test name
Test status
Simulation time 930813734 ps
CPU time 54.5 seconds
Started May 12 02:54:44 PM PDT 24
Finished May 12 02:55:39 PM PDT 24
Peak memory 255536 kb
Host smart-81b400b8-9616-4d2d-85e2-4a2f3e4c2f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
08430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1484208430
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3409740648
Short name T30
Test name
Test status
Simulation time 602212130 ps
CPU time 26.33 seconds
Started May 12 02:54:51 PM PDT 24
Finished May 12 02:55:18 PM PDT 24
Peak memory 270236 kb
Host smart-2f950f3b-07ea-4882-aee4-4a4ab1dd3a89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3409740648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3409740648
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2895821495
Short name T251
Test name
Test status
Simulation time 411229348 ps
CPU time 22.86 seconds
Started May 12 02:54:49 PM PDT 24
Finished May 12 02:55:13 PM PDT 24
Peak memory 248760 kb
Host smart-e97b57ed-713c-42a5-a297-c7d194c44f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
21495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2895821495
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.206462158
Short name T393
Test name
Test status
Simulation time 358044323 ps
CPU time 36.43 seconds
Started May 12 02:54:45 PM PDT 24
Finished May 12 02:55:22 PM PDT 24
Peak memory 248748 kb
Host smart-c03063b3-ded7-4c26-ba1c-a3d43acb41c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
2158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.206462158
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3426069743
Short name T266
Test name
Test status
Simulation time 39354388437 ps
CPU time 634.5 seconds
Started May 12 02:54:48 PM PDT 24
Finished May 12 03:05:23 PM PDT 24
Peak memory 256804 kb
Host smart-d9908578-e8e1-4647-b73a-43dfa5c74a24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426069743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3426069743
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3283248113
Short name T192
Test name
Test status
Simulation time 28163603363 ps
CPU time 1625.18 seconds
Started May 12 02:54:50 PM PDT 24
Finished May 12 03:21:56 PM PDT 24
Peak memory 281692 kb
Host smart-aa858e94-d8ae-4334-95b8-1c698365af4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283248113 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3283248113
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2117391113
Short name T607
Test name
Test status
Simulation time 13600060249 ps
CPU time 1089.4 seconds
Started May 12 02:56:43 PM PDT 24
Finished May 12 03:14:53 PM PDT 24
Peak memory 271916 kb
Host smart-518ce66f-a281-4eb9-8502-345a1de4206a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117391113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2117391113
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.902444181
Short name T594
Test name
Test status
Simulation time 3725593471 ps
CPU time 222.03 seconds
Started May 12 02:56:40 PM PDT 24
Finished May 12 03:00:23 PM PDT 24
Peak memory 257096 kb
Host smart-acb5c059-4592-44bb-ab6a-a95e676c9588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90244
4181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.902444181
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2369313000
Short name T364
Test name
Test status
Simulation time 120279715 ps
CPU time 9.8 seconds
Started May 12 02:56:42 PM PDT 24
Finished May 12 02:56:52 PM PDT 24
Peak memory 252380 kb
Host smart-75d6b444-fb87-48f8-912b-85c8e001dd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
13000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2369313000
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3172769336
Short name T584
Test name
Test status
Simulation time 31629634395 ps
CPU time 1564.62 seconds
Started May 12 02:56:45 PM PDT 24
Finished May 12 03:22:51 PM PDT 24
Peak memory 281548 kb
Host smart-975d2d05-1499-4011-9c71-c5c58f3e355c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172769336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3172769336
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2612991221
Short name T264
Test name
Test status
Simulation time 14544092842 ps
CPU time 1172.8 seconds
Started May 12 02:56:45 PM PDT 24
Finished May 12 03:16:18 PM PDT 24
Peak memory 282560 kb
Host smart-0c178c6d-f5ed-4bc0-ab5e-7920cd586efd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612991221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2612991221
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2369170393
Short name T532
Test name
Test status
Simulation time 17617771879 ps
CPU time 350.09 seconds
Started May 12 02:56:45 PM PDT 24
Finished May 12 03:02:35 PM PDT 24
Peak memory 247968 kb
Host smart-80db7606-a39b-421b-8feb-70f0f0f4833a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369170393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2369170393
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.111715479
Short name T608
Test name
Test status
Simulation time 734717050 ps
CPU time 15.74 seconds
Started May 12 02:56:41 PM PDT 24
Finished May 12 02:56:58 PM PDT 24
Peak memory 248776 kb
Host smart-93952b34-bcde-4154-859e-fec3fbd810a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
5479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.111715479
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1581398720
Short name T649
Test name
Test status
Simulation time 125477111 ps
CPU time 5.78 seconds
Started May 12 02:56:43 PM PDT 24
Finished May 12 02:56:49 PM PDT 24
Peak memory 239228 kb
Host smart-d5c3ccdf-bfdb-4d25-a5bb-d9a03ab85e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15813
98720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1581398720
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3241200264
Short name T244
Test name
Test status
Simulation time 642103650 ps
CPU time 20.64 seconds
Started May 12 02:56:41 PM PDT 24
Finished May 12 02:57:02 PM PDT 24
Peak memory 248768 kb
Host smart-36847926-c5ad-46d5-ad8e-79c9face4eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
00264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3241200264
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2297080158
Short name T497
Test name
Test status
Simulation time 555047058 ps
CPU time 34.39 seconds
Started May 12 02:56:41 PM PDT 24
Finished May 12 02:57:16 PM PDT 24
Peak memory 248956 kb
Host smart-896b7305-a010-4664-aa2f-46212faa3211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
80158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2297080158
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4107998663
Short name T617
Test name
Test status
Simulation time 43825332643 ps
CPU time 2956.57 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 03:46:04 PM PDT 24
Peak memory 286932 kb
Host smart-2f3f5dbb-aff7-4953-8dbb-caab5a89f386
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107998663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4107998663
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2735349339
Short name T115
Test name
Test status
Simulation time 10336999809 ps
CPU time 636.79 seconds
Started May 12 02:56:43 PM PDT 24
Finished May 12 03:07:21 PM PDT 24
Peak memory 265372 kb
Host smart-1b41e02f-b490-41a5-8bfc-d6b8dcb40f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735349339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2735349339
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.8699572
Short name T602
Test name
Test status
Simulation time 3771931155 ps
CPU time 147.11 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:59:13 PM PDT 24
Peak memory 256944 kb
Host smart-4f9f7cb3-848a-42bc-a2d7-1b229920a6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86995
72 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.8699572
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1063929245
Short name T407
Test name
Test status
Simulation time 169385419 ps
CPU time 13.18 seconds
Started May 12 02:56:43 PM PDT 24
Finished May 12 02:56:57 PM PDT 24
Peak memory 252484 kb
Host smart-9ddee288-2aa2-4102-8735-9dad4d4d05bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
29245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1063929245
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.753034792
Short name T318
Test name
Test status
Simulation time 24948831634 ps
CPU time 1649.65 seconds
Started May 12 02:56:48 PM PDT 24
Finished May 12 03:24:18 PM PDT 24
Peak memory 273380 kb
Host smart-385bc4c3-0bbd-4815-aa65-bc1a72142c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753034792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.753034792
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1226032190
Short name T461
Test name
Test status
Simulation time 72701696332 ps
CPU time 2852.43 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 03:44:19 PM PDT 24
Peak memory 286356 kb
Host smart-abdba992-603c-4f7d-8d4c-4e90920adfff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226032190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1226032190
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3304298691
Short name T292
Test name
Test status
Simulation time 62432924850 ps
CPU time 591.85 seconds
Started May 12 02:56:47 PM PDT 24
Finished May 12 03:06:40 PM PDT 24
Peak memory 254880 kb
Host smart-e330fbfb-c747-4a9b-af88-3efcc9e7a975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304298691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3304298691
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2272917148
Short name T59
Test name
Test status
Simulation time 47240060 ps
CPU time 6.23 seconds
Started May 12 02:56:44 PM PDT 24
Finished May 12 02:56:51 PM PDT 24
Peak memory 256880 kb
Host smart-d09fd895-dbd8-4114-81b1-4558cfadc195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
17148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2272917148
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2876485604
Short name T645
Test name
Test status
Simulation time 1599788219 ps
CPU time 26.69 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:57:13 PM PDT 24
Peak memory 248996 kb
Host smart-927f8bcf-6de6-4ce9-b6af-f5e092636dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
85604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2876485604
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.91188136
Short name T546
Test name
Test status
Simulation time 4432573732 ps
CPU time 48.21 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:57:35 PM PDT 24
Peak memory 256940 kb
Host smart-e6efd357-f73e-46e4-9780-f49965053f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91188
136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.91188136
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2307426096
Short name T525
Test name
Test status
Simulation time 14319642076 ps
CPU time 1919.48 seconds
Started May 12 02:56:50 PM PDT 24
Finished May 12 03:28:50 PM PDT 24
Peak memory 289688 kb
Host smart-8d18e732-a86d-4722-9806-b00e4de512a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307426096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2307426096
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1366617403
Short name T237
Test name
Test status
Simulation time 46508369437 ps
CPU time 3415.18 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 03:53:43 PM PDT 24
Peak memory 289460 kb
Host smart-53bc8341-b95d-45a7-9f9c-7e1720aec1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366617403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1366617403
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1904126782
Short name T551
Test name
Test status
Simulation time 52339424860 ps
CPU time 1886.41 seconds
Started May 12 02:56:52 PM PDT 24
Finished May 12 03:28:19 PM PDT 24
Peak memory 288920 kb
Host smart-c79cb656-208a-487e-aded-6ee81413850a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904126782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1904126782
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1918198680
Short name T360
Test name
Test status
Simulation time 23125661125 ps
CPU time 91.05 seconds
Started May 12 02:56:51 PM PDT 24
Finished May 12 02:58:22 PM PDT 24
Peak memory 256988 kb
Host smart-d8d4e119-0614-4e6b-a29b-cd59b4a825f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19181
98680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1918198680
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1146999319
Short name T348
Test name
Test status
Simulation time 338778785 ps
CPU time 20.11 seconds
Started May 12 02:56:48 PM PDT 24
Finished May 12 02:57:09 PM PDT 24
Peak memory 248744 kb
Host smart-4ccd3773-28fd-4fb2-9f34-5b252c68cd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
99319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1146999319
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.678338643
Short name T375
Test name
Test status
Simulation time 41133817850 ps
CPU time 2756.59 seconds
Started May 12 02:56:52 PM PDT 24
Finished May 12 03:42:49 PM PDT 24
Peak memory 288868 kb
Host smart-ef504cc5-c7e9-436e-bc9b-5511334b1653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678338643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.678338643
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3924786678
Short name T307
Test name
Test status
Simulation time 4033985909 ps
CPU time 169.95 seconds
Started May 12 02:56:50 PM PDT 24
Finished May 12 02:59:40 PM PDT 24
Peak memory 248216 kb
Host smart-790436cc-3d5d-4e9c-aea0-0189a1c4bef5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924786678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3924786678
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1606247032
Short name T651
Test name
Test status
Simulation time 174272930 ps
CPU time 20.54 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:57:08 PM PDT 24
Peak memory 256720 kb
Host smart-1e4bd713-9f40-4374-bc5d-ec3e3b2e54f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
47032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1606247032
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3819293544
Short name T113
Test name
Test status
Simulation time 441925254 ps
CPU time 43.94 seconds
Started May 12 02:56:46 PM PDT 24
Finished May 12 02:57:31 PM PDT 24
Peak memory 248764 kb
Host smart-125b7fd5-1cac-48ba-906d-74a8fdf25fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38192
93544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3819293544
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3419002504
Short name T254
Test name
Test status
Simulation time 3267450848 ps
CPU time 54.59 seconds
Started May 12 02:56:51 PM PDT 24
Finished May 12 02:57:46 PM PDT 24
Peak memory 256508 kb
Host smart-a2ef0b9f-fb67-477f-8a9f-77bc73978b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
02504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3419002504
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.471270736
Short name T107
Test name
Test status
Simulation time 705744225 ps
CPU time 41.38 seconds
Started May 12 02:56:48 PM PDT 24
Finished May 12 02:57:30 PM PDT 24
Peak memory 256864 kb
Host smart-d585dcd2-25cb-4b27-8c8a-d74241d7d41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47127
0736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.471270736
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.220645576
Short name T521
Test name
Test status
Simulation time 2724247825 ps
CPU time 226.89 seconds
Started May 12 02:56:50 PM PDT 24
Finished May 12 03:00:38 PM PDT 24
Peak memory 256980 kb
Host smart-b7fd198b-b49c-4d94-8103-28dca52fa09b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220645576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.220645576
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.255854828
Short name T663
Test name
Test status
Simulation time 237086274473 ps
CPU time 4603.93 seconds
Started May 12 02:56:54 PM PDT 24
Finished May 12 04:13:40 PM PDT 24
Peak memory 322656 kb
Host smart-51bf490e-0738-4445-9cbe-23713fa2efa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255854828 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.255854828
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.391372317
Short name T616
Test name
Test status
Simulation time 61891580535 ps
CPU time 2499.53 seconds
Started May 12 02:56:58 PM PDT 24
Finished May 12 03:38:38 PM PDT 24
Peak memory 284444 kb
Host smart-f9dd247b-2171-4dce-bdc1-734525dd81c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391372317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.391372317
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1856178872
Short name T449
Test name
Test status
Simulation time 151187573 ps
CPU time 10.02 seconds
Started May 12 02:56:54 PM PDT 24
Finished May 12 02:57:05 PM PDT 24
Peak memory 254308 kb
Host smart-610fc590-a19c-45a9-b904-a6836c3eca5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
78872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1856178872
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1323477285
Short name T676
Test name
Test status
Simulation time 1686827159 ps
CPU time 32.87 seconds
Started May 12 02:56:56 PM PDT 24
Finished May 12 02:57:29 PM PDT 24
Peak memory 248820 kb
Host smart-cbebdebe-0a96-4cf5-a872-f8691adb9a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234
77285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1323477285
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2731814522
Short name T506
Test name
Test status
Simulation time 365022413582 ps
CPU time 2387.67 seconds
Started May 12 02:57:02 PM PDT 24
Finished May 12 03:36:51 PM PDT 24
Peak memory 287216 kb
Host smart-dd1d4a75-3d2a-4bf7-a4e1-47dd6392376f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731814522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2731814522
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3946967970
Short name T611
Test name
Test status
Simulation time 17928085344 ps
CPU time 1806.48 seconds
Started May 12 02:56:57 PM PDT 24
Finished May 12 03:27:05 PM PDT 24
Peak memory 289468 kb
Host smart-b2e26124-3575-4045-b06b-32bd62a4f563
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946967970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3946967970
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3447864477
Short name T297
Test name
Test status
Simulation time 7739066287 ps
CPU time 300.07 seconds
Started May 12 02:57:00 PM PDT 24
Finished May 12 03:02:00 PM PDT 24
Peak memory 248000 kb
Host smart-ddfbb35c-3734-4a7e-90ec-12f110ef7138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447864477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3447864477
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1377897723
Short name T356
Test name
Test status
Simulation time 3192165064 ps
CPU time 55.13 seconds
Started May 12 02:56:55 PM PDT 24
Finished May 12 02:57:50 PM PDT 24
Peak memory 256204 kb
Host smart-79dff3c5-885b-4355-bd5b-45e88dc53df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
97723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1377897723
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1721335012
Short name T441
Test name
Test status
Simulation time 444935193 ps
CPU time 26.34 seconds
Started May 12 02:56:54 PM PDT 24
Finished May 12 02:57:21 PM PDT 24
Peak memory 256024 kb
Host smart-d364422a-81e3-406b-beb1-714b390a0d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17213
35012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1721335012
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2063293527
Short name T39
Test name
Test status
Simulation time 720064778 ps
CPU time 40.74 seconds
Started May 12 02:57:01 PM PDT 24
Finished May 12 02:57:42 PM PDT 24
Peak memory 248736 kb
Host smart-fba085e5-c449-4602-a050-36c8451e9a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
93527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2063293527
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3314348621
Short name T647
Test name
Test status
Simulation time 276901760 ps
CPU time 23.79 seconds
Started May 12 02:56:56 PM PDT 24
Finished May 12 02:57:20 PM PDT 24
Peak memory 248720 kb
Host smart-7fb35c4a-31e6-4650-83ce-4436388f52b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33143
48621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3314348621
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.317145388
Short name T101
Test name
Test status
Simulation time 104000972495 ps
CPU time 3698.98 seconds
Started May 12 02:56:59 PM PDT 24
Finished May 12 03:58:39 PM PDT 24
Peak memory 289284 kb
Host smart-58537ac8-5958-4fa4-aa3b-11d783e6f925
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317145388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.317145388
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1759915957
Short name T395
Test name
Test status
Simulation time 31541584587 ps
CPU time 2170.27 seconds
Started May 12 02:57:01 PM PDT 24
Finished May 12 03:33:12 PM PDT 24
Peak memory 281576 kb
Host smart-a0757bba-0d69-4afa-bb62-8ef32ad85f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759915957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1759915957
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1384540759
Short name T465
Test name
Test status
Simulation time 45189248 ps
CPU time 4.03 seconds
Started May 12 02:57:03 PM PDT 24
Finished May 12 02:57:07 PM PDT 24
Peak memory 250712 kb
Host smart-5d4ffeeb-cf3a-4bf0-b425-d5a1c954a761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13845
40759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1384540759
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2534641202
Short name T670
Test name
Test status
Simulation time 859728940 ps
CPU time 48.55 seconds
Started May 12 02:57:04 PM PDT 24
Finished May 12 02:57:53 PM PDT 24
Peak memory 255844 kb
Host smart-39444ed6-6ccf-4d46-81ff-8ab7614cf865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
41202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2534641202
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3317406143
Short name T319
Test name
Test status
Simulation time 185761221060 ps
CPU time 2422.76 seconds
Started May 12 02:57:04 PM PDT 24
Finished May 12 03:37:28 PM PDT 24
Peak memory 272420 kb
Host smart-fe9b9900-eb73-46b5-8696-43928a894a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317406143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3317406143
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.973509820
Short name T498
Test name
Test status
Simulation time 18142602040 ps
CPU time 1184.4 seconds
Started May 12 02:57:02 PM PDT 24
Finished May 12 03:16:47 PM PDT 24
Peak memory 266188 kb
Host smart-368b1f65-7d2b-42a0-9e69-ebb5c019563f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973509820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.973509820
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1239708529
Short name T488
Test name
Test status
Simulation time 21572093548 ps
CPU time 232.23 seconds
Started May 12 02:57:04 PM PDT 24
Finished May 12 03:00:57 PM PDT 24
Peak memory 256472 kb
Host smart-2339278b-a324-4db7-bc99-c87df65586d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239708529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1239708529
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3509999039
Short name T653
Test name
Test status
Simulation time 6146017567 ps
CPU time 42.82 seconds
Started May 12 02:57:02 PM PDT 24
Finished May 12 02:57:45 PM PDT 24
Peak memory 256008 kb
Host smart-bc254e00-ecee-4b36-925d-076224b2f196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35099
99039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3509999039
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2952016994
Short name T632
Test name
Test status
Simulation time 815187753 ps
CPU time 54.56 seconds
Started May 12 02:57:03 PM PDT 24
Finished May 12 02:57:58 PM PDT 24
Peak memory 248720 kb
Host smart-896ca988-6e7d-4613-b4e6-40bbacbea352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
16994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2952016994
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.482231261
Short name T561
Test name
Test status
Simulation time 3829027766 ps
CPU time 39.6 seconds
Started May 12 02:56:59 PM PDT 24
Finished May 12 02:57:39 PM PDT 24
Peak memory 248840 kb
Host smart-691a3ad3-6d0d-40c9-8d3b-91ea28581067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48223
1261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.482231261
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1772718807
Short name T517
Test name
Test status
Simulation time 22645115208 ps
CPU time 1701.51 seconds
Started May 12 02:57:06 PM PDT 24
Finished May 12 03:25:29 PM PDT 24
Peak memory 285312 kb
Host smart-85c8888a-abf6-4099-bb3f-f0e48f6a475c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772718807 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1772718807
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2726366302
Short name T526
Test name
Test status
Simulation time 12878611971 ps
CPU time 681.44 seconds
Started May 12 02:57:06 PM PDT 24
Finished May 12 03:08:28 PM PDT 24
Peak memory 272380 kb
Host smart-be62a605-d718-41f2-a08a-f29fd0ccf58a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726366302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2726366302
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.574151520
Short name T638
Test name
Test status
Simulation time 867941661 ps
CPU time 82.85 seconds
Started May 12 02:57:05 PM PDT 24
Finished May 12 02:58:29 PM PDT 24
Peak memory 257036 kb
Host smart-e91ea2f0-195d-4002-9f5f-d966d4aac96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57415
1520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.574151520
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1576829348
Short name T333
Test name
Test status
Simulation time 162695016949 ps
CPU time 2757.31 seconds
Started May 12 02:57:10 PM PDT 24
Finished May 12 03:43:08 PM PDT 24
Peak memory 287500 kb
Host smart-935241fd-5c9a-46c9-8c6a-db657c85ba7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576829348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1576829348
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2174071318
Short name T105
Test name
Test status
Simulation time 38295774299 ps
CPU time 2005.8 seconds
Started May 12 02:57:10 PM PDT 24
Finished May 12 03:30:37 PM PDT 24
Peak memory 284676 kb
Host smart-8380f153-eba4-4462-a94c-d7bd956e68e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174071318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2174071318
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3788320248
Short name T423
Test name
Test status
Simulation time 1361472704 ps
CPU time 36.17 seconds
Started May 12 02:57:06 PM PDT 24
Finished May 12 02:57:42 PM PDT 24
Peak memory 248740 kb
Host smart-c3a9ec1f-cd9f-445c-bd19-ab3fe00ca09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37883
20248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3788320248
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.742147372
Short name T451
Test name
Test status
Simulation time 2754861506 ps
CPU time 52.66 seconds
Started May 12 02:57:06 PM PDT 24
Finished May 12 02:57:59 PM PDT 24
Peak memory 256140 kb
Host smart-6cd3d8ab-0d4c-43ae-9870-dd37c1deeae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74214
7372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.742147372
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1019700321
Short name T631
Test name
Test status
Simulation time 769723106 ps
CPU time 52.55 seconds
Started May 12 02:57:07 PM PDT 24
Finished May 12 02:58:00 PM PDT 24
Peak memory 249184 kb
Host smart-9d16d871-4744-45f3-a0bc-2e8bed237343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
00321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1019700321
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1621513824
Short name T513
Test name
Test status
Simulation time 23962473079 ps
CPU time 1666.8 seconds
Started May 12 02:57:09 PM PDT 24
Finished May 12 03:24:56 PM PDT 24
Peak memory 289244 kb
Host smart-e1d6dc67-9946-4e6c-bda1-e74a625d72c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621513824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1621513824
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.798575154
Short name T53
Test name
Test status
Simulation time 29721096424 ps
CPU time 2126.14 seconds
Started May 12 02:57:11 PM PDT 24
Finished May 12 03:32:38 PM PDT 24
Peak memory 282476 kb
Host smart-3d06847f-2bfb-4e17-8ea6-65fd1a2f30da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798575154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.798575154
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2995561788
Short name T592
Test name
Test status
Simulation time 2043119942 ps
CPU time 149.1 seconds
Started May 12 02:57:09 PM PDT 24
Finished May 12 02:59:38 PM PDT 24
Peak memory 249736 kb
Host smart-b0438e40-d48b-4170-a08b-8ac70b4e4ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29955
61788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2995561788
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1760181835
Short name T385
Test name
Test status
Simulation time 2180170496 ps
CPU time 14.21 seconds
Started May 12 02:57:11 PM PDT 24
Finished May 12 02:57:26 PM PDT 24
Peak memory 254820 kb
Host smart-86db0245-b67f-4c2c-bfb1-a5b6fe1776b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
81835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1760181835
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2689827243
Short name T305
Test name
Test status
Simulation time 16384274255 ps
CPU time 548.01 seconds
Started May 12 02:57:11 PM PDT 24
Finished May 12 03:06:19 PM PDT 24
Peak memory 255992 kb
Host smart-55d9e7b9-ecd9-41d8-b18f-1813c2a8b657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689827243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2689827243
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2689546363
Short name T228
Test name
Test status
Simulation time 1186987552 ps
CPU time 67.03 seconds
Started May 12 02:57:12 PM PDT 24
Finished May 12 02:58:19 PM PDT 24
Peak memory 255504 kb
Host smart-cc3ecb30-47f0-49c3-9967-abb98ad99046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895
46363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2689546363
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1285189273
Short name T419
Test name
Test status
Simulation time 317471461 ps
CPU time 31.24 seconds
Started May 12 02:57:10 PM PDT 24
Finished May 12 02:57:41 PM PDT 24
Peak memory 249224 kb
Host smart-b452ca5b-4fa5-4644-bc67-95efc9154414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
89273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1285189273
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3841565730
Short name T553
Test name
Test status
Simulation time 514435348 ps
CPU time 16.69 seconds
Started May 12 02:57:12 PM PDT 24
Finished May 12 02:57:29 PM PDT 24
Peak memory 248724 kb
Host smart-5b91d741-1e42-4d5a-b9dc-8fa17811362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38415
65730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3841565730
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1720626743
Short name T682
Test name
Test status
Simulation time 459196357 ps
CPU time 24.78 seconds
Started May 12 02:57:09 PM PDT 24
Finished May 12 02:57:34 PM PDT 24
Peak memory 248740 kb
Host smart-bad795af-97c1-4ac5-b6be-691f1b5493bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
26743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1720626743
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1745286031
Short name T440
Test name
Test status
Simulation time 23110015789 ps
CPU time 1296.89 seconds
Started May 12 02:57:14 PM PDT 24
Finished May 12 03:18:51 PM PDT 24
Peak memory 289392 kb
Host smart-bfafa63a-11a4-4a79-8cb2-858eba330525
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745286031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1745286031
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1338097986
Short name T456
Test name
Test status
Simulation time 207051001 ps
CPU time 9.44 seconds
Started May 12 02:57:13 PM PDT 24
Finished May 12 02:57:23 PM PDT 24
Peak memory 248920 kb
Host smart-3bf6ba61-0bf6-483a-b0c8-c4796c9f7bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
97986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1338097986
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2634377096
Short name T18
Test name
Test status
Simulation time 2457813476 ps
CPU time 35.28 seconds
Started May 12 02:57:13 PM PDT 24
Finished May 12 02:57:49 PM PDT 24
Peak memory 256320 kb
Host smart-699d2670-c21f-4470-a812-e1965aa9327a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26343
77096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2634377096
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2752402439
Short name T590
Test name
Test status
Simulation time 144414948191 ps
CPU time 1552.01 seconds
Started May 12 02:57:15 PM PDT 24
Finished May 12 03:23:08 PM PDT 24
Peak memory 285596 kb
Host smart-cae4bf31-3ae0-4efe-8051-9b053573c02a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752402439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2752402439
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3855951630
Short name T43
Test name
Test status
Simulation time 18604200098 ps
CPU time 1498.46 seconds
Started May 12 02:57:16 PM PDT 24
Finished May 12 03:22:16 PM PDT 24
Peak memory 273392 kb
Host smart-c25473e7-08c3-430b-bfc2-2321411bfb8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855951630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3855951630
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.135944627
Short name T309
Test name
Test status
Simulation time 54055643080 ps
CPU time 430.24 seconds
Started May 12 02:57:16 PM PDT 24
Finished May 12 03:04:27 PM PDT 24
Peak memory 248228 kb
Host smart-f030fc9e-857c-4d28-a668-6ef1184e5793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135944627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.135944627
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1051177623
Short name T538
Test name
Test status
Simulation time 981779928 ps
CPU time 56.92 seconds
Started May 12 02:57:14 PM PDT 24
Finished May 12 02:58:11 PM PDT 24
Peak memory 248736 kb
Host smart-4c643948-f5db-4d3c-8023-5a5d1c824607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
77623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1051177623
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2242338741
Short name T490
Test name
Test status
Simulation time 325880170 ps
CPU time 11.95 seconds
Started May 12 02:57:13 PM PDT 24
Finished May 12 02:57:26 PM PDT 24
Peak memory 247384 kb
Host smart-deeb1d6c-fa63-4999-9ba1-2a390958087c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
38741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2242338741
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2696631080
Short name T572
Test name
Test status
Simulation time 639230245 ps
CPU time 30.01 seconds
Started May 12 02:57:16 PM PDT 24
Finished May 12 02:57:46 PM PDT 24
Peak memory 255928 kb
Host smart-7c7cdd9a-57ee-4dc8-b4c1-21a3ee8a9527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26966
31080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2696631080
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.206263499
Short name T347
Test name
Test status
Simulation time 1350113103 ps
CPU time 22.36 seconds
Started May 12 02:57:15 PM PDT 24
Finished May 12 02:57:37 PM PDT 24
Peak memory 248780 kb
Host smart-3a816f05-c4ec-4077-bd8f-81835f03ca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
3499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.206263499
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1065842433
Short name T657
Test name
Test status
Simulation time 8640728579 ps
CPU time 902.85 seconds
Started May 12 02:57:20 PM PDT 24
Finished May 12 03:12:24 PM PDT 24
Peak memory 288600 kb
Host smart-f092674a-8a42-4b8d-95ef-51cc7f594f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065842433 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1065842433
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2459518167
Short name T672
Test name
Test status
Simulation time 122919256743 ps
CPU time 2404.46 seconds
Started May 12 02:57:23 PM PDT 24
Finished May 12 03:37:28 PM PDT 24
Peak memory 281600 kb
Host smart-e83178d9-a944-4082-93ed-5c719ee60087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459518167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2459518167
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.299050898
Short name T494
Test name
Test status
Simulation time 27403549811 ps
CPU time 155.04 seconds
Started May 12 02:57:19 PM PDT 24
Finished May 12 02:59:55 PM PDT 24
Peak memory 256984 kb
Host smart-9f558b35-536d-4e20-987a-fc2fd660b038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29905
0898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.299050898
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1953109337
Short name T408
Test name
Test status
Simulation time 61513721 ps
CPU time 5.02 seconds
Started May 12 02:57:19 PM PDT 24
Finished May 12 02:57:25 PM PDT 24
Peak memory 240508 kb
Host smart-b308b3a8-5977-4dad-8b02-d60457490b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19531
09337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1953109337
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.139809567
Short name T315
Test name
Test status
Simulation time 11907124748 ps
CPU time 998.2 seconds
Started May 12 02:57:23 PM PDT 24
Finished May 12 03:14:01 PM PDT 24
Peak memory 268284 kb
Host smart-d0229f30-e074-4c72-9ff8-de4d6239b7e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139809567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.139809567
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3540315267
Short name T530
Test name
Test status
Simulation time 70003014292 ps
CPU time 2263.37 seconds
Started May 12 02:57:23 PM PDT 24
Finished May 12 03:35:08 PM PDT 24
Peak memory 273428 kb
Host smart-15b542b1-dd90-4bbc-8d49-d08f9d19bc3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540315267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3540315267
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1904046234
Short name T528
Test name
Test status
Simulation time 224471766 ps
CPU time 7 seconds
Started May 12 02:57:19 PM PDT 24
Finished May 12 02:57:26 PM PDT 24
Peak memory 248720 kb
Host smart-9f52c6c8-cd74-4d82-8604-8db23bf1c7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
46234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1904046234
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1498202645
Short name T691
Test name
Test status
Simulation time 1131693363 ps
CPU time 22.41 seconds
Started May 12 02:57:18 PM PDT 24
Finished May 12 02:57:41 PM PDT 24
Peak memory 247428 kb
Host smart-7fea62d2-1788-4dc0-8a60-2d83b91873bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14982
02645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1498202645
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1044106383
Short name T696
Test name
Test status
Simulation time 631593683 ps
CPU time 43.79 seconds
Started May 12 02:57:24 PM PDT 24
Finished May 12 02:58:09 PM PDT 24
Peak memory 248716 kb
Host smart-fbc716cd-d517-4ec4-8ece-552c8a19875f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
06383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1044106383
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.574726511
Short name T85
Test name
Test status
Simulation time 193930595 ps
CPU time 13.35 seconds
Started May 12 02:57:19 PM PDT 24
Finished May 12 02:57:33 PM PDT 24
Peak memory 256948 kb
Host smart-9a082a69-b803-4a5d-8882-1adda9aa5b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57472
6511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.574726511
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.405176942
Short name T194
Test name
Test status
Simulation time 20865479399 ps
CPU time 1955.83 seconds
Started May 12 02:57:24 PM PDT 24
Finished May 12 03:30:01 PM PDT 24
Peak memory 289808 kb
Host smart-dc1fca31-183b-47d9-9958-0ee7cb47213f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405176942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.405176942
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2387982699
Short name T677
Test name
Test status
Simulation time 87676159245 ps
CPU time 3660.74 seconds
Started May 12 02:57:27 PM PDT 24
Finished May 12 03:58:28 PM PDT 24
Peak memory 320540 kb
Host smart-1edfb6c2-b892-4b7c-8597-4f9ff3fd14ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387982699 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2387982699
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4205609103
Short name T35
Test name
Test status
Simulation time 32624915093 ps
CPU time 2397.76 seconds
Started May 12 02:57:29 PM PDT 24
Finished May 12 03:37:28 PM PDT 24
Peak memory 288844 kb
Host smart-af5c5ce3-2a77-4644-9356-45352c65057e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205609103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4205609103
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4257890829
Short name T509
Test name
Test status
Simulation time 95128177 ps
CPU time 7.4 seconds
Started May 12 02:57:27 PM PDT 24
Finished May 12 02:57:35 PM PDT 24
Peak memory 240464 kb
Host smart-20ee271b-002a-47b2-8e74-cb2148585e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
90829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4257890829
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3948975726
Short name T635
Test name
Test status
Simulation time 116877841 ps
CPU time 11.98 seconds
Started May 12 02:57:29 PM PDT 24
Finished May 12 02:57:41 PM PDT 24
Peak memory 254700 kb
Host smart-f2fea171-a63e-4009-9a52-8207e1196874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
75726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3948975726
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1885307687
Short name T328
Test name
Test status
Simulation time 188711089623 ps
CPU time 1535.17 seconds
Started May 12 02:57:29 PM PDT 24
Finished May 12 03:23:05 PM PDT 24
Peak memory 288712 kb
Host smart-0e804333-dde9-42d5-9c68-5669d8ffd733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885307687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1885307687
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1469679113
Short name T398
Test name
Test status
Simulation time 15119255368 ps
CPU time 630.52 seconds
Started May 12 02:57:29 PM PDT 24
Finished May 12 03:08:00 PM PDT 24
Peak memory 265516 kb
Host smart-4763857d-fc01-492a-8d6c-92f8822602e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469679113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1469679113
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2695068073
Short name T365
Test name
Test status
Simulation time 720171694 ps
CPU time 44.4 seconds
Started May 12 02:57:27 PM PDT 24
Finished May 12 02:58:12 PM PDT 24
Peak memory 248732 kb
Host smart-f5f7effd-a535-41f7-9309-04a973af457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
68073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2695068073
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1938662774
Short name T618
Test name
Test status
Simulation time 756421412 ps
CPU time 51.57 seconds
Started May 12 02:57:27 PM PDT 24
Finished May 12 02:58:19 PM PDT 24
Peak memory 249092 kb
Host smart-c5dda008-fb1f-46e5-a882-d007d43801df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386
62774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1938662774
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4063796512
Short name T462
Test name
Test status
Simulation time 1775416203 ps
CPU time 40.15 seconds
Started May 12 02:57:28 PM PDT 24
Finished May 12 02:58:09 PM PDT 24
Peak memory 256308 kb
Host smart-d3b3fbda-03b8-4596-8081-ce0a9762d788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
96512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4063796512
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3643880070
Short name T354
Test name
Test status
Simulation time 2886128755 ps
CPU time 45.66 seconds
Started May 12 02:57:26 PM PDT 24
Finished May 12 02:58:12 PM PDT 24
Peak memory 248836 kb
Host smart-5818ccf4-a14c-47c6-a4c1-84fac0d8419d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36438
80070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3643880070
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.610328178
Short name T199
Test name
Test status
Simulation time 153618912 ps
CPU time 3.64 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 02:55:04 PM PDT 24
Peak memory 248892 kb
Host smart-175424df-bad0-44af-8fd5-1be8f8db3bb6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=610328178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.610328178
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3122813152
Short name T468
Test name
Test status
Simulation time 15526740564 ps
CPU time 1220 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 03:15:20 PM PDT 24
Peak memory 272476 kb
Host smart-a084dc0f-8112-4970-baa0-abdd56188f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122813152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3122813152
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4270506555
Short name T340
Test name
Test status
Simulation time 380037049 ps
CPU time 16.9 seconds
Started May 12 02:54:57 PM PDT 24
Finished May 12 02:55:14 PM PDT 24
Peak memory 240540 kb
Host smart-e1822425-4f8f-4376-b2d6-1821809f7ed0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4270506555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4270506555
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3707342804
Short name T486
Test name
Test status
Simulation time 4472313896 ps
CPU time 212.29 seconds
Started May 12 02:54:57 PM PDT 24
Finished May 12 02:58:29 PM PDT 24
Peak memory 249832 kb
Host smart-67b015b7-2491-4b10-a31d-114db2e96d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37073
42804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3707342804
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.596743299
Short name T71
Test name
Test status
Simulation time 4194384594 ps
CPU time 59.97 seconds
Started May 12 02:54:53 PM PDT 24
Finished May 12 02:55:53 PM PDT 24
Peak memory 256908 kb
Host smart-df572e63-da4b-4f4c-91a7-809efd6b5166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59674
3299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.596743299
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.292736365
Short name T430
Test name
Test status
Simulation time 59676129660 ps
CPU time 1091.62 seconds
Started May 12 02:54:56 PM PDT 24
Finished May 12 03:13:08 PM PDT 24
Peak memory 272484 kb
Host smart-97a377fc-38d2-46db-9f30-5fa8723e7229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292736365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.292736365
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2480035533
Short name T477
Test name
Test status
Simulation time 53426485162 ps
CPU time 1384.82 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 03:18:05 PM PDT 24
Peak memory 289740 kb
Host smart-7b587333-32d9-49d9-b009-be95345dc614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480035533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2480035533
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1802019946
Short name T613
Test name
Test status
Simulation time 21612288096 ps
CPU time 430.18 seconds
Started May 12 02:54:56 PM PDT 24
Finished May 12 03:02:07 PM PDT 24
Peak memory 248008 kb
Host smart-d580aeb1-790c-4d24-a84f-95ecba0bf6a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802019946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1802019946
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2585238283
Short name T362
Test name
Test status
Simulation time 101468001 ps
CPU time 11.47 seconds
Started May 12 02:54:53 PM PDT 24
Finished May 12 02:55:05 PM PDT 24
Peak memory 249040 kb
Host smart-2bfdd775-4ba8-4d8e-a7e6-557f97c840e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
38283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2585238283
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.864741643
Short name T401
Test name
Test status
Simulation time 44820713 ps
CPU time 2.84 seconds
Started May 12 02:54:51 PM PDT 24
Finished May 12 02:54:55 PM PDT 24
Peak memory 239240 kb
Host smart-adee2924-ca3f-498b-b36c-9d36ba687dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86474
1643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.864741643
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2154918518
Short name T12
Test name
Test status
Simulation time 780895351 ps
CPU time 13.51 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 02:55:14 PM PDT 24
Peak memory 277600 kb
Host smart-10242210-155f-4f7d-b530-44e69ac4d8e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2154918518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2154918518
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3551943755
Short name T437
Test name
Test status
Simulation time 2967678885 ps
CPU time 48.58 seconds
Started May 12 02:54:57 PM PDT 24
Finished May 12 02:55:46 PM PDT 24
Peak memory 256132 kb
Host smart-b466b755-8011-4600-83f9-02e335822bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
43755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3551943755
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2254704443
Short name T571
Test name
Test status
Simulation time 263404595 ps
CPU time 17.58 seconds
Started May 12 02:54:51 PM PDT 24
Finished May 12 02:55:09 PM PDT 24
Peak memory 254208 kb
Host smart-002c24cd-2924-4cb2-b5b3-a7312425220b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
04443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2254704443
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2019608278
Short name T90
Test name
Test status
Simulation time 69132809192 ps
CPU time 4275.98 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 04:06:16 PM PDT 24
Peak memory 297792 kb
Host smart-c68e46db-a458-4674-b288-bca597050f5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019608278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2019608278
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3915323573
Short name T450
Test name
Test status
Simulation time 21754742603 ps
CPU time 1291.2 seconds
Started May 12 02:57:35 PM PDT 24
Finished May 12 03:19:07 PM PDT 24
Peak memory 286624 kb
Host smart-c9e03fbd-5fb4-4369-afe9-81a2fb202f25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915323573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3915323573
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.571367396
Short name T580
Test name
Test status
Simulation time 1371891206 ps
CPU time 104.99 seconds
Started May 12 02:57:38 PM PDT 24
Finished May 12 02:59:23 PM PDT 24
Peak memory 249872 kb
Host smart-0ed36797-59d9-4beb-bccb-7d9378402314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57136
7396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.571367396
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.39387451
Short name T62
Test name
Test status
Simulation time 3495254028 ps
CPU time 57.32 seconds
Started May 12 02:57:31 PM PDT 24
Finished May 12 02:58:29 PM PDT 24
Peak memory 256064 kb
Host smart-cca09dc8-cbce-4670-8c5a-abf1637e627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.39387451
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3445320007
Short name T662
Test name
Test status
Simulation time 27428168723 ps
CPU time 1908.65 seconds
Started May 12 02:57:37 PM PDT 24
Finished May 12 03:29:27 PM PDT 24
Peak memory 266224 kb
Host smart-9543563a-0365-49b8-b761-a41a2cd24a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445320007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3445320007
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.570883116
Short name T27
Test name
Test status
Simulation time 42368293349 ps
CPU time 797.45 seconds
Started May 12 02:57:39 PM PDT 24
Finished May 12 03:10:58 PM PDT 24
Peak memory 272684 kb
Host smart-6e677eaa-1f11-4f1b-968e-6a7999ed550c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570883116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.570883116
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4189576561
Short name T218
Test name
Test status
Simulation time 8881788141 ps
CPU time 150.34 seconds
Started May 12 02:57:36 PM PDT 24
Finished May 12 03:00:07 PM PDT 24
Peak memory 247064 kb
Host smart-6ad720ff-f06f-4cb8-bfe1-e9ef1d13da07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189576561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4189576561
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2653903254
Short name T588
Test name
Test status
Simulation time 808608816 ps
CPU time 24.96 seconds
Started May 12 02:57:30 PM PDT 24
Finished May 12 02:57:55 PM PDT 24
Peak memory 248764 kb
Host smart-6d22cfae-cd6e-4e0d-9192-af82f1758261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
03254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2653903254
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2414674464
Short name T46
Test name
Test status
Simulation time 1613475465 ps
CPU time 70.24 seconds
Started May 12 02:57:31 PM PDT 24
Finished May 12 02:58:42 PM PDT 24
Peak memory 254872 kb
Host smart-c2c1d13f-e10d-4499-be24-ec99ac087c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24146
74464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2414674464
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.659678226
Short name T258
Test name
Test status
Simulation time 612342979 ps
CPU time 41.25 seconds
Started May 12 02:57:35 PM PDT 24
Finished May 12 02:58:17 PM PDT 24
Peak memory 248732 kb
Host smart-bf3ac72c-9649-4e60-b235-d90756a548a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65967
8226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.659678226
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2289022251
Short name T357
Test name
Test status
Simulation time 136165164 ps
CPU time 6.05 seconds
Started May 12 02:57:32 PM PDT 24
Finished May 12 02:57:38 PM PDT 24
Peak memory 240572 kb
Host smart-aba68d9b-3c8f-4ec2-8854-958c11ae8f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
22251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2289022251
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3590599364
Short name T661
Test name
Test status
Simulation time 164617001168 ps
CPU time 2409.1 seconds
Started May 12 02:57:38 PM PDT 24
Finished May 12 03:37:48 PM PDT 24
Peak memory 273172 kb
Host smart-b07ea394-e448-4ec3-a4fc-1cd56c48eb58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590599364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3590599364
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.376097144
Short name T23
Test name
Test status
Simulation time 39922438691 ps
CPU time 2162.13 seconds
Started May 12 02:57:50 PM PDT 24
Finished May 12 03:33:53 PM PDT 24
Peak memory 288892 kb
Host smart-4b14e8d1-dbe7-4056-a32f-b34a14ecb9ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376097144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.376097144
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3109320079
Short name T674
Test name
Test status
Simulation time 194895610 ps
CPU time 3.71 seconds
Started May 12 02:57:44 PM PDT 24
Finished May 12 02:57:48 PM PDT 24
Peak memory 239300 kb
Host smart-eb1c1fbe-d9b6-42c4-982a-3001225909f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
20079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3109320079
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1676722779
Short name T73
Test name
Test status
Simulation time 590584452 ps
CPU time 33.8 seconds
Started May 12 02:57:46 PM PDT 24
Finished May 12 02:58:20 PM PDT 24
Peak memory 255536 kb
Host smart-cbea9ff4-547f-4249-a667-9af6545a57ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767
22779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1676722779
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1962803412
Short name T286
Test name
Test status
Simulation time 27733218369 ps
CPU time 1357.54 seconds
Started May 12 02:57:51 PM PDT 24
Finished May 12 03:20:29 PM PDT 24
Peak memory 283596 kb
Host smart-05b10751-28d4-4dcc-8b99-247c7e3cd462
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962803412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1962803412
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.302656909
Short name T627
Test name
Test status
Simulation time 140117585670 ps
CPU time 2471.54 seconds
Started May 12 02:57:53 PM PDT 24
Finished May 12 03:39:05 PM PDT 24
Peak memory 289156 kb
Host smart-e374e499-c053-4162-b44f-5a0563c29a1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302656909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.302656909
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1971252761
Short name T80
Test name
Test status
Simulation time 3232878328 ps
CPU time 143.65 seconds
Started May 12 02:57:51 PM PDT 24
Finished May 12 03:00:15 PM PDT 24
Peak memory 254660 kb
Host smart-4a658461-835d-46cd-bf4e-b645bed6d02d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971252761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1971252761
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3406413917
Short name T612
Test name
Test status
Simulation time 1417054613 ps
CPU time 51.73 seconds
Started May 12 02:57:42 PM PDT 24
Finished May 12 02:58:34 PM PDT 24
Peak memory 248776 kb
Host smart-1d309c9d-86b1-4583-a05f-e449eb9cc3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
13917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3406413917
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4264296941
Short name T455
Test name
Test status
Simulation time 1946252071 ps
CPU time 12.9 seconds
Started May 12 02:57:44 PM PDT 24
Finished May 12 02:57:57 PM PDT 24
Peak memory 248528 kb
Host smart-dbf340f6-aa80-426a-b41e-277d727cff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
96941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4264296941
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2134818885
Short name T466
Test name
Test status
Simulation time 61162582 ps
CPU time 8.4 seconds
Started May 12 02:57:46 PM PDT 24
Finished May 12 02:57:54 PM PDT 24
Peak memory 254016 kb
Host smart-3002fc12-584b-4b22-af4e-8f56cd457f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
18885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2134818885
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.296342648
Short name T539
Test name
Test status
Simulation time 382560500 ps
CPU time 16.89 seconds
Started May 12 02:57:39 PM PDT 24
Finished May 12 02:57:56 PM PDT 24
Peak memory 248708 kb
Host smart-36de30ff-16a7-4b7d-aae1-5a1e255e24bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
2648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.296342648
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2401518274
Short name T89
Test name
Test status
Simulation time 3864458470 ps
CPU time 156.13 seconds
Started May 12 02:57:52 PM PDT 24
Finished May 12 03:00:28 PM PDT 24
Peak memory 255788 kb
Host smart-e95f78e3-d615-41f1-931e-099acbfee5b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401518274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2401518274
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.30105427
Short name T238
Test name
Test status
Simulation time 159488899444 ps
CPU time 1268.21 seconds
Started May 12 02:57:52 PM PDT 24
Finished May 12 03:19:01 PM PDT 24
Peak memory 281704 kb
Host smart-57d3a158-133c-4afb-9c33-41f2929662bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105427 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.30105427
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4291201884
Short name T94
Test name
Test status
Simulation time 73043179205 ps
CPU time 2382.64 seconds
Started May 12 02:57:58 PM PDT 24
Finished May 12 03:37:41 PM PDT 24
Peak memory 289404 kb
Host smart-9ab2867c-d7b9-4c37-80f1-60f09001eebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291201884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4291201884
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2295591177
Short name T636
Test name
Test status
Simulation time 1110786229 ps
CPU time 59.01 seconds
Started May 12 02:57:57 PM PDT 24
Finished May 12 02:58:57 PM PDT 24
Peak memory 256136 kb
Host smart-7633345e-b490-4437-8620-c03cca10a1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22955
91177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2295591177
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.823880773
Short name T68
Test name
Test status
Simulation time 809390231 ps
CPU time 52.38 seconds
Started May 12 02:57:54 PM PDT 24
Finished May 12 02:58:47 PM PDT 24
Peak memory 248768 kb
Host smart-10a6a476-ddf0-4fb1-a60e-0ed9b6be0b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82388
0773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.823880773
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.658467288
Short name T280
Test name
Test status
Simulation time 50887667752 ps
CPU time 1539.58 seconds
Started May 12 02:58:00 PM PDT 24
Finished May 12 03:23:40 PM PDT 24
Peak memory 273368 kb
Host smart-cae88e2d-2134-4148-9c27-13890627f8fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658467288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.658467288
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1532281891
Short name T642
Test name
Test status
Simulation time 6686031135 ps
CPU time 129.91 seconds
Started May 12 02:57:58 PM PDT 24
Finished May 12 03:00:09 PM PDT 24
Peak memory 247980 kb
Host smart-a0349f4d-1c54-49d6-b4c5-b9ea610ee07d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532281891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1532281891
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.4046968587
Short name T606
Test name
Test status
Simulation time 82862344 ps
CPU time 5.34 seconds
Started May 12 02:57:57 PM PDT 24
Finished May 12 02:58:03 PM PDT 24
Peak memory 240556 kb
Host smart-5daf7a69-b443-4931-a3bb-6c0afe856e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40469
68587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4046968587
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1269040397
Short name T282
Test name
Test status
Simulation time 1339475097 ps
CPU time 19.16 seconds
Started May 12 02:57:58 PM PDT 24
Finished May 12 02:58:18 PM PDT 24
Peak memory 247428 kb
Host smart-9539b1dd-79cf-41d6-89ea-9b93d3c3d185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
40397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1269040397
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3004162531
Short name T109
Test name
Test status
Simulation time 1855998500 ps
CPU time 39.03 seconds
Started May 12 02:57:55 PM PDT 24
Finished May 12 02:58:34 PM PDT 24
Peak memory 255704 kb
Host smart-88dccea8-5cad-41c1-97dc-0cecb03599a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30041
62531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3004162531
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3149595698
Short name T355
Test name
Test status
Simulation time 1286028782 ps
CPU time 62.91 seconds
Started May 12 02:57:52 PM PDT 24
Finished May 12 02:58:55 PM PDT 24
Peak memory 255980 kb
Host smart-c0825686-7fab-4015-9602-139b7ea61321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
95698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3149595698
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.854440391
Short name T112
Test name
Test status
Simulation time 310863873904 ps
CPU time 1309.37 seconds
Started May 12 02:58:02 PM PDT 24
Finished May 12 03:19:52 PM PDT 24
Peak memory 265224 kb
Host smart-53426cda-1b20-4c3b-89b7-061842d3403a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854440391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.854440391
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2451618578
Short name T597
Test name
Test status
Simulation time 27280317942 ps
CPU time 359.46 seconds
Started May 12 02:58:04 PM PDT 24
Finished May 12 03:04:04 PM PDT 24
Peak memory 251060 kb
Host smart-cebd7b5f-10e3-4b4c-a7cc-09c220e88bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
18578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2451618578
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3369892454
Short name T78
Test name
Test status
Simulation time 663051295 ps
CPU time 15.88 seconds
Started May 12 02:58:02 PM PDT 24
Finished May 12 02:58:18 PM PDT 24
Peak memory 254560 kb
Host smart-8272406a-7e47-4c59-ae25-6004afdaadde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
92454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3369892454
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4062361640
Short name T217
Test name
Test status
Simulation time 92542499940 ps
CPU time 2757.53 seconds
Started May 12 02:58:04 PM PDT 24
Finished May 12 03:44:03 PM PDT 24
Peak memory 281664 kb
Host smart-2fc2640f-802a-425b-b4c5-55ecb09d2a4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062361640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4062361640
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1298499023
Short name T433
Test name
Test status
Simulation time 21131850047 ps
CPU time 985.77 seconds
Started May 12 02:58:05 PM PDT 24
Finished May 12 03:14:31 PM PDT 24
Peak memory 273528 kb
Host smart-bd1b7aca-ad77-4d62-a718-fee3c1500f6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298499023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1298499023
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1891906687
Short name T79
Test name
Test status
Simulation time 3610636759 ps
CPU time 149.81 seconds
Started May 12 02:58:07 PM PDT 24
Finished May 12 03:00:37 PM PDT 24
Peak memory 247064 kb
Host smart-454a20d6-0484-4a6d-be9b-3b38f69c0cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891906687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1891906687
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4248819924
Short name T570
Test name
Test status
Simulation time 801652404 ps
CPU time 15.82 seconds
Started May 12 02:58:03 PM PDT 24
Finished May 12 02:58:19 PM PDT 24
Peak memory 248768 kb
Host smart-ac851a17-e077-4b95-b39c-8057295f773d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42488
19924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4248819924
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1261160808
Short name T64
Test name
Test status
Simulation time 693422877 ps
CPU time 18.81 seconds
Started May 12 02:58:01 PM PDT 24
Finished May 12 02:58:20 PM PDT 24
Peak memory 256088 kb
Host smart-861aebb7-4ac2-4bb7-abfd-a3b098378874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
60808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1261160808
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3278833887
Short name T243
Test name
Test status
Simulation time 2438752661 ps
CPU time 39.58 seconds
Started May 12 02:58:02 PM PDT 24
Finished May 12 02:58:42 PM PDT 24
Peak memory 249268 kb
Host smart-08628cfd-f4b6-4195-8b4e-dab9dc0a74bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32788
33887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3278833887
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1396516609
Short name T272
Test name
Test status
Simulation time 275754246 ps
CPU time 34.86 seconds
Started May 12 02:58:02 PM PDT 24
Finished May 12 02:58:37 PM PDT 24
Peak memory 248736 kb
Host smart-40b04f94-318e-4919-8f12-bb5c2f26605d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965
16609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1396516609
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2492382142
Short name T241
Test name
Test status
Simulation time 56767009809 ps
CPU time 2343.13 seconds
Started May 12 02:58:06 PM PDT 24
Finished May 12 03:37:10 PM PDT 24
Peak memory 285768 kb
Host smart-c483e4bc-e9b2-4d8f-b5c3-5e917ceea06b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492382142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2492382142
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1116709626
Short name T414
Test name
Test status
Simulation time 10586880251 ps
CPU time 1162.95 seconds
Started May 12 02:58:12 PM PDT 24
Finished May 12 03:17:35 PM PDT 24
Peak memory 281580 kb
Host smart-ac21cd2f-b031-4a2a-8e45-964bbc8a421a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116709626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1116709626
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.34793111
Short name T32
Test name
Test status
Simulation time 11133584474 ps
CPU time 85.12 seconds
Started May 12 02:58:09 PM PDT 24
Finished May 12 02:59:34 PM PDT 24
Peak memory 248852 kb
Host smart-3269a9d0-c3a0-4c9f-95bb-086ab7edd1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.34793111
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.544832507
Short name T428
Test name
Test status
Simulation time 377044998 ps
CPU time 31.5 seconds
Started May 12 02:58:08 PM PDT 24
Finished May 12 02:58:40 PM PDT 24
Peak memory 255880 kb
Host smart-4efff205-2183-4f54-b81e-1ae6ddf45dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54483
2507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.544832507
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1439418482
Short name T648
Test name
Test status
Simulation time 133443036108 ps
CPU time 1113.58 seconds
Started May 12 02:58:11 PM PDT 24
Finished May 12 03:16:45 PM PDT 24
Peak memory 288584 kb
Host smart-048d45d9-b432-40e5-8253-afefeffd0bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439418482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1439418482
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2374723557
Short name T436
Test name
Test status
Simulation time 12710935108 ps
CPU time 1509.31 seconds
Started May 12 02:58:10 PM PDT 24
Finished May 12 03:23:20 PM PDT 24
Peak memory 281164 kb
Host smart-2e3b17ec-8508-44db-a242-7d5f3823c83c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374723557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2374723557
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.529931329
Short name T390
Test name
Test status
Simulation time 600667851 ps
CPU time 33.74 seconds
Started May 12 02:58:08 PM PDT 24
Finished May 12 02:58:42 PM PDT 24
Peak memory 248732 kb
Host smart-a0a315b2-9872-4ff3-bd86-f91c8bb91b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52993
1329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.529931329
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.894059037
Short name T277
Test name
Test status
Simulation time 436290322 ps
CPU time 27.01 seconds
Started May 12 02:58:08 PM PDT 24
Finished May 12 02:58:36 PM PDT 24
Peak memory 249228 kb
Host smart-c459d899-d5c3-4da1-b073-b42c0f9d659f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89405
9037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.894059037
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4122752720
Short name T70
Test name
Test status
Simulation time 327849372 ps
CPU time 18.72 seconds
Started May 12 02:58:12 PM PDT 24
Finished May 12 02:58:31 PM PDT 24
Peak memory 254904 kb
Host smart-abc8caf7-8556-4bb8-80ef-8133e65dd590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41227
52720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4122752720
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2597705724
Short name T420
Test name
Test status
Simulation time 865835473 ps
CPU time 50.98 seconds
Started May 12 02:58:06 PM PDT 24
Finished May 12 02:58:58 PM PDT 24
Peak memory 248808 kb
Host smart-76511196-dc71-41fb-85ac-2a80d6c298e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
05724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2597705724
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1232379726
Short name T5
Test name
Test status
Simulation time 45998371015 ps
CPU time 1748.86 seconds
Started May 12 02:58:15 PM PDT 24
Finished May 12 03:27:25 PM PDT 24
Peak memory 273340 kb
Host smart-a5f758f4-c54f-46c9-93be-96181c667d71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232379726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1232379726
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2903431650
Short name T507
Test name
Test status
Simulation time 1571331141 ps
CPU time 130.63 seconds
Started May 12 02:58:17 PM PDT 24
Finished May 12 03:00:28 PM PDT 24
Peak memory 256756 kb
Host smart-35615984-dcee-433e-8d38-fd440e692b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
31650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2903431650
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3125671977
Short name T664
Test name
Test status
Simulation time 376986370 ps
CPU time 23.35 seconds
Started May 12 02:58:15 PM PDT 24
Finished May 12 02:58:39 PM PDT 24
Peak memory 255524 kb
Host smart-fffc5b5d-e5ca-4799-95d0-6c66f1456a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31256
71977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3125671977
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2000565434
Short name T565
Test name
Test status
Simulation time 38285670814 ps
CPU time 1221.62 seconds
Started May 12 02:58:15 PM PDT 24
Finished May 12 03:18:38 PM PDT 24
Peak memory 270344 kb
Host smart-9c39c15d-187a-49e0-99c9-75a63e7213b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000565434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2000565434
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1455766745
Short name T313
Test name
Test status
Simulation time 12160486979 ps
CPU time 488.39 seconds
Started May 12 02:58:15 PM PDT 24
Finished May 12 03:06:24 PM PDT 24
Peak memory 254956 kb
Host smart-cf7bf1bf-0764-4f8a-a24d-a259178c88c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455766745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1455766745
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1986475633
Short name T438
Test name
Test status
Simulation time 722542623 ps
CPU time 51.52 seconds
Started May 12 02:58:11 PM PDT 24
Finished May 12 02:59:03 PM PDT 24
Peak memory 248744 kb
Host smart-cbbfd37d-e91a-4720-8b6b-04d7489c7edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864
75633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1986475633
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.785995065
Short name T643
Test name
Test status
Simulation time 767199399 ps
CPU time 41.17 seconds
Started May 12 02:58:15 PM PDT 24
Finished May 12 02:58:57 PM PDT 24
Peak memory 248732 kb
Host smart-5cae39d6-2ffa-4bca-bf45-cee178cd45b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78599
5065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.785995065
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2657220677
Short name T541
Test name
Test status
Simulation time 502771119 ps
CPU time 35.32 seconds
Started May 12 02:58:12 PM PDT 24
Finished May 12 02:58:48 PM PDT 24
Peak memory 256048 kb
Host smart-c524a75d-5e47-47d9-9a9f-88f516c20855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
20677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2657220677
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2939545432
Short name T193
Test name
Test status
Simulation time 20998226357 ps
CPU time 2031.89 seconds
Started May 12 02:58:19 PM PDT 24
Finished May 12 03:32:12 PM PDT 24
Peak memory 305992 kb
Host smart-f2c6ce41-c385-48da-b449-19b803b4556d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939545432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2939545432
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1329425358
Short name T236
Test name
Test status
Simulation time 46569968366 ps
CPU time 2470.69 seconds
Started May 12 02:58:20 PM PDT 24
Finished May 12 03:39:32 PM PDT 24
Peak memory 283076 kb
Host smart-a6eaaef5-14be-4057-a1f4-f3a3f30dfdda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329425358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1329425358
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3315462376
Short name T552
Test name
Test status
Simulation time 34147411456 ps
CPU time 1067.39 seconds
Started May 12 02:58:26 PM PDT 24
Finished May 12 03:16:14 PM PDT 24
Peak memory 273372 kb
Host smart-61b95835-0f1d-4894-892f-58ab4459a8e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315462376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3315462376
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2286550265
Short name T380
Test name
Test status
Simulation time 6247477136 ps
CPU time 80.09 seconds
Started May 12 02:58:21 PM PDT 24
Finished May 12 02:59:42 PM PDT 24
Peak memory 256968 kb
Host smart-de8a4d99-34f0-43dc-be6a-026fb9588bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
50265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2286550265
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.463574206
Short name T417
Test name
Test status
Simulation time 1351350822 ps
CPU time 33.77 seconds
Started May 12 02:58:22 PM PDT 24
Finished May 12 02:58:56 PM PDT 24
Peak memory 249136 kb
Host smart-003f67e0-8e00-4066-b0d5-e1f0ec830340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46357
4206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.463574206
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1342406652
Short name T700
Test name
Test status
Simulation time 22014452114 ps
CPU time 1706.12 seconds
Started May 12 02:58:25 PM PDT 24
Finished May 12 03:26:52 PM PDT 24
Peak memory 289460 kb
Host smart-c5c5e108-861e-4f7d-86f0-87f318735030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342406652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1342406652
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2322701001
Short name T223
Test name
Test status
Simulation time 8118087322 ps
CPU time 335.91 seconds
Started May 12 02:58:25 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 248316 kb
Host smart-7a370737-e894-47b5-876e-20ea318955c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322701001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2322701001
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2172041561
Short name T366
Test name
Test status
Simulation time 2635691120 ps
CPU time 48.33 seconds
Started May 12 02:58:23 PM PDT 24
Finished May 12 02:59:12 PM PDT 24
Peak memory 256188 kb
Host smart-fa1e7a70-e29f-426f-be03-ae4ae0a989c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21720
41561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2172041561
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2989735038
Short name T478
Test name
Test status
Simulation time 157984641 ps
CPU time 14.25 seconds
Started May 12 02:58:22 PM PDT 24
Finished May 12 02:58:37 PM PDT 24
Peak memory 252340 kb
Host smart-dbd5effd-ab2e-4709-8b75-d2afa7208ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
35038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2989735038
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3945421074
Short name T520
Test name
Test status
Simulation time 45843395 ps
CPU time 4.8 seconds
Started May 12 02:58:22 PM PDT 24
Finished May 12 02:58:28 PM PDT 24
Peak memory 239256 kb
Host smart-9e263956-dfb2-4ed7-a2f9-ce78feb3abea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
21074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3945421074
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.672395846
Short name T630
Test name
Test status
Simulation time 707662419 ps
CPU time 57.34 seconds
Started May 12 02:58:18 PM PDT 24
Finished May 12 02:59:16 PM PDT 24
Peak memory 256020 kb
Host smart-7d3521ef-a48b-410c-aae4-5a6f985bfea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67239
5846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.672395846
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.694174686
Short name T689
Test name
Test status
Simulation time 19544550507 ps
CPU time 306.22 seconds
Started May 12 02:58:25 PM PDT 24
Finished May 12 03:03:32 PM PDT 24
Peak memory 255564 kb
Host smart-578a9020-8778-4b8f-acb1-40b94c488e3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694174686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.694174686
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2535627707
Short name T397
Test name
Test status
Simulation time 12443596857 ps
CPU time 843.44 seconds
Started May 12 02:58:33 PM PDT 24
Finished May 12 03:12:37 PM PDT 24
Peak memory 266316 kb
Host smart-b0a25372-c875-41e8-aa9d-956213e99ce2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535627707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2535627707
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1479201964
Short name T480
Test name
Test status
Simulation time 3772040953 ps
CPU time 201.1 seconds
Started May 12 02:58:32 PM PDT 24
Finished May 12 03:01:54 PM PDT 24
Peak memory 249816 kb
Host smart-5d22df16-66a5-481d-9259-c3c3d4e88d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
01964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1479201964
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.286065118
Short name T439
Test name
Test status
Simulation time 117827994 ps
CPU time 8.79 seconds
Started May 12 02:58:29 PM PDT 24
Finished May 12 02:58:38 PM PDT 24
Peak memory 250912 kb
Host smart-f82f54f6-353e-4074-a4ff-1692aff52533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606
5118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.286065118
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2256039256
Short name T491
Test name
Test status
Simulation time 82788293543 ps
CPU time 2530.47 seconds
Started May 12 02:58:32 PM PDT 24
Finished May 12 03:40:43 PM PDT 24
Peak memory 289236 kb
Host smart-8b999224-c187-4d7e-a5c5-f011ecf5a331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256039256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2256039256
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2421840760
Short name T623
Test name
Test status
Simulation time 36712512743 ps
CPU time 372.34 seconds
Started May 12 02:58:34 PM PDT 24
Finished May 12 03:04:47 PM PDT 24
Peak memory 247072 kb
Host smart-be93dda2-cb71-436b-aa11-a438147267a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421840760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2421840760
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.54990470
Short name T67
Test name
Test status
Simulation time 723302036 ps
CPU time 23.46 seconds
Started May 12 02:58:30 PM PDT 24
Finished May 12 02:58:54 PM PDT 24
Peak memory 248704 kb
Host smart-d54cbc82-8aa3-4c60-acdc-36bf2a1ee0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54990
470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.54990470
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1863490858
Short name T63
Test name
Test status
Simulation time 530750493 ps
CPU time 34.88 seconds
Started May 12 02:58:29 PM PDT 24
Finished May 12 02:59:04 PM PDT 24
Peak memory 248760 kb
Host smart-add84561-54e6-4667-a2db-716e9bbd31eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
90858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1863490858
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4034199392
Short name T252
Test name
Test status
Simulation time 1555468155 ps
CPU time 25.33 seconds
Started May 12 02:58:34 PM PDT 24
Finished May 12 02:59:00 PM PDT 24
Peak memory 247428 kb
Host smart-eb4384b0-04c0-47b2-a6e4-32db20b2b032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40341
99392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4034199392
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.124136524
Short name T686
Test name
Test status
Simulation time 602546515 ps
CPU time 38.27 seconds
Started May 12 02:58:29 PM PDT 24
Finished May 12 02:59:08 PM PDT 24
Peak memory 255980 kb
Host smart-82b2f6b5-6722-4945-9048-74932de705a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
6524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.124136524
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2963174237
Short name T97
Test name
Test status
Simulation time 65545841477 ps
CPU time 2255.54 seconds
Started May 12 02:58:45 PM PDT 24
Finished May 12 03:36:21 PM PDT 24
Peak memory 268444 kb
Host smart-7cea7487-0088-4aaf-b801-73531287cf95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963174237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2963174237
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.24579129
Short name T387
Test name
Test status
Simulation time 821468311 ps
CPU time 30.08 seconds
Started May 12 02:58:41 PM PDT 24
Finished May 12 02:59:12 PM PDT 24
Peak memory 249036 kb
Host smart-a13af5d4-24c0-484f-8e36-dabafc80bf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.24579129
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3981707243
Short name T675
Test name
Test status
Simulation time 1313495592 ps
CPU time 49.61 seconds
Started May 12 02:58:39 PM PDT 24
Finished May 12 02:59:29 PM PDT 24
Peak memory 256112 kb
Host smart-b69ef519-52c6-408f-9c9b-f013eef44f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
07243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3981707243
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4006047601
Short name T316
Test name
Test status
Simulation time 12428100026 ps
CPU time 1258.04 seconds
Started May 12 02:58:48 PM PDT 24
Finished May 12 03:19:47 PM PDT 24
Peak memory 273412 kb
Host smart-61a2a0aa-8746-4408-b8a0-4c6404450d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006047601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4006047601
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2899078292
Short name T447
Test name
Test status
Simulation time 5401456925 ps
CPU time 744.01 seconds
Started May 12 02:58:50 PM PDT 24
Finished May 12 03:11:15 PM PDT 24
Peak memory 272068 kb
Host smart-143e0cdb-7d69-4997-9a46-db9d19aebc36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899078292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2899078292
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1137998969
Short name T383
Test name
Test status
Simulation time 516447845 ps
CPU time 28.1 seconds
Started May 12 02:58:42 PM PDT 24
Finished May 12 02:59:10 PM PDT 24
Peak memory 248772 kb
Host smart-b1da920b-987a-4776-b28d-2ea60927ce66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
98969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1137998969
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2116272781
Short name T40
Test name
Test status
Simulation time 223212247 ps
CPU time 19.32 seconds
Started May 12 02:58:39 PM PDT 24
Finished May 12 02:58:59 PM PDT 24
Peak memory 247452 kb
Host smart-c040bb04-5695-40e7-9dd0-6513cd4c2b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21162
72781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2116272781
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1967912043
Short name T367
Test name
Test status
Simulation time 27930074 ps
CPU time 2.96 seconds
Started May 12 02:58:39 PM PDT 24
Finished May 12 02:58:42 PM PDT 24
Peak memory 240568 kb
Host smart-af2afa8d-d99b-445e-8259-ea133b9027e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19679
12043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1967912043
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.630000201
Short name T256
Test name
Test status
Simulation time 126753867620 ps
CPU time 2092.53 seconds
Started May 12 02:58:49 PM PDT 24
Finished May 12 03:33:42 PM PDT 24
Peak memory 305948 kb
Host smart-a860d14f-50c9-4b8c-a40f-f8ba5d204504
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630000201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.630000201
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.786553184
Short name T276
Test name
Test status
Simulation time 36465485821 ps
CPU time 1047.35 seconds
Started May 12 02:58:52 PM PDT 24
Finished May 12 03:16:20 PM PDT 24
Peak memory 289372 kb
Host smart-cefb79e4-4e66-42d2-a3d6-d9ef8621f22c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786553184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.786553184
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1930739009
Short name T644
Test name
Test status
Simulation time 14376125912 ps
CPU time 256.72 seconds
Started May 12 02:58:50 PM PDT 24
Finished May 12 03:03:07 PM PDT 24
Peak memory 250896 kb
Host smart-307773de-665e-46ee-8fae-4fc87a8acfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307
39009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1930739009
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3148204137
Short name T369
Test name
Test status
Simulation time 393824033 ps
CPU time 33.5 seconds
Started May 12 02:58:51 PM PDT 24
Finished May 12 02:59:25 PM PDT 24
Peak memory 248860 kb
Host smart-61fee404-e17e-418d-a520-580e45aa4dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
04137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3148204137
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.837897505
Short name T310
Test name
Test status
Simulation time 19304547492 ps
CPU time 1285.28 seconds
Started May 12 02:58:51 PM PDT 24
Finished May 12 03:20:17 PM PDT 24
Peak memory 265204 kb
Host smart-46239c21-dad0-4628-8b18-9d760528680c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837897505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.837897505
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2757596357
Short name T379
Test name
Test status
Simulation time 119872205882 ps
CPU time 1886.38 seconds
Started May 12 02:58:53 PM PDT 24
Finished May 12 03:30:20 PM PDT 24
Peak memory 273400 kb
Host smart-5e39e372-cb41-4d28-b3ae-79c7957e784c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757596357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2757596357
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.830158133
Short name T233
Test name
Test status
Simulation time 23815091892 ps
CPU time 290.75 seconds
Started May 12 02:58:55 PM PDT 24
Finished May 12 03:03:46 PM PDT 24
Peak memory 254704 kb
Host smart-2fa56aaf-cee4-4ca0-b800-879cbea34b1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830158133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.830158133
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.178860275
Short name T82
Test name
Test status
Simulation time 149869280 ps
CPU time 12.27 seconds
Started May 12 02:58:52 PM PDT 24
Finished May 12 02:59:05 PM PDT 24
Peak memory 252940 kb
Host smart-5fe348df-18de-4559-a246-1e937a2d6449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
0275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.178860275
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4152095087
Short name T400
Test name
Test status
Simulation time 406276511 ps
CPU time 34.51 seconds
Started May 12 02:58:55 PM PDT 24
Finished May 12 02:59:30 PM PDT 24
Peak memory 255392 kb
Host smart-dd79632c-a882-4a13-9a3a-7abdc7009480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41520
95087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4152095087
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2640576426
Short name T240
Test name
Test status
Simulation time 5839708006 ps
CPU time 63.07 seconds
Started May 12 02:58:52 PM PDT 24
Finished May 12 02:59:56 PM PDT 24
Peak memory 256492 kb
Host smart-c2b1522c-cd5c-4264-8878-fc075c6bd536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
76426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2640576426
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3882085523
Short name T454
Test name
Test status
Simulation time 5110286896 ps
CPU time 73.55 seconds
Started May 12 02:58:50 PM PDT 24
Finished May 12 03:00:04 PM PDT 24
Peak memory 256052 kb
Host smart-8601db75-7a13-4f61-9f18-c437441e6720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
85523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3882085523
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2579322857
Short name T535
Test name
Test status
Simulation time 153415416039 ps
CPU time 4148.5 seconds
Started May 12 02:58:57 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 299564 kb
Host smart-3e62877c-3a2d-4c16-adc4-12e41dc3bef4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579322857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2579322857
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.368203807
Short name T54
Test name
Test status
Simulation time 315310645304 ps
CPU time 7970.42 seconds
Started May 12 02:58:59 PM PDT 24
Finished May 12 05:11:51 PM PDT 24
Peak memory 371176 kb
Host smart-b329247f-7d1e-44a4-b1c4-71ba71d09b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368203807 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.368203807
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2307985727
Short name T215
Test name
Test status
Simulation time 67652082 ps
CPU time 2.47 seconds
Started May 12 02:55:04 PM PDT 24
Finished May 12 02:55:07 PM PDT 24
Peak memory 248864 kb
Host smart-cf6cbba5-3ab5-4603-b53c-0b7a26827f9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2307985727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2307985727
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.201749478
Short name T687
Test name
Test status
Simulation time 9685075006 ps
CPU time 1299.87 seconds
Started May 12 02:55:02 PM PDT 24
Finished May 12 03:16:43 PM PDT 24
Peak memory 285736 kb
Host smart-639c2efc-c823-4bb4-81bb-36306b329fdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201749478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.201749478
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4021762758
Short name T633
Test name
Test status
Simulation time 715031712 ps
CPU time 24.92 seconds
Started May 12 02:55:02 PM PDT 24
Finished May 12 02:55:27 PM PDT 24
Peak memory 251448 kb
Host smart-a9ea250b-64a3-4a31-97b2-4182d4b5a240
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4021762758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4021762758
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1033003013
Short name T227
Test name
Test status
Simulation time 1313418442 ps
CPU time 114.4 seconds
Started May 12 02:55:02 PM PDT 24
Finished May 12 02:56:57 PM PDT 24
Peak memory 249852 kb
Host smart-1dbd8268-827c-4bad-9e27-35066f80a1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
03013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1033003013
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3332225292
Short name T603
Test name
Test status
Simulation time 3460794315 ps
CPU time 55.05 seconds
Started May 12 02:55:00 PM PDT 24
Finished May 12 02:55:56 PM PDT 24
Peak memory 256360 kb
Host smart-c2a0b326-e53c-4746-bcd7-95ec4729605a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
25292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3332225292
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2027676863
Short name T331
Test name
Test status
Simulation time 76445756478 ps
CPU time 2476.24 seconds
Started May 12 02:55:03 PM PDT 24
Finished May 12 03:36:20 PM PDT 24
Peak memory 282304 kb
Host smart-5cef9dd5-85a0-4a91-9dff-b7ded0e9b419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027676863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2027676863
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3808677977
Short name T377
Test name
Test status
Simulation time 45003485602 ps
CPU time 1059.92 seconds
Started May 12 02:55:03 PM PDT 24
Finished May 12 03:12:44 PM PDT 24
Peak memory 272436 kb
Host smart-708a477b-0e68-432b-9c3a-efca720630c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808677977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3808677977
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1034335286
Short name T601
Test name
Test status
Simulation time 12579819459 ps
CPU time 212.59 seconds
Started May 12 02:55:02 PM PDT 24
Finished May 12 02:58:35 PM PDT 24
Peak memory 254856 kb
Host smart-1bf830e3-68d9-48a6-8921-3580cef64a11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034335286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1034335286
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1353722140
Short name T555
Test name
Test status
Simulation time 117543806 ps
CPU time 8.11 seconds
Started May 12 02:55:01 PM PDT 24
Finished May 12 02:55:09 PM PDT 24
Peak memory 248708 kb
Host smart-a6e43cd8-77c5-46dd-8c9d-54aa8c237108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
22140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1353722140
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2506764445
Short name T523
Test name
Test status
Simulation time 3414516383 ps
CPU time 46.02 seconds
Started May 12 02:54:59 PM PDT 24
Finished May 12 02:55:46 PM PDT 24
Peak memory 255828 kb
Host smart-185731b4-ea57-466e-9446-877064759ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25067
64445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2506764445
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1284296401
Short name T11
Test name
Test status
Simulation time 569246658 ps
CPU time 14.26 seconds
Started May 12 02:55:08 PM PDT 24
Finished May 12 02:55:23 PM PDT 24
Peak memory 276564 kb
Host smart-a9a6dc6b-2393-4f9e-bd57-96fb8d11b0bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1284296401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1284296401
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2558023383
Short name T257
Test name
Test status
Simulation time 1737926537 ps
CPU time 68.06 seconds
Started May 12 02:55:04 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 256016 kb
Host smart-cbe33f93-d6ee-4b5c-9a54-42c33d465c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25580
23383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2558023383
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1493466260
Short name T225
Test name
Test status
Simulation time 845775496 ps
CPU time 10.88 seconds
Started May 12 02:54:58 PM PDT 24
Finished May 12 02:55:09 PM PDT 24
Peak memory 248720 kb
Host smart-c27d1f7d-dad3-48d0-ba77-216a053afcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
66260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1493466260
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.815101294
Short name T87
Test name
Test status
Simulation time 68404899462 ps
CPU time 4267.95 seconds
Started May 12 02:55:02 PM PDT 24
Finished May 12 04:06:11 PM PDT 24
Peak memory 301552 kb
Host smart-81e870d2-069f-44c7-a3c1-7984e40dfb29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815101294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.815101294
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2381940884
Short name T698
Test name
Test status
Simulation time 84310183466 ps
CPU time 1288.33 seconds
Started May 12 02:58:59 PM PDT 24
Finished May 12 03:20:28 PM PDT 24
Peak memory 273416 kb
Host smart-fe105c08-a338-4ff0-8fe6-5500f33eb597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381940884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2381940884
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2467735796
Short name T378
Test name
Test status
Simulation time 31550802672 ps
CPU time 189.54 seconds
Started May 12 02:59:00 PM PDT 24
Finished May 12 03:02:10 PM PDT 24
Peak memory 250428 kb
Host smart-25ea9cf0-dfcf-496a-89b5-d4446d74e0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
35796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2467735796
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4167706662
Short name T482
Test name
Test status
Simulation time 205182448 ps
CPU time 16.39 seconds
Started May 12 02:59:03 PM PDT 24
Finished May 12 02:59:20 PM PDT 24
Peak memory 249232 kb
Host smart-38aab24a-55aa-4da4-8081-c0a0ad774f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41677
06662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4167706662
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2707893516
Short name T411
Test name
Test status
Simulation time 9375153008 ps
CPU time 725.21 seconds
Started May 12 02:59:02 PM PDT 24
Finished May 12 03:11:08 PM PDT 24
Peak memory 273040 kb
Host smart-08f7845f-da64-4329-8539-6527a8492b11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707893516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2707893516
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3203960385
Short name T685
Test name
Test status
Simulation time 16828728499 ps
CPU time 526.22 seconds
Started May 12 02:59:04 PM PDT 24
Finished May 12 03:07:51 PM PDT 24
Peak memory 248284 kb
Host smart-10f234ec-d332-4670-8462-bda127ce0df1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203960385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3203960385
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3099105171
Short name T548
Test name
Test status
Simulation time 5714445175 ps
CPU time 47.38 seconds
Started May 12 02:58:57 PM PDT 24
Finished May 12 02:59:45 PM PDT 24
Peak memory 256104 kb
Host smart-d77086c7-4035-403d-a667-e8935f3aa1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30991
05171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3099105171
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2445517937
Short name T543
Test name
Test status
Simulation time 729841084 ps
CPU time 23.46 seconds
Started May 12 02:58:59 PM PDT 24
Finished May 12 02:59:23 PM PDT 24
Peak memory 248708 kb
Host smart-57463a41-59aa-457a-a28f-b441f0bf36b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
17937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2445517937
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3387173544
Short name T596
Test name
Test status
Simulation time 61714315 ps
CPU time 5.52 seconds
Started May 12 02:59:05 PM PDT 24
Finished May 12 02:59:11 PM PDT 24
Peak memory 239252 kb
Host smart-e6165268-90fd-4068-b5a1-41fc65eea814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33871
73544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3387173544
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.956380700
Short name T639
Test name
Test status
Simulation time 529634014 ps
CPU time 23.19 seconds
Started May 12 02:58:58 PM PDT 24
Finished May 12 02:59:22 PM PDT 24
Peak memory 248728 kb
Host smart-2c47c013-80b0-45f1-8a68-3c71f500abcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95638
0700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.956380700
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2313223640
Short name T484
Test name
Test status
Simulation time 9365245596 ps
CPU time 1444.61 seconds
Started May 12 02:59:09 PM PDT 24
Finished May 12 03:23:15 PM PDT 24
Peak memory 281580 kb
Host smart-ac2d4404-2300-4cee-99a1-c0a6d46e1a1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313223640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2313223640
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.798340098
Short name T435
Test name
Test status
Simulation time 1110017757 ps
CPU time 45.53 seconds
Started May 12 02:59:07 PM PDT 24
Finished May 12 02:59:53 PM PDT 24
Peak memory 248788 kb
Host smart-c5200142-a920-4bde-a355-958a18af403e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79834
0098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.798340098
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2182690999
Short name T118
Test name
Test status
Simulation time 7792061431 ps
CPU time 47.5 seconds
Started May 12 02:59:07 PM PDT 24
Finished May 12 02:59:54 PM PDT 24
Peak memory 248840 kb
Host smart-0fd1c7e7-4f52-42ab-9b3c-493b1b126498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21826
90999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2182690999
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1208366305
Short name T322
Test name
Test status
Simulation time 681068573289 ps
CPU time 3194.67 seconds
Started May 12 02:59:13 PM PDT 24
Finished May 12 03:52:29 PM PDT 24
Peak memory 284396 kb
Host smart-cf2de49c-fceb-48dc-872c-71758172b820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208366305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1208366305
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1631120643
Short name T275
Test name
Test status
Simulation time 144479380500 ps
CPU time 2026.07 seconds
Started May 12 02:59:15 PM PDT 24
Finished May 12 03:33:02 PM PDT 24
Peak memory 281972 kb
Host smart-b4d312be-8cb2-4ff7-91db-292b573797b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631120643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1631120643
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3936466315
Short name T1
Test name
Test status
Simulation time 7717235732 ps
CPU time 294.24 seconds
Started May 12 02:59:09 PM PDT 24
Finished May 12 03:04:04 PM PDT 24
Peak memory 254548 kb
Host smart-12f374a0-1760-4a50-b574-d1c1b389792c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936466315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3936466315
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1136471438
Short name T416
Test name
Test status
Simulation time 5427352342 ps
CPU time 52.78 seconds
Started May 12 02:59:10 PM PDT 24
Finished May 12 03:00:03 PM PDT 24
Peak memory 256088 kb
Host smart-fc290a5d-648f-40b7-981d-0495bbbd933a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364
71438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1136471438
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3142912683
Short name T389
Test name
Test status
Simulation time 1752486172 ps
CPU time 60.23 seconds
Started May 12 02:59:07 PM PDT 24
Finished May 12 03:00:08 PM PDT 24
Peak memory 248772 kb
Host smart-beb2046a-08cf-4f1e-8a01-b6676680628d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
12683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3142912683
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.168211569
Short name T284
Test name
Test status
Simulation time 2515185556 ps
CPU time 44.86 seconds
Started May 12 02:59:11 PM PDT 24
Finished May 12 02:59:57 PM PDT 24
Peak memory 249076 kb
Host smart-4e40a58a-ee39-4d01-9766-807d2b24070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
1569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.168211569
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1303404826
Short name T422
Test name
Test status
Simulation time 342409517 ps
CPU time 39.42 seconds
Started May 12 02:59:10 PM PDT 24
Finished May 12 02:59:50 PM PDT 24
Peak memory 248720 kb
Host smart-930fa04b-cb44-4575-b4d0-8899d641b89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13034
04826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1303404826
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2739359244
Short name T349
Test name
Test status
Simulation time 235180777598 ps
CPU time 1610.04 seconds
Started May 12 02:59:14 PM PDT 24
Finished May 12 03:26:05 PM PDT 24
Peak memory 272756 kb
Host smart-9f3d4154-3817-4501-9847-1c25dd7b2e4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739359244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2739359244
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.335057609
Short name T116
Test name
Test status
Simulation time 29731710859 ps
CPU time 1758.25 seconds
Started May 12 02:59:20 PM PDT 24
Finished May 12 03:28:39 PM PDT 24
Peak memory 273420 kb
Host smart-f922a97d-ab1e-42e0-a9a4-24d05aec214b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335057609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.335057609
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.276006736
Short name T188
Test name
Test status
Simulation time 3232976778 ps
CPU time 76.15 seconds
Started May 12 02:59:19 PM PDT 24
Finished May 12 03:00:35 PM PDT 24
Peak memory 256836 kb
Host smart-061f15c8-f98a-420f-ac9d-ddde75f1f7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
6736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.276006736
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.706380335
Short name T460
Test name
Test status
Simulation time 1014027180 ps
CPU time 48.57 seconds
Started May 12 02:59:17 PM PDT 24
Finished May 12 03:00:06 PM PDT 24
Peak memory 248808 kb
Host smart-4842400e-cd5e-4a74-ab6f-43ad792800e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70638
0335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.706380335
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.843345392
Short name T327
Test name
Test status
Simulation time 33506195114 ps
CPU time 1916.09 seconds
Started May 12 02:59:25 PM PDT 24
Finished May 12 03:31:21 PM PDT 24
Peak memory 273380 kb
Host smart-b71a05d1-cf4a-48f2-a6cd-4bd960b0cd9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843345392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.843345392
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.149304365
Short name T519
Test name
Test status
Simulation time 31789403887 ps
CPU time 2059.61 seconds
Started May 12 02:59:25 PM PDT 24
Finished May 12 03:33:45 PM PDT 24
Peak memory 285208 kb
Host smart-f419e542-b949-4a55-9c92-9c6c119df22d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149304365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.149304365
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1539807915
Short name T61
Test name
Test status
Simulation time 20132078574 ps
CPU time 200.02 seconds
Started May 12 02:59:21 PM PDT 24
Finished May 12 03:02:41 PM PDT 24
Peak memory 248316 kb
Host smart-6d26d2df-421b-4cc4-912d-854d43dc1399
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539807915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1539807915
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3078557651
Short name T26
Test name
Test status
Simulation time 1307506314 ps
CPU time 29.41 seconds
Started May 12 02:59:14 PM PDT 24
Finished May 12 02:59:43 PM PDT 24
Peak memory 248768 kb
Host smart-a3378d27-4a43-40a8-9134-7cb84d9a1a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
57651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3078557651
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.121936624
Short name T479
Test name
Test status
Simulation time 964477308 ps
CPU time 11.14 seconds
Started May 12 02:59:13 PM PDT 24
Finished May 12 02:59:25 PM PDT 24
Peak memory 247412 kb
Host smart-f9b9e73f-ee2c-4f71-b09e-f9ba47278ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193
6624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.121936624
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3756544951
Short name T600
Test name
Test status
Simulation time 1704336727 ps
CPU time 55.77 seconds
Started May 12 02:59:21 PM PDT 24
Finished May 12 03:00:17 PM PDT 24
Peak memory 256760 kb
Host smart-bce6d30c-939d-4a7d-b4a2-75d0e4cf3ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
44951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3756544951
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.434345529
Short name T446
Test name
Test status
Simulation time 657841806 ps
CPU time 28.84 seconds
Started May 12 02:59:13 PM PDT 24
Finished May 12 02:59:43 PM PDT 24
Peak memory 248760 kb
Host smart-d938df3a-d322-4c5f-92a7-64663bb03aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43434
5529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.434345529
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2459774143
Short name T412
Test name
Test status
Simulation time 21670269438 ps
CPU time 623.13 seconds
Started May 12 02:59:25 PM PDT 24
Finished May 12 03:09:49 PM PDT 24
Peak memory 256612 kb
Host smart-b33fa3ae-7559-4055-9205-6468848c7ce7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459774143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2459774143
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1522651274
Short name T514
Test name
Test status
Simulation time 63168152422 ps
CPU time 2324.09 seconds
Started May 12 02:59:39 PM PDT 24
Finished May 12 03:38:24 PM PDT 24
Peak memory 281580 kb
Host smart-58fc36f0-a829-4bd5-99c9-9b4599d98076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522651274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1522651274
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2226222561
Short name T232
Test name
Test status
Simulation time 848376365 ps
CPU time 47.11 seconds
Started May 12 02:59:30 PM PDT 24
Finished May 12 03:00:18 PM PDT 24
Peak memory 255920 kb
Host smart-70bb0896-10b1-409f-81e4-1a00e3b38c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22262
22561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2226222561
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3642622122
Short name T3
Test name
Test status
Simulation time 1042915720 ps
CPU time 16.65 seconds
Started May 12 02:59:28 PM PDT 24
Finished May 12 02:59:45 PM PDT 24
Peak memory 253028 kb
Host smart-1da13cd7-4d0f-4b4c-bf7d-fdf3b416c51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
22122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3642622122
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.688951177
Short name T13
Test name
Test status
Simulation time 82127672229 ps
CPU time 1831.5 seconds
Started May 12 02:59:37 PM PDT 24
Finished May 12 03:30:09 PM PDT 24
Peak memory 289168 kb
Host smart-bd90c475-9686-44f0-8baf-b4798161fb7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688951177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.688951177
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1863356456
Short name T574
Test name
Test status
Simulation time 43739327639 ps
CPU time 1520.83 seconds
Started May 12 02:59:38 PM PDT 24
Finished May 12 03:24:59 PM PDT 24
Peak memory 272440 kb
Host smart-dca87348-3d1e-4c51-b86f-9da23411c314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863356456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1863356456
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2664605169
Short name T311
Test name
Test status
Simulation time 6747820838 ps
CPU time 273.82 seconds
Started May 12 02:59:37 PM PDT 24
Finished May 12 03:04:12 PM PDT 24
Peak memory 248160 kb
Host smart-5db7668d-29f6-4b4c-9f81-02fbc19f01a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664605169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2664605169
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3536694915
Short name T41
Test name
Test status
Simulation time 501831137 ps
CPU time 22.51 seconds
Started May 12 02:59:28 PM PDT 24
Finished May 12 02:59:51 PM PDT 24
Peak memory 256036 kb
Host smart-9a08af5a-ad0a-4bb8-a582-3fa0270090ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
94915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3536694915
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.285808979
Short name T621
Test name
Test status
Simulation time 182443998 ps
CPU time 8.67 seconds
Started May 12 02:59:28 PM PDT 24
Finished May 12 02:59:37 PM PDT 24
Peak memory 247448 kb
Host smart-de11885f-2177-4f3b-9079-90f965ca6137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
8979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.285808979
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.780680046
Short name T269
Test name
Test status
Simulation time 4050708975 ps
CPU time 68.7 seconds
Started May 12 02:59:40 PM PDT 24
Finished May 12 03:00:49 PM PDT 24
Peak memory 256308 kb
Host smart-26e9d55a-196d-4236-80fd-3663f79e4086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78068
0046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.780680046
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1130670046
Short name T381
Test name
Test status
Simulation time 191673263 ps
CPU time 6.93 seconds
Started May 12 02:59:27 PM PDT 24
Finished May 12 02:59:34 PM PDT 24
Peak memory 248776 kb
Host smart-84f62a52-4499-4f7b-85d1-50e871c4a7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306
70046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1130670046
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.921222996
Short name T226
Test name
Test status
Simulation time 45345716316 ps
CPU time 2877.4 seconds
Started May 12 02:59:38 PM PDT 24
Finished May 12 03:47:36 PM PDT 24
Peak memory 289312 kb
Host smart-a69421d7-b82e-4ab5-bd00-0d95bd5f971a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921222996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.921222996
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1460555749
Short name T504
Test name
Test status
Simulation time 52922406569 ps
CPU time 2131.21 seconds
Started May 12 02:59:40 PM PDT 24
Finished May 12 03:35:12 PM PDT 24
Peak memory 282196 kb
Host smart-8c46d6e6-c562-45a4-9148-782f47ac2e0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460555749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1460555749
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1928886207
Short name T371
Test name
Test status
Simulation time 5817674602 ps
CPU time 76.03 seconds
Started May 12 02:59:43 PM PDT 24
Finished May 12 03:00:59 PM PDT 24
Peak memory 256900 kb
Host smart-43195622-973d-498e-940e-db3d2a75037f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
86207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1928886207
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.673651958
Short name T501
Test name
Test status
Simulation time 122494257 ps
CPU time 9.8 seconds
Started May 12 02:59:40 PM PDT 24
Finished May 12 02:59:51 PM PDT 24
Peak memory 248696 kb
Host smart-22681c17-e25c-4493-b576-e20f010b46c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67365
1958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.673651958
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.130539861
Short name T320
Test name
Test status
Simulation time 82100910910 ps
CPU time 2807.67 seconds
Started May 12 02:59:43 PM PDT 24
Finished May 12 03:46:31 PM PDT 24
Peak memory 286728 kb
Host smart-9c88d255-3698-405e-a476-134076dfd0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130539861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.130539861
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1262723885
Short name T427
Test name
Test status
Simulation time 61612401827 ps
CPU time 1984.59 seconds
Started May 12 02:59:44 PM PDT 24
Finished May 12 03:32:49 PM PDT 24
Peak memory 289352 kb
Host smart-f6211e5b-86c6-45a6-a529-12441afd1e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262723885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1262723885
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2464358145
Short name T690
Test name
Test status
Simulation time 6667462678 ps
CPU time 154.48 seconds
Started May 12 02:59:42 PM PDT 24
Finished May 12 03:02:17 PM PDT 24
Peak memory 248236 kb
Host smart-60eb83ab-a12d-48fc-bf11-d1e16b66546d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464358145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2464358145
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3990089305
Short name T346
Test name
Test status
Simulation time 47253010 ps
CPU time 5.16 seconds
Started May 12 02:59:39 PM PDT 24
Finished May 12 02:59:44 PM PDT 24
Peak memory 240544 kb
Host smart-c0e02a5b-12a2-446b-b43b-5ecb3c74dbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
89305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3990089305
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2952671127
Short name T418
Test name
Test status
Simulation time 1127561079 ps
CPU time 72.97 seconds
Started May 12 02:59:41 PM PDT 24
Finished May 12 03:00:54 PM PDT 24
Peak memory 254856 kb
Host smart-e92cb9bd-5b09-44da-9718-2f6e4f2477b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29526
71127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2952671127
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3938051835
Short name T508
Test name
Test status
Simulation time 304781578 ps
CPU time 43.6 seconds
Started May 12 02:59:41 PM PDT 24
Finished May 12 03:00:25 PM PDT 24
Peak memory 248180 kb
Host smart-9a729eb8-db4c-4793-aa57-5b5bcc2e104d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
51835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3938051835
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3557940598
Short name T593
Test name
Test status
Simulation time 502382900 ps
CPU time 36.54 seconds
Started May 12 02:59:40 PM PDT 24
Finished May 12 03:00:17 PM PDT 24
Peak memory 248708 kb
Host smart-26ed3270-bdff-4da0-9866-07acfa425ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35579
40598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3557940598
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2747616763
Short name T505
Test name
Test status
Simulation time 43051618241 ps
CPU time 2341.5 seconds
Started May 12 02:59:43 PM PDT 24
Finished May 12 03:38:46 PM PDT 24
Peak memory 284352 kb
Host smart-38796d46-50c4-4ae4-a5bf-6f2e08329741
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747616763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2747616763
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1353624876
Short name T55
Test name
Test status
Simulation time 56312365818 ps
CPU time 6607.36 seconds
Started May 12 02:59:43 PM PDT 24
Finished May 12 04:49:52 PM PDT 24
Peak memory 355452 kb
Host smart-663d778a-72b9-4db7-892e-3138109966e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353624876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1353624876
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1433114112
Short name T406
Test name
Test status
Simulation time 52325957065 ps
CPU time 3517.23 seconds
Started May 12 02:59:53 PM PDT 24
Finished May 12 03:58:32 PM PDT 24
Peak memory 288796 kb
Host smart-6f9475d5-fe43-4942-8cca-56abf7f205b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433114112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1433114112
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1497927105
Short name T665
Test name
Test status
Simulation time 2786329039 ps
CPU time 178.29 seconds
Started May 12 02:59:50 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 250284 kb
Host smart-4743f685-e7c4-42be-84fb-5c4d52415abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14979
27105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1497927105
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1679970928
Short name T452
Test name
Test status
Simulation time 64928431 ps
CPU time 4.31 seconds
Started May 12 02:59:50 PM PDT 24
Finished May 12 02:59:54 PM PDT 24
Peak memory 240564 kb
Host smart-ee81bfa8-962f-4041-9544-938f47486500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
70928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1679970928
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1619380163
Short name T610
Test name
Test status
Simulation time 150001692549 ps
CPU time 2556.66 seconds
Started May 12 02:59:53 PM PDT 24
Finished May 12 03:42:30 PM PDT 24
Peak memory 284548 kb
Host smart-e54b22e3-ec6b-4b95-afaf-3ebac59916bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619380163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1619380163
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1837119629
Short name T542
Test name
Test status
Simulation time 5317999246 ps
CPU time 206.53 seconds
Started May 12 02:59:53 PM PDT 24
Finished May 12 03:03:20 PM PDT 24
Peak memory 248084 kb
Host smart-b0381ff8-25f5-4da9-86a9-cf6a29b8f122
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837119629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1837119629
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3524364161
Short name T230
Test name
Test status
Simulation time 1241330125 ps
CPU time 26.81 seconds
Started May 12 02:59:47 PM PDT 24
Finished May 12 03:00:14 PM PDT 24
Peak memory 248872 kb
Host smart-900ee38d-5f43-4403-b56c-c6b17b764a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35243
64161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3524364161
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.977699689
Short name T52
Test name
Test status
Simulation time 355651423 ps
CPU time 24.05 seconds
Started May 12 02:59:45 PM PDT 24
Finished May 12 03:00:10 PM PDT 24
Peak memory 249164 kb
Host smart-13d15551-c229-41c3-91fd-76a7a43922c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97769
9689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.977699689
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3469773399
Short name T559
Test name
Test status
Simulation time 437215070 ps
CPU time 9.57 seconds
Started May 12 02:59:53 PM PDT 24
Finished May 12 03:00:03 PM PDT 24
Peak memory 254912 kb
Host smart-7c4677fe-9360-4b98-a174-68e10a180093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34697
73399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3469773399
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4133289782
Short name T500
Test name
Test status
Simulation time 406413157 ps
CPU time 33.05 seconds
Started May 12 02:59:46 PM PDT 24
Finished May 12 03:00:19 PM PDT 24
Peak memory 248756 kb
Host smart-d6d352e0-0c10-4fb1-a656-169c97c42f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332
89782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4133289782
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2646783109
Short name T472
Test name
Test status
Simulation time 1145398317 ps
CPU time 68.73 seconds
Started May 12 02:59:53 PM PDT 24
Finished May 12 03:01:02 PM PDT 24
Peak memory 256324 kb
Host smart-21b90aca-d940-467e-b58d-85a24a6917cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646783109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2646783109
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3098502837
Short name T564
Test name
Test status
Simulation time 438548369071 ps
CPU time 5363.93 seconds
Started May 12 02:59:56 PM PDT 24
Finished May 12 04:29:21 PM PDT 24
Peak memory 355080 kb
Host smart-c62d12be-eb8c-433e-b25d-80754b3f387d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098502837 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3098502837
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2404798525
Short name T382
Test name
Test status
Simulation time 36404938949 ps
CPU time 1786.88 seconds
Started May 12 03:00:04 PM PDT 24
Finished May 12 03:29:52 PM PDT 24
Peak memory 289388 kb
Host smart-361d1265-ff6f-4176-92a4-6ea05e9fd973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404798525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2404798525
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1121555861
Short name T388
Test name
Test status
Simulation time 5091713607 ps
CPU time 176.37 seconds
Started May 12 03:00:06 PM PDT 24
Finished May 12 03:03:02 PM PDT 24
Peak memory 256928 kb
Host smart-1c7ba738-4f8b-4099-b207-b908e42dd208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
55861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1121555861
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4112903157
Short name T537
Test name
Test status
Simulation time 1773516913 ps
CPU time 56.94 seconds
Started May 12 03:00:00 PM PDT 24
Finished May 12 03:00:58 PM PDT 24
Peak memory 256916 kb
Host smart-a41a7dbc-d392-44b6-b009-0f42e9e80ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41129
03157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4112903157
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.499312465
Short name T321
Test name
Test status
Simulation time 6588756232 ps
CPU time 741.21 seconds
Started May 12 03:00:05 PM PDT 24
Finished May 12 03:12:26 PM PDT 24
Peak memory 272828 kb
Host smart-cc42215c-1457-4b66-9de4-c07c683343e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499312465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.499312465
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.396196456
Short name T399
Test name
Test status
Simulation time 16977501864 ps
CPU time 1814.15 seconds
Started May 12 03:00:06 PM PDT 24
Finished May 12 03:30:21 PM PDT 24
Peak memory 289648 kb
Host smart-42cb9cad-90a9-445a-a810-515d16008873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396196456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.396196456
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2852664557
Short name T591
Test name
Test status
Simulation time 1994958351 ps
CPU time 83.76 seconds
Started May 12 03:00:03 PM PDT 24
Finished May 12 03:01:27 PM PDT 24
Peak memory 248028 kb
Host smart-54ecb2e8-cc3d-4166-86c3-1c695a7ee404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852664557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2852664557
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1005022602
Short name T554
Test name
Test status
Simulation time 4199448088 ps
CPU time 55.7 seconds
Started May 12 03:00:00 PM PDT 24
Finished May 12 03:00:56 PM PDT 24
Peak memory 248820 kb
Host smart-7a1307b4-51d0-41ed-b2e1-2a13b24025b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10050
22602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1005022602
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4237084084
Short name T485
Test name
Test status
Simulation time 375472564 ps
CPU time 6 seconds
Started May 12 03:00:00 PM PDT 24
Finished May 12 03:00:06 PM PDT 24
Peak memory 239092 kb
Host smart-82155355-5189-498c-988c-2184e8e7ada4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42370
84084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4237084084
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2951772012
Short name T119
Test name
Test status
Simulation time 204196633 ps
CPU time 18.11 seconds
Started May 12 03:00:05 PM PDT 24
Finished May 12 03:00:23 PM PDT 24
Peak memory 255560 kb
Host smart-24f9e931-7e2c-4c95-8196-99e00339a014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29517
72012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2951772012
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.823741076
Short name T459
Test name
Test status
Simulation time 271067699 ps
CPU time 16.85 seconds
Started May 12 02:59:57 PM PDT 24
Finished May 12 03:00:15 PM PDT 24
Peak memory 248708 kb
Host smart-01d9962e-1de5-4eaf-bbb6-e617e94f7606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82374
1076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.823741076
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1803843870
Short name T263
Test name
Test status
Simulation time 2037818311 ps
CPU time 86.62 seconds
Started May 12 03:00:10 PM PDT 24
Finished May 12 03:01:37 PM PDT 24
Peak memory 250256 kb
Host smart-85f854b2-0864-4502-9227-f5c40ecf5cb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803843870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1803843870
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2389624731
Short name T190
Test name
Test status
Simulation time 64576948273 ps
CPU time 4826.36 seconds
Started May 12 03:00:11 PM PDT 24
Finished May 12 04:20:38 PM PDT 24
Peak memory 321916 kb
Host smart-a4ec2371-15db-491e-8bfe-a66706af1866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389624731 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2389624731
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2759081898
Short name T699
Test name
Test status
Simulation time 57790449297 ps
CPU time 1426.8 seconds
Started May 12 03:00:18 PM PDT 24
Finished May 12 03:24:06 PM PDT 24
Peak memory 285240 kb
Host smart-7e97530c-ee87-4af6-ab94-69231edfaa0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759081898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2759081898
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3695871866
Short name T688
Test name
Test status
Simulation time 1635556503 ps
CPU time 55.03 seconds
Started May 12 03:00:14 PM PDT 24
Finished May 12 03:01:09 PM PDT 24
Peak memory 254844 kb
Host smart-7ad94ca8-6cbb-421f-a21f-64bb7efe36fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
71866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3695871866
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2717280278
Short name T522
Test name
Test status
Simulation time 5539655000 ps
CPU time 45.54 seconds
Started May 12 03:00:16 PM PDT 24
Finished May 12 03:01:02 PM PDT 24
Peak memory 256044 kb
Host smart-fefe7856-a02d-472c-bbfd-974920e77308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27172
80278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2717280278
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3211302
Short name T655
Test name
Test status
Simulation time 95181454335 ps
CPU time 1765.81 seconds
Started May 12 03:00:17 PM PDT 24
Finished May 12 03:29:43 PM PDT 24
Peak memory 269292 kb
Host smart-cdc93756-eee2-4373-9a4f-2c6314f6ac53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3211302
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.497656572
Short name T88
Test name
Test status
Simulation time 52958533662 ps
CPU time 2225.93 seconds
Started May 12 03:00:21 PM PDT 24
Finished May 12 03:37:28 PM PDT 24
Peak memory 285012 kb
Host smart-91dd2c4f-d1df-4411-b784-b0551a61f0c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497656572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.497656572
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2298202967
Short name T444
Test name
Test status
Simulation time 531623839 ps
CPU time 10.82 seconds
Started May 12 03:00:12 PM PDT 24
Finished May 12 03:00:23 PM PDT 24
Peak memory 248760 kb
Host smart-a10fd584-98f2-4642-b562-8a81b2c8563b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22982
02967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2298202967
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.831737440
Short name T25
Test name
Test status
Simulation time 450717903 ps
CPU time 28.97 seconds
Started May 12 03:00:14 PM PDT 24
Finished May 12 03:00:44 PM PDT 24
Peak memory 253900 kb
Host smart-b5df113a-4945-48ce-afb5-f98cc77de17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83173
7440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.831737440
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2116124858
Short name T471
Test name
Test status
Simulation time 649065300 ps
CPU time 17.75 seconds
Started May 12 03:00:15 PM PDT 24
Finished May 12 03:00:33 PM PDT 24
Peak memory 247576 kb
Host smart-e7e2802d-3f85-46ad-b46a-8f7ea8186e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21161
24858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2116124858
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2485862803
Short name T474
Test name
Test status
Simulation time 990045259 ps
CPU time 62.83 seconds
Started May 12 03:00:14 PM PDT 24
Finished May 12 03:01:18 PM PDT 24
Peak memory 256388 kb
Host smart-618cdda6-f73b-4e4e-b8ab-62079f472c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24858
62803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2485862803
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3152730298
Short name T50
Test name
Test status
Simulation time 78979411228 ps
CPU time 2196.62 seconds
Started May 12 03:00:21 PM PDT 24
Finished May 12 03:36:58 PM PDT 24
Peak memory 289372 kb
Host smart-bffd26a4-c2da-42ce-8283-3eca3c36dcb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152730298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3152730298
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1611386804
Short name T98
Test name
Test status
Simulation time 87298211950 ps
CPU time 4409.73 seconds
Started May 12 03:00:23 PM PDT 24
Finished May 12 04:13:54 PM PDT 24
Peak memory 335004 kb
Host smart-b1f70ebd-fbbe-4d41-99e2-abbaf2d6b084
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611386804 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1611386804
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2127012677
Short name T283
Test name
Test status
Simulation time 31934688360 ps
CPU time 2523.52 seconds
Started May 12 03:00:28 PM PDT 24
Finished May 12 03:42:32 PM PDT 24
Peak memory 281604 kb
Host smart-ba6032c3-2148-4d11-912d-a94941c10ae0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127012677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2127012677
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.44346818
Short name T16
Test name
Test status
Simulation time 2244668615 ps
CPU time 142.82 seconds
Started May 12 03:00:24 PM PDT 24
Finished May 12 03:02:48 PM PDT 24
Peak memory 256956 kb
Host smart-dcdd1230-9816-430b-b196-9dfa60426648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44346
818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.44346818
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.4222434276
Short name T620
Test name
Test status
Simulation time 571835069 ps
CPU time 17.88 seconds
Started May 12 03:00:25 PM PDT 24
Finished May 12 03:00:43 PM PDT 24
Peak memory 254804 kb
Host smart-2707f97a-063f-4b42-b58a-50d4930905dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
34276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4222434276
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2481653131
Short name T289
Test name
Test status
Simulation time 36967659024 ps
CPU time 2792.11 seconds
Started May 12 03:00:32 PM PDT 24
Finished May 12 03:47:05 PM PDT 24
Peak memory 288108 kb
Host smart-d71392e6-891c-4624-af12-3e8286bb9761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481653131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2481653131
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2515165565
Short name T524
Test name
Test status
Simulation time 62108859944 ps
CPU time 2100.01 seconds
Started May 12 03:00:31 PM PDT 24
Finished May 12 03:35:31 PM PDT 24
Peak memory 289124 kb
Host smart-d3187012-c179-47b6-ab05-8b2fd326b575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515165565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2515165565
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3508895300
Short name T296
Test name
Test status
Simulation time 12740487668 ps
CPU time 559.05 seconds
Started May 12 03:00:28 PM PDT 24
Finished May 12 03:09:47 PM PDT 24
Peak memory 248236 kb
Host smart-a685441a-92a5-4b69-bb63-ef72b2bc5211
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508895300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3508895300
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2724768098
Short name T445
Test name
Test status
Simulation time 76482319 ps
CPU time 9.34 seconds
Started May 12 03:00:24 PM PDT 24
Finished May 12 03:00:34 PM PDT 24
Peak memory 248776 kb
Host smart-f609febb-2b0b-44f2-82ed-bedc3df1022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
68098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2724768098
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3413040914
Short name T668
Test name
Test status
Simulation time 162646051 ps
CPU time 10.84 seconds
Started May 12 03:00:24 PM PDT 24
Finished May 12 03:00:36 PM PDT 24
Peak memory 247444 kb
Host smart-29ada642-bedb-44f3-a3c0-14df0a1ca79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130
40914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3413040914
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2325900300
Short name T586
Test name
Test status
Simulation time 277289393 ps
CPU time 34.85 seconds
Started May 12 03:00:24 PM PDT 24
Finished May 12 03:01:00 PM PDT 24
Peak memory 248716 kb
Host smart-a4e11aab-d0b7-4ed0-8d0d-a57413c4bd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23259
00300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2325900300
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3680263763
Short name T424
Test name
Test status
Simulation time 3677564880 ps
CPU time 31.89 seconds
Started May 12 03:00:25 PM PDT 24
Finished May 12 03:00:57 PM PDT 24
Peak memory 256244 kb
Host smart-4ffb107f-70cd-4d43-ba26-f76cc5217df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36802
63763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3680263763
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.144942740
Short name T432
Test name
Test status
Simulation time 868708709 ps
CPU time 52.98 seconds
Started May 12 03:00:31 PM PDT 24
Finished May 12 03:01:25 PM PDT 24
Peak memory 256916 kb
Host smart-4f121ebe-feca-4c1e-92d2-4e7c9fbcf299
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144942740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.144942740
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2874272589
Short name T96
Test name
Test status
Simulation time 194544436181 ps
CPU time 6858.6 seconds
Started May 12 03:00:35 PM PDT 24
Finished May 12 04:54:54 PM PDT 24
Peak memory 338468 kb
Host smart-d3f1a01f-9928-442c-b3eb-49a9ddeef483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874272589 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2874272589
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1721158785
Short name T8
Test name
Test status
Simulation time 140978912754 ps
CPU time 1836.41 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 03:31:16 PM PDT 24
Peak memory 273384 kb
Host smart-f1776cfb-3895-4e23-bbcf-2f7dd32757e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721158785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1721158785
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2701317554
Short name T405
Test name
Test status
Simulation time 3365419571 ps
CPU time 177.29 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 03:03:36 PM PDT 24
Peak memory 250888 kb
Host smart-d0fd2d89-c0d9-47b8-bb9e-f8d92632d614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27013
17554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2701317554
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4189349909
Short name T493
Test name
Test status
Simulation time 920904987 ps
CPU time 8.52 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 03:00:48 PM PDT 24
Peak memory 252768 kb
Host smart-010a2c77-06b7-4dd2-847e-4288e2bffdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
49909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4189349909
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.985181424
Short name T287
Test name
Test status
Simulation time 11530149413 ps
CPU time 1064.55 seconds
Started May 12 03:00:38 PM PDT 24
Finished May 12 03:18:23 PM PDT 24
Peak memory 271600 kb
Host smart-843eb886-817a-4d4d-b245-503ef30f88a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985181424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.985181424
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1816405842
Short name T42
Test name
Test status
Simulation time 351611537356 ps
CPU time 1920.62 seconds
Started May 12 03:00:38 PM PDT 24
Finished May 12 03:32:40 PM PDT 24
Peak memory 266228 kb
Host smart-e31b00e7-3056-4038-b8bc-966947578f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816405842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1816405842
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3636962232
Short name T308
Test name
Test status
Simulation time 45617719205 ps
CPU time 468.36 seconds
Started May 12 03:00:40 PM PDT 24
Finished May 12 03:08:29 PM PDT 24
Peak memory 248032 kb
Host smart-0ae3d68a-3147-4be9-a260-54862be8b91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636962232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3636962232
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3746965768
Short name T83
Test name
Test status
Simulation time 4227747655 ps
CPU time 72.9 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 03:01:52 PM PDT 24
Peak memory 256136 kb
Host smart-3519a7a6-1f8b-4063-b20a-c590b796c695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37469
65768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3746965768
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4026201839
Short name T48
Test name
Test status
Simulation time 820290284 ps
CPU time 29.46 seconds
Started May 12 03:00:38 PM PDT 24
Finished May 12 03:01:08 PM PDT 24
Peak memory 248852 kb
Host smart-52467f06-7595-4f1f-a05c-c3f5c16efa09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262
01839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4026201839
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2361044652
Short name T533
Test name
Test status
Simulation time 234404292 ps
CPU time 18.8 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 03:00:58 PM PDT 24
Peak memory 254016 kb
Host smart-3059f85f-a0c9-4eef-b02e-206a24e277eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23610
44652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2361044652
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1967924801
Short name T585
Test name
Test status
Simulation time 150579843 ps
CPU time 8.74 seconds
Started May 12 03:00:35 PM PDT 24
Finished May 12 03:00:44 PM PDT 24
Peak memory 248776 kb
Host smart-3c771f21-c851-48ba-a2e3-40cadaadff63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19679
24801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1967924801
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3805421286
Short name T57
Test name
Test status
Simulation time 455311604797 ps
CPU time 3960.57 seconds
Started May 12 03:00:39 PM PDT 24
Finished May 12 04:06:40 PM PDT 24
Peak memory 305624 kb
Host smart-58a85920-57dd-4c79-91f0-734547ed272e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805421286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3805421286
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1227703937
Short name T208
Test name
Test status
Simulation time 18143794 ps
CPU time 2.68 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 02:55:14 PM PDT 24
Peak memory 248948 kb
Host smart-384845cc-5a64-42f0-8736-f5af7111b450
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1227703937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1227703937
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1051135640
Short name T189
Test name
Test status
Simulation time 48725971874 ps
CPU time 1745.63 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 03:24:18 PM PDT 24
Peak memory 273380 kb
Host smart-bf2f2de4-5101-40ab-bb37-9186ce5811ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051135640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1051135640
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.792059886
Short name T386
Test name
Test status
Simulation time 866528802 ps
CPU time 13.86 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 02:55:26 PM PDT 24
Peak memory 240716 kb
Host smart-5a3a074b-e179-4e98-9427-8614de809891
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=792059886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.792059886
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1695247121
Short name T279
Test name
Test status
Simulation time 3445385473 ps
CPU time 151.02 seconds
Started May 12 02:55:09 PM PDT 24
Finished May 12 02:57:41 PM PDT 24
Peak memory 250924 kb
Host smart-4be9cf44-0f91-4f6e-ad48-fe5ffe4879df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16952
47121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1695247121
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2354929476
Short name T545
Test name
Test status
Simulation time 299268300 ps
CPU time 12.85 seconds
Started May 12 02:55:07 PM PDT 24
Finished May 12 02:55:21 PM PDT 24
Peak memory 255580 kb
Host smart-38948e5d-f8e9-4da2-8e1f-8ee81d7fcbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
29476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2354929476
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2020344513
Short name T470
Test name
Test status
Simulation time 8963125718 ps
CPU time 868.92 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 03:09:41 PM PDT 24
Peak memory 281808 kb
Host smart-e3323805-6cf8-492b-a124-8c58937a2b5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020344513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2020344513
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2936043173
Short name T544
Test name
Test status
Simulation time 5637820049 ps
CPU time 50.99 seconds
Started May 12 02:55:12 PM PDT 24
Finished May 12 02:56:03 PM PDT 24
Peak memory 248080 kb
Host smart-ca50d129-20f8-450c-b0d6-764df4ef8007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936043173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2936043173
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3995224422
Short name T605
Test name
Test status
Simulation time 778572902 ps
CPU time 47.49 seconds
Started May 12 02:55:07 PM PDT 24
Finished May 12 02:55:55 PM PDT 24
Peak memory 248736 kb
Host smart-e24da2d9-6759-4ab8-8169-63e11c8723d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39952
24422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3995224422
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4123483694
Short name T527
Test name
Test status
Simulation time 43218314 ps
CPU time 4.8 seconds
Started May 12 02:55:07 PM PDT 24
Finished May 12 02:55:13 PM PDT 24
Peak memory 239064 kb
Host smart-037f4b29-b53b-48ee-a4b6-7f82d34136a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41234
83694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4123483694
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2158581594
Short name T36
Test name
Test status
Simulation time 2555315563 ps
CPU time 42.81 seconds
Started May 12 02:55:09 PM PDT 24
Finished May 12 02:55:53 PM PDT 24
Peak memory 256932 kb
Host smart-9c0f6a8f-8db1-4800-8518-8ef0f6daf225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
81594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2158581594
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2982416162
Short name T4
Test name
Test status
Simulation time 64086126896 ps
CPU time 1318.74 seconds
Started May 12 02:55:12 PM PDT 24
Finished May 12 03:17:12 PM PDT 24
Peak memory 289288 kb
Host smart-262d300c-49d9-4d55-b0db-c0772ed4a183
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982416162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2982416162
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3343723834
Short name T191
Test name
Test status
Simulation time 196873272001 ps
CPU time 4637.31 seconds
Started May 12 02:55:11 PM PDT 24
Finished May 12 04:12:30 PM PDT 24
Peak memory 338432 kb
Host smart-59db6d79-cf36-48d6-adb6-a7afb1a011b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343723834 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3343723834
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2509666303
Short name T206
Test name
Test status
Simulation time 31468030 ps
CPU time 3.55 seconds
Started May 12 02:55:18 PM PDT 24
Finished May 12 02:55:22 PM PDT 24
Peak memory 248912 kb
Host smart-23a7cad7-61d0-4a13-aae6-6fe9095e7853
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2509666303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2509666303
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2515117300
Short name T499
Test name
Test status
Simulation time 28126657897 ps
CPU time 1358.33 seconds
Started May 12 02:55:13 PM PDT 24
Finished May 12 03:17:52 PM PDT 24
Peak memory 272392 kb
Host smart-c11be56a-097b-42a3-ae0d-3d2f20f29fc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515117300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2515117300
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3226860184
Short name T684
Test name
Test status
Simulation time 1553143705 ps
CPU time 19.64 seconds
Started May 12 02:55:14 PM PDT 24
Finished May 12 02:55:35 PM PDT 24
Peak memory 240580 kb
Host smart-94d410d4-0854-4aba-b42f-6e6afe792fcf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3226860184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3226860184
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4232232099
Short name T658
Test name
Test status
Simulation time 10701264215 ps
CPU time 145.33 seconds
Started May 12 02:55:15 PM PDT 24
Finished May 12 02:57:41 PM PDT 24
Peak memory 256964 kb
Host smart-b75151b0-7810-4f44-855f-4554b3b1f426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
32099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4232232099
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2966158978
Short name T589
Test name
Test status
Simulation time 836359199 ps
CPU time 49.18 seconds
Started May 12 02:55:12 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 248972 kb
Host smart-ec0032b3-7306-4124-ad85-46fb0d5e63a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29661
58978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2966158978
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3873732850
Short name T669
Test name
Test status
Simulation time 66898344518 ps
CPU time 1729.11 seconds
Started May 12 02:55:14 PM PDT 24
Finished May 12 03:24:04 PM PDT 24
Peak memory 288992 kb
Host smart-a4f8fa9c-eb95-493a-b54d-d2320302a6c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873732850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3873732850
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2961172342
Short name T671
Test name
Test status
Simulation time 19364543181 ps
CPU time 1173.71 seconds
Started May 12 02:55:14 PM PDT 24
Finished May 12 03:14:48 PM PDT 24
Peak memory 270492 kb
Host smart-9482ac55-c167-4c04-aa21-dbf6ef39681c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961172342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2961172342
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1804297388
Short name T302
Test name
Test status
Simulation time 49562545145 ps
CPU time 420.6 seconds
Started May 12 02:55:16 PM PDT 24
Finished May 12 03:02:17 PM PDT 24
Peak memory 248328 kb
Host smart-697bb632-0d8e-4690-8b15-97380b23935f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804297388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1804297388
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2271065586
Short name T281
Test name
Test status
Simulation time 105039033 ps
CPU time 12.24 seconds
Started May 12 02:55:14 PM PDT 24
Finished May 12 02:55:27 PM PDT 24
Peak memory 248952 kb
Host smart-4ff30cc5-eeba-4553-a3d0-8df7bdb72ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22710
65586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2271065586
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1639901231
Short name T467
Test name
Test status
Simulation time 362565141 ps
CPU time 12.75 seconds
Started May 12 02:55:14 PM PDT 24
Finished May 12 02:55:27 PM PDT 24
Peak memory 253868 kb
Host smart-e08105c6-1f09-4e24-9fd9-dbf31efb46a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16399
01231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1639901231
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.909913682
Short name T262
Test name
Test status
Simulation time 2894327662 ps
CPU time 47.39 seconds
Started May 12 02:55:13 PM PDT 24
Finished May 12 02:56:01 PM PDT 24
Peak memory 255928 kb
Host smart-3b669996-d051-4caf-8a73-32189d3eae04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90991
3682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.909913682
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.581366271
Short name T626
Test name
Test status
Simulation time 1358916003 ps
CPU time 31.27 seconds
Started May 12 02:55:15 PM PDT 24
Finished May 12 02:55:47 PM PDT 24
Peak memory 248780 kb
Host smart-78efb88f-dec0-4474-aee3-0db049660961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58136
6271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.581366271
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2778785205
Short name T74
Test name
Test status
Simulation time 16651372221 ps
CPU time 1945.92 seconds
Started May 12 02:55:18 PM PDT 24
Finished May 12 03:27:44 PM PDT 24
Peak memory 289792 kb
Host smart-bbeb2641-8711-43cf-bd2c-cf55f6481d05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778785205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2778785205
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.144046694
Short name T211
Test name
Test status
Simulation time 19252192 ps
CPU time 3.03 seconds
Started May 12 02:55:21 PM PDT 24
Finished May 12 02:55:24 PM PDT 24
Peak memory 248944 kb
Host smart-dfdc89cf-db19-402c-82e9-24d145a6f7e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=144046694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.144046694
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2981728144
Short name T60
Test name
Test status
Simulation time 577857245 ps
CPU time 9.78 seconds
Started May 12 02:55:22 PM PDT 24
Finished May 12 02:55:32 PM PDT 24
Peak memory 240552 kb
Host smart-3a4421c2-3042-4ae6-9793-d6cc7adf848f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2981728144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2981728144
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4056533579
Short name T598
Test name
Test status
Simulation time 1243355174 ps
CPU time 96.6 seconds
Started May 12 02:55:18 PM PDT 24
Finished May 12 02:56:55 PM PDT 24
Peak memory 256936 kb
Host smart-7b264fff-3539-4812-bbed-9659b6d8e968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40565
33579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4056533579
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2271308188
Short name T582
Test name
Test status
Simulation time 358092253 ps
CPU time 35.97 seconds
Started May 12 02:55:19 PM PDT 24
Finished May 12 02:55:56 PM PDT 24
Peak memory 255908 kb
Host smart-74d10713-9dfc-48c4-bf44-1c30ff6a7077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
08188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2271308188
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1094673226
Short name T634
Test name
Test status
Simulation time 57287235035 ps
CPU time 3271.36 seconds
Started May 12 02:55:20 PM PDT 24
Finished May 12 03:49:52 PM PDT 24
Peak memory 288352 kb
Host smart-bc78036a-7451-4f17-8093-ba7c61ca21e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094673226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1094673226
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1825638281
Short name T402
Test name
Test status
Simulation time 149307600794 ps
CPU time 2838.33 seconds
Started May 12 02:55:24 PM PDT 24
Finished May 12 03:42:44 PM PDT 24
Peak memory 281568 kb
Host smart-28afe1d6-94ce-480d-ab11-2dcb791a7d44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825638281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1825638281
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4253615421
Short name T683
Test name
Test status
Simulation time 25221409092 ps
CPU time 264.28 seconds
Started May 12 02:55:21 PM PDT 24
Finished May 12 02:59:46 PM PDT 24
Peak memory 247960 kb
Host smart-3e2ffc42-34ec-4240-b8a7-3f8b4dc8c912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253615421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4253615421
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.224919338
Short name T44
Test name
Test status
Simulation time 3660335952 ps
CPU time 44.43 seconds
Started May 12 02:55:17 PM PDT 24
Finished May 12 02:56:02 PM PDT 24
Peak memory 248828 kb
Host smart-59d8fadf-ce66-47fc-a2aa-cecb0782e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22491
9338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.224919338
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3060731549
Short name T15
Test name
Test status
Simulation time 1997377169 ps
CPU time 35.27 seconds
Started May 12 02:55:16 PM PDT 24
Finished May 12 02:55:52 PM PDT 24
Peak memory 248880 kb
Host smart-cc8860b8-2b58-4acf-a4f6-37642e244526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30607
31549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3060731549
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3174859862
Short name T222
Test name
Test status
Simulation time 140130633 ps
CPU time 16.37 seconds
Started May 12 02:55:22 PM PDT 24
Finished May 12 02:55:39 PM PDT 24
Peak memory 247372 kb
Host smart-d2d312e4-7045-407e-8b8f-a659896cd9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
59862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3174859862
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1548767673
Short name T495
Test name
Test status
Simulation time 282159879 ps
CPU time 20.45 seconds
Started May 12 02:55:17 PM PDT 24
Finished May 12 02:55:38 PM PDT 24
Peak memory 248772 kb
Host smart-5756a3d5-0cee-48d0-a961-beff84d0e791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
67673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1548767673
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1274244595
Short name T568
Test name
Test status
Simulation time 255868744763 ps
CPU time 4163.91 seconds
Started May 12 02:55:21 PM PDT 24
Finished May 12 04:04:46 PM PDT 24
Peak memory 299804 kb
Host smart-9bc09a7a-a276-46c3-8bb7-9982ecad86d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274244595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1274244595
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.4200232906
Short name T213
Test name
Test status
Simulation time 129570219 ps
CPU time 3.54 seconds
Started May 12 02:55:27 PM PDT 24
Finished May 12 02:55:31 PM PDT 24
Peak memory 248964 kb
Host smart-88634b9a-3f35-45f2-bc04-de68f28615f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4200232906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4200232906
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3491590066
Short name T650
Test name
Test status
Simulation time 61535725361 ps
CPU time 1561.77 seconds
Started May 12 02:55:24 PM PDT 24
Finished May 12 03:21:26 PM PDT 24
Peak memory 289052 kb
Host smart-fd417d26-01c9-44ad-96f2-820a3ce818bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491590066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3491590066
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.854804255
Short name T481
Test name
Test status
Simulation time 3054001599 ps
CPU time 44.29 seconds
Started May 12 02:55:28 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 248792 kb
Host smart-5b694081-b2a6-4e71-8f64-e3c3447872cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=854804255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.854804255
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2398943678
Short name T694
Test name
Test status
Simulation time 839401871 ps
CPU time 19.82 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 02:55:46 PM PDT 24
Peak memory 248760 kb
Host smart-578a965b-7c25-44c1-9f82-d6051a45df0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23989
43678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2398943678
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.21958071
Short name T260
Test name
Test status
Simulation time 1099391705 ps
CPU time 27.48 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 02:55:53 PM PDT 24
Peak memory 255888 kb
Host smart-cd7024ab-3e66-44d9-9d3b-438a7652c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21958
071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.21958071
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1437076158
Short name T290
Test name
Test status
Simulation time 31934948114 ps
CPU time 2118.15 seconds
Started May 12 02:55:29 PM PDT 24
Finished May 12 03:30:48 PM PDT 24
Peak memory 272628 kb
Host smart-e76fb353-897e-4afe-a5d0-aaf0ef3ab994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437076158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1437076158
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3449227788
Short name T518
Test name
Test status
Simulation time 33474947278 ps
CPU time 1276.38 seconds
Started May 12 02:55:29 PM PDT 24
Finished May 12 03:16:46 PM PDT 24
Peak memory 286096 kb
Host smart-08fd3043-edc6-43f0-a606-9592f384cc53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449227788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3449227788
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1649949459
Short name T301
Test name
Test status
Simulation time 92953177234 ps
CPU time 441.08 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 254884 kb
Host smart-770ad28a-d032-47dd-96cf-111feeee8568
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649949459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1649949459
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1779469102
Short name T558
Test name
Test status
Simulation time 148537412 ps
CPU time 10.48 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 02:55:36 PM PDT 24
Peak memory 248776 kb
Host smart-e7cf78ab-6804-4e79-8d1d-1f23e60593db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17794
69102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1779469102
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2774419226
Short name T100
Test name
Test status
Simulation time 635221102 ps
CPU time 37.52 seconds
Started May 12 02:55:26 PM PDT 24
Finished May 12 02:56:04 PM PDT 24
Peak memory 255756 kb
Host smart-2597f6c4-2d8f-4700-9dab-c6b80ad4a7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744
19226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2774419226
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1394092587
Short name T595
Test name
Test status
Simulation time 86800140 ps
CPU time 7.34 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 02:55:33 PM PDT 24
Peak memory 240716 kb
Host smart-9843ed10-7f6e-4652-bf81-dbfb8311b249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13940
92587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1394092587
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.4001089541
Short name T372
Test name
Test status
Simulation time 412835168 ps
CPU time 21.94 seconds
Started May 12 02:55:25 PM PDT 24
Finished May 12 02:55:47 PM PDT 24
Peak memory 248772 kb
Host smart-558cc735-0d30-4bd5-b071-0afb4a42aa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
89541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.4001089541
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1376617778
Short name T102
Test name
Test status
Simulation time 15473520885 ps
CPU time 2080.41 seconds
Started May 12 02:55:28 PM PDT 24
Finished May 12 03:30:09 PM PDT 24
Peak memory 289548 kb
Host smart-e094788b-9f9d-43ef-8902-8ed0b6a0e8b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376617778 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1376617778
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.572365888
Short name T214
Test name
Test status
Simulation time 117015119 ps
CPU time 3.8 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 02:55:47 PM PDT 24
Peak memory 248884 kb
Host smart-d37c900a-11e4-42ca-a341-cb30f7466f47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=572365888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.572365888
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3800589365
Short name T458
Test name
Test status
Simulation time 31973535886 ps
CPU time 1593.37 seconds
Started May 12 02:55:33 PM PDT 24
Finished May 12 03:22:07 PM PDT 24
Peak memory 288876 kb
Host smart-e5229525-1e46-4b42-814b-b87276e39c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800589365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3800589365
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1242618227
Short name T426
Test name
Test status
Simulation time 1047981097 ps
CPU time 41.7 seconds
Started May 12 02:55:35 PM PDT 24
Finished May 12 02:56:17 PM PDT 24
Peak memory 248772 kb
Host smart-ab3d1a13-d2f9-4929-ba53-ab7fec988db9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1242618227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1242618227
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.93845587
Short name T425
Test name
Test status
Simulation time 1344948894 ps
CPU time 74.49 seconds
Started May 12 02:55:31 PM PDT 24
Finished May 12 02:56:46 PM PDT 24
Peak memory 248564 kb
Host smart-4d3c7286-27b2-450f-8390-635a79a998e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93845
587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.93845587
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.797967831
Short name T579
Test name
Test status
Simulation time 2793508346 ps
CPU time 40.82 seconds
Started May 12 02:55:32 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 255600 kb
Host smart-55b033df-b3bf-4350-be4a-2e1906d01023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79796
7831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.797967831
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.516387187
Short name T34
Test name
Test status
Simulation time 35046184416 ps
CPU time 725.71 seconds
Started May 12 02:55:43 PM PDT 24
Finished May 12 03:07:49 PM PDT 24
Peak memory 273344 kb
Host smart-d5be50e0-abe7-45f8-9201-ca6257b45e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516387187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.516387187
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1365843224
Short name T536
Test name
Test status
Simulation time 92305647437 ps
CPU time 1702.19 seconds
Started May 12 02:55:36 PM PDT 24
Finished May 12 03:23:59 PM PDT 24
Peak memory 273388 kb
Host smart-f8a5edd9-fd56-4180-9104-f4b441b38dbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365843224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1365843224
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1394929674
Short name T312
Test name
Test status
Simulation time 18704205477 ps
CPU time 384.28 seconds
Started May 12 02:55:36 PM PDT 24
Finished May 12 03:02:01 PM PDT 24
Peak memory 248260 kb
Host smart-94313d27-20bd-43fb-ba16-39ccb81705b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394929674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1394929674
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.748808070
Short name T421
Test name
Test status
Simulation time 649309206 ps
CPU time 15.43 seconds
Started May 12 02:55:34 PM PDT 24
Finished May 12 02:55:50 PM PDT 24
Peak memory 248704 kb
Host smart-42db44b5-06f9-48e9-8336-1516a1b01fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74880
8070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.748808070
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.778099884
Short name T38
Test name
Test status
Simulation time 1459707609 ps
CPU time 36.23 seconds
Started May 12 02:55:34 PM PDT 24
Finished May 12 02:56:10 PM PDT 24
Peak memory 254752 kb
Host smart-5ab5ff61-e6ac-4c04-9fd7-215e02a7329f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77809
9884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.778099884
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1832825891
Short name T464
Test name
Test status
Simulation time 570791195 ps
CPU time 40.11 seconds
Started May 12 02:55:32 PM PDT 24
Finished May 12 02:56:13 PM PDT 24
Peak memory 254324 kb
Host smart-df4761e8-1dd5-42a8-8448-65a8b221b343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18328
25891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1832825891
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.297603996
Short name T370
Test name
Test status
Simulation time 229719811 ps
CPU time 14.28 seconds
Started May 12 02:55:30 PM PDT 24
Finished May 12 02:55:44 PM PDT 24
Peak memory 248716 kb
Host smart-c0f116fd-fca0-40e8-942f-8d037dd90fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
3996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.297603996
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2241024546
Short name T534
Test name
Test status
Simulation time 30696565043 ps
CPU time 1245.52 seconds
Started May 12 02:55:36 PM PDT 24
Finished May 12 03:16:22 PM PDT 24
Peak memory 288896 kb
Host smart-f451f1c0-118b-4691-b81b-770da20c0fa8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241024546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2241024546
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.619202637
Short name T540
Test name
Test status
Simulation time 75682343710 ps
CPU time 4843.4 seconds
Started May 12 02:55:33 PM PDT 24
Finished May 12 04:16:18 PM PDT 24
Peak memory 338396 kb
Host smart-20ffe728-39d1-4af2-b336-b82893a51895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619202637 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.619202637
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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