Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	80200	1			T1	60		T5	9		T9	1
class_i[0x1]	56369	1			T4	2		T17	1209		T5	19
class_i[0x2]	55865	1			T1	4		T4	15		T18	177
class_i[0x3]	67626	1			T1	6		T17	1921		T9	5

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	69808	1			T1	14		T4	1		T17	958
alert[0x1]	64509	1			T1	21		T4	7		T17	605
alert[0x2]	62503	1			T1	27		T4	2		T17	894
alert[0x3]	63240	1			T1	8		T4	7		T17	673

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

259783

1

T1

70

T4

17

T17

3130

esc_ping_fail

277

1

T5

9

T9

6

T10

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	69738	1			T1	14		T4	1		T17	958
esc_integrity_fail	alert[0x1]	64433	1			T1	21		T4	7		T17	605
esc_integrity_fail	alert[0x2]	62434	1			T1	27		T4	2		T17	894
esc_integrity_fail	alert[0x3]	63178	1			T1	8		T4	7		T17	673
esc_ping_fail	alert[0x0]	70	1			T5	2		T10	1		T225	2
esc_ping_fail	alert[0x1]	76	1			T5	3		T9	2		T10	2
esc_ping_fail	alert[0x2]	69	1			T5	1		T9	2		T10	3
esc_ping_fail	alert[0x3]	62	1			T5	3		T9	2		T10	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	80131	1			T1	60		T9	1		T14	2213
esc_integrity_fail	class_i[0x1]	56292	1			T4	2		T17	1209		T5	19
esc_integrity_fail	class_i[0x2]	55797	1			T1	4		T4	15		T18	177
esc_integrity_fail	class_i[0x3]	67563	1			T1	6		T17	1921		T9	4
esc_ping_fail	class_i[0x0]	69	1			T5	9		T10	8		T225	4
esc_ping_fail	class_i[0x1]	77	1			T218	3		T289	1		T290	5
esc_ping_fail	class_i[0x2]	68	1			T9	5		T220	2		T287	5
esc_ping_fail	class_i[0x3]	63	1			T9	1		T221	5		T218	1