Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	674959995	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	674959995	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	674959995	674811777	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	674959995	674811777	0	0
tb.dut.EdnKnownO_A	0	0	674959995	674811777	0	0
tb.dut.EscPKnownO_A	0	0	674959995	674811777	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	674959995	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	674959995	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	674959995	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	674959995	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	674959995	60	0	0
tb.dut.IrqAKnownO_A	0	0	674959995	674811777	0	0
tb.dut.IrqBKnownO_A	0	0	674959995	674811777	0	0
tb.dut.IrqCKnownO_A	0	0	674959995	674811777	0	0
tb.dut.IrqDKnownO_A	0	0	674959995	674811777	0	0
tb.dut.TlAReadyKnownO_A	0	0	674959995	674811777	0	0
tb.dut.TlDValidKnownO_A	0	0	674959995	674811777	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	696880995	3245964	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	696880995	13459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	696880995	14414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	696880995	13820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	696880995	13514	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	696880995	15820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	696880995	14740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	696880995	15013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	696880995	14728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	696880995	15384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	696880995	15724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	696880995	13974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	696880995	14472	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	696880995	14491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	696880995	15355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	696880995	13302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	696880995	15641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	696880995	15781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	696880995	14167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	696880995	13593	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	696880995	15547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	696880995	14805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	696880995	16388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	696880995	14035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	696880995	17804	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	696880995	17326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	696880995	13163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	696880995	13098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	696880995	15160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	696880995	13133	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	696880995	14512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	696880995	15621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	696880995	14041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	696880995	14337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	696880995	13184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	696880995	15590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	696880995	15540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	696880995	14237	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	696880995	15525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	696880995	15666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	696880995	15536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	696880995	13288	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	696880995	15831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	696880995	15433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	696880995	13239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	696880995	14508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	696880995	15559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	696880995	13334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	696880995	14401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	696880995	14798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	696880995	13445	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	696880995	13139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	696880995	16025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	696880995	13216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	696880995	16845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	696880995	14166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	696880995	14566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	696880995	15324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	696880995	13139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	696880995	14371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	696880995	13641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	696880995	14209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	696880995	14913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	696880995	13653	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	696880995	13994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	696880995	14431	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	696880995	13995	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	696880995	15559	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	696880995	14183	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	696880995	14951	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	696880995	27312	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	696880995	14444	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	696880995	14581	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	696880995	13912	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	696880995	14183	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	696880995	13192	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	696880995	13171	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	696880995	13424	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	696880995	15512	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	674959995	3180	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	674959995	240909	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	674959995	326764215	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	674959995	261	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	674959995	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	674959995	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	674959995	428	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	674845748	229059465	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	674959995	985	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	674959995	973	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	674959995	951	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	674959995	934	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	674959995	1167	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	674959995	114547	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	674959995	1056	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	674959995	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674959995	1079	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	674959995	899	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	674844385	674772097	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	674959995	674811777	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	674959995	4866	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	674959995	146532	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	674959995	400308464	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	674959995	213	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	674959995	469	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	674959995	15	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	674959995	190	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	674845748	315349995	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	674959995	524	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	674959995	512	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	674959995	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	674959995	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	674959995	1243	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	674959995	124806	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	674959995	1176	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	674959995	52	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674959995	1124	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	674959995	944	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	674844385	674772097	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	674959995	674811777	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	674959995	1921	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	674959995	181115	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	674959995	400064677	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	674959995	200	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	674959995	464	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	674959995	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	674959995	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	674845748	311637746	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	674959995	565	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	674959995	559	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	674959995	549	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	674959995	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	674959995	620	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	674959995	79972	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	674959995	514	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	674959995	88	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674959995	1018	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	674959995	838	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	674844385	674772097	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	674959995	674811777	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	674959995	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	674959995	5193	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	674959995	176601	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	674959995	366332026	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	674959995	213	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	674959995	530	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	674959995	29	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	674959995	266	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	674845748	282614842	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	674959995	622	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	674959995	609	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	674959995	594	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	674959995	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	674959995	1341	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	674959995	145322	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	674959995	1242	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	674959995	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674959995	1013	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	674959995	833	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	674844385	674772097	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	674959995	674811777	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	696880995	133736730	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	696880995	696270146	0	0
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