Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T18	1		T43	2		T25	1
class_index[0x1]	52	1			T17	2		T70	3		T43	2
class_index[0x2]	88	1			T1	1		T17	3		T18	1
class_index[0x3]	69	1			T18	4		T73	2		T68	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	91	1			T1	1		T17	1		T73	1
intr_timeout_cnt[1]	48	1			T18	1		T66	1		T70	3
intr_timeout_cnt[2]	39	1			T17	3		T43	4		T25	1
intr_timeout_cnt[3]	17	1			T18	1		T73	1		T72	1
intr_timeout_cnt[4]	20	1			T17	1		T43	1		T78	1
intr_timeout_cnt[5]	17	1			T18	4		T79	1		T82	1
intr_timeout_cnt[6]	9	1			T68	1		T70	1		T83	1
intr_timeout_cnt[7]	16	1			T47	2		T213	1		T97	1
intr_timeout_cnt[8]	4	1			T25	1		T84	1		T262	1
intr_timeout_cnt[9]	10	1			T68	1		T70	2		T84	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T78	1		T101	1		T96	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T81	1		T85	1		T95	1
class_index[0x0]	intr_timeout_cnt[2]	11	1			T43	1		T25	1		T51	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T18	1		T72	1		T263	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T43	1		T52	1		T264	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T79	1		T265	2		T266	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T234	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T47	2		T51	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T84	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T17	1		T80	1		T86	1
class_index[0x1]	intr_timeout_cnt[1]	3	1			T267	1		T268	2		-	-
class_index[0x1]	intr_timeout_cnt[2]	7	1			T43	2		T83	1		T269	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T270	1		T271	3		T254	1
class_index[0x1]	intr_timeout_cnt[4]	6	1			T17	1		T81	1		T85	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T82	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T70	1		T83	1		T86	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T272	1		T106	2		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T25	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T70	2		T98	1		T273	1
class_index[0x2]	intr_timeout_cnt[0]	29	1			T1	1		T7	1		T77	1
class_index[0x2]	intr_timeout_cnt[1]	19	1			T18	1		T66	1		T70	2
class_index[0x2]	intr_timeout_cnt[2]	15	1			T17	3		T43	1		T79	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T49	1		T260	1		T266	1
class_index[0x2]	intr_timeout_cnt[4]	7	1			T78	1		T239	1		T96	1
class_index[0x2]	intr_timeout_cnt[5]	5	1			T83	1		T260	2		T274	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T68	1		T275	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T213	1		T276	1		T106	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T262	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T174	1		T112	1		T23	2
class_index[0x3]	intr_timeout_cnt[0]	22	1			T73	1		T95	1		T49	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T70	1		T80	1		T85	2
class_index[0x3]	intr_timeout_cnt[2]	6	1			T81	1		T52	1		T249	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T73	1		T83	1		T111	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T277	1		T278	1		T88	2
class_index[0x3]	intr_timeout_cnt[5]	6	1			T18	4		T96	1		T51	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T239	2		T266	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	7	1			T97	1		T89	4		T276	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T265	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T68	1		T84	1		-	-