Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346643	1			T1	2307		T3	23		T4	1993
all_values[1]	346643	1			T1	2307		T3	23		T4	1993
all_values[2]	346643	1			T1	2307		T3	23		T4	1993
all_values[3]	346643	1			T1	2307		T3	23		T4	1993

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689227

1

T1

4699

T3

37

T4

3928

auto[1]

697345

1

T1

4529

T3

55

T4

4044

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

822466

1

T1

4869

T3

81

T4

4016

auto[1]

564106

1

T1

4359

T3

11

T4

3956

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98436	1			T1	618		T3	4		T4	493
all_values[0]	auto[0]	auto[1]	73937	1			T1	588		T3	3		T4	493
all_values[0]	auto[1]	auto[0]	100354	1			T1	568		T3	8		T4	508
all_values[0]	auto[1]	auto[1]	73916	1			T1	533		T3	8		T4	499
all_values[1]	auto[0]	auto[0]	103934	1			T1	607		T3	6		T4	494
all_values[1]	auto[0]	auto[1]	67956	1			T1	548		T4	484		T17	398
all_values[1]	auto[1]	auto[0]	106264	1			T1	611		T3	17		T4	511
all_values[1]	auto[1]	auto[1]	68489	1			T1	541		T4	504		T17	402
all_values[2]	auto[0]	auto[0]	102382	1			T1	627		T3	13		T4	482
all_values[2]	auto[0]	auto[1]	69793	1			T1	557		T4	469		T17	374
all_values[2]	auto[1]	auto[0]	104219	1			T1	602		T3	10		T4	525
all_values[2]	auto[1]	auto[1]	70249	1			T1	521		T4	517		T17	401
all_values[3]	auto[0]	auto[0]	102878	1			T1	614		T3	11		T4	511
all_values[3]	auto[0]	auto[1]	69911	1			T1	540		T4	502		T17	409
all_values[3]	auto[1]	auto[0]	103999	1			T1	622		T3	12		T4	492
all_values[3]	auto[1]	auto[1]	69855	1			T1	531		T4	488		T17	375