Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	346643	1			T1	2307		T3	23		T4	1993
all_pins[1]	346643	1			T1	2307		T3	23		T4	1993
all_pins[2]	346643	1			T1	2307		T3	23		T4	1993
all_pins[3]	346643	1			T1	2307		T3	23		T4	1993

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1104063	1			T1	7102		T3	84		T4	5964
values[0x1]	282509	1			T1	2126		T3	8		T4	2008
transitions[0x0=>0x1]	188196	1			T1	1353		T3	7		T4	1227
transitions[0x1=>0x0]	188442	1			T1	1353		T3	8		T4	1228

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	272727	1			T1	1774		T3	15		T4	1494
all_pins[0]	values[0x1]	73916	1			T1	533		T3	8		T4	499
all_pins[0]	transitions[0x0=>0x1]	73206	1			T1	533		T3	7		T4	498
all_pins[0]	transitions[0x1=>0x0]	69391	1			T1	531		T4	488		T17	369
all_pins[1]	values[0x0]	278154	1			T1	1766		T3	23		T4	1489
all_pins[1]	values[0x1]	68489	1			T1	541		T4	504		T17	402
all_pins[1]	transitions[0x0=>0x1]	37711	1			T1	276		T4	245		T17	224
all_pins[1]	transitions[0x1=>0x0]	43138	1			T1	268		T3	8		T4	240
all_pins[2]	values[0x0]	276394	1			T1	1786		T3	23		T4	1476
all_pins[2]	values[0x1]	70249	1			T1	521		T4	517		T17	401
all_pins[2]	transitions[0x0=>0x1]	38983	1			T1	269		T4	255		T17	202
all_pins[2]	transitions[0x1=>0x0]	37223	1			T1	289		T4	242		T17	203
all_pins[3]	values[0x0]	276788	1			T1	1776		T3	23		T4	1505
all_pins[3]	values[0x1]	69855	1			T1	531		T4	488		T17	375
all_pins[3]	transitions[0x0=>0x1]	38296	1			T1	275		T4	229		T17	206
all_pins[3]	transitions[0x1=>0x0]	38690	1			T1	265		T4	258		T17	232