Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T155	7		T156	4		T157	4
all_values[1]	275	1			T155	7		T156	4		T157	4
all_values[2]	275	1			T155	7		T156	4		T157	4
all_values[3]	275	1			T155	7		T156	4		T157	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T155

18

T156

7

T157

9

auto[1]

501

1

T155

10

T156

9

T157

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

442

1

T155

12

T156

11

T157

11

auto[1]

658

1

T155

16

T156

5

T157

5

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T155

16

T156

12

T157

12

auto[1]

458

1

T155

12

T156

4

T157

4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T156

1

T157

1

T230

4

all_values[0]

auto[0]

auto[0]

auto[1]

21

1

T157

1

T217

2

T323

1

all_values[0]

auto[0]

auto[1]

auto[0]

53

1

T155

4

T156

2

T217

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T231

1

T232

2

T323

1

all_values[0]

auto[1]

auto[0]

auto[1]

72

1

T155

1

T157

2

T217

1

all_values[0]

auto[1]

auto[1]

auto[1]

46

1

T155

2

T156

1

T217

3

all_values[1]

auto[0]

auto[0]

auto[0]

59

1

T155

1

T217

1

T230

2

all_values[1]

auto[0]

auto[0]

auto[1]

19

1

T230

1

T232

1

T323

1

all_values[1]

auto[0]

auto[1]

auto[0]

60

1

T156

2

T157

4

T217

3

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T155

2

T156

1

T217

1

all_values[1]

auto[1]

auto[0]

auto[1]

68

1

T155

4

T217

1

T230

1

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T156

1

T217

1

T232

1

all_values[2]

auto[0]

auto[0]

auto[0]

53

1

T155

3

T156

2

T157

1

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T155

1

T230

3

T232

1

all_values[2]

auto[0]

auto[1]

auto[0]

51

1

T156

1

T157

1

T217

3

all_values[2]

auto[0]

auto[1]

auto[1]

34

1

T230

1

T233

1

T324

1

all_values[2]

auto[1]

auto[0]

auto[1]

67

1

T155

3

T156

1

T157

2

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T232

2

T233

1

T325

1

all_values[3]

auto[0]

auto[0]

auto[0]

72

1

T155

3

T156

3

T157

2

all_values[3]

auto[0]

auto[0]

auto[1]

26

1

T155

1

T217

1

T230

1

all_values[3]

auto[0]

auto[1]

auto[0]

35

1

T155

1

T157

2

T217

1

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T217

2

T230

1

T231

3

all_values[3]

auto[1]

auto[0]

auto[1]

59

1

T155

1

T217

1

T230

2

all_values[3]

auto[1]

auto[1]

auto[1]

51

1

T155

1

T156

1

T217

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal