Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90357	1			T1	1797		T4	585		T17	326
accum_cnt_1000	230322	1			T1	2019		T4	527		T17	1553
accum_cnt_100	25492	1			T1	316		T4	31		T17	93
accum_cnt_50	66047	1			T1	360		T4	13		T17	114
accum_cnt_10	204447	1			T1	304		T3	8		T4	7
accum_cnt_0	372703	1			T1	1867		T3	56		T4	4465

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256385	1			T1	1692		T3	16		T4	1489
class_index[0x1]	256385	1			T1	1692		T3	16		T4	1489
class_index[0x2]	256385	1			T1	1692		T3	16		T4	1489
class_index[0x3]	256385	1			T1	1692		T3	16		T4	1489

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23513	1			T14	233		T15	180		T69	580
class_index[0x0]	accum_cnt_1000	65574	1			T1	45		T17	748		T18	34
class_index[0x0]	accum_cnt_100	7509	1			T1	41		T17	26		T18	29
class_index[0x0]	accum_cnt_50	14729	1			T1	90		T17	30		T18	31
class_index[0x0]	accum_cnt_10	58649	1			T1	71		T3	8		T4	3
class_index[0x0]	accum_cnt_0	73129	1			T1	1445		T3	8		T4	1486
class_index[0x1]	accum_cnt_2000	19648	1			T1	637		T17	326		T73	69
class_index[0x1]	accum_cnt_1000	49445	1			T1	577		T17	632		T73	840
class_index[0x1]	accum_cnt_100	6299	1			T1	98		T17	35		T73	52
class_index[0x1]	accum_cnt_50	15554	1			T1	98		T17	43		T19	6
class_index[0x1]	accum_cnt_10	54182	1			T1	59		T17	26		T5	43
class_index[0x1]	accum_cnt_0	104194	1			T1	118		T3	16		T4	1489
class_index[0x2]	accum_cnt_2000	23144	1			T1	585		T15	96		T16	431
class_index[0x2]	accum_cnt_1000	56246	1			T1	700		T17	61		T18	25
class_index[0x2]	accum_cnt_100	6196	1			T1	108		T17	32		T18	6
class_index[0x2]	accum_cnt_50	17092	1			T1	109		T17	27		T18	9
class_index[0x2]	accum_cnt_10	40976	1			T1	40		T4	1		T17	17
class_index[0x2]	accum_cnt_0	105004	1			T1	150		T3	16		T4	1488
class_index[0x3]	accum_cnt_2000	24052	1			T1	575		T4	585		T73	253
class_index[0x3]	accum_cnt_1000	59057	1			T1	697		T4	527		T17	112
class_index[0x3]	accum_cnt_100	5488	1			T1	69		T4	31		T73	15
class_index[0x3]	accum_cnt_50	18672	1			T1	63		T4	13		T17	14
class_index[0x3]	accum_cnt_10	50640	1			T1	134		T4	3		T17	919
class_index[0x3]	accum_cnt_0	90376	1			T1	154		T3	16		T4	2