Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4212	1			T4	1055		T5	1		T10	1
alert[0x1]	9231	1			T4	127		T17	2		T10	1
alert[0x2]	5176	1			T17	2		T75	44		T221	1
alert[0x3]	6559	1			T4	29		T17	19		T16	105
alert[0x4]	2653	1			T9	1		T43	21		T25	2
alert[0x5]	4914	1			T17	1		T9	1		T10	1
alert[0x6]	4955	1			T15	4		T16	30		T71	3
alert[0x7]	7230	1			T5	1		T37	1		T75	176
alert[0x8]	2323	1			T5	3		T8	1		T16	82
alert[0x9]	3474	1			T4	3		T15	21		T10	1
alert[0xa]	9909	1			T15	3		T75	843		T71	221
alert[0xb]	9165	1			T73	51		T16	212		T75	81
alert[0xc]	9144	1			T4	28		T5	2		T15	16
alert[0xd]	8044	1			T4	2626		T75	16		T71	260
alert[0xe]	4697	1			T15	6		T37	23		T16	650
alert[0xf]	5823	1			T4	65		T17	17		T15	16
alert[0x10]	3080	1			T73	3		T16	43		T43	531
alert[0x11]	4174	1			T17	43		T16	13		T75	34
alert[0x12]	4709	1			T73	7		T16	20		T75	17
alert[0x13]	6321	1			T4	24		T9	1		T43	13
alert[0x14]	5196	1			T4	146		T15	3		T16	20
alert[0x15]	6148	1			T4	291		T75	12		T43	62
alert[0x16]	5330	1			T4	123		T17	13		T14	1
alert[0x17]	12994	1			T15	2		T37	2		T16	473
alert[0x18]	6732	1			T5	1		T15	1		T10	2
alert[0x19]	2414	1			T37	11		T16	372		T71	41
alert[0x1a]	7256	1			T4	784		T17	525		T15	8
alert[0x1b]	4964	1			T15	6		T16	14		T75	45
alert[0x1c]	6913	1			T4	41		T5	1		T16	275
alert[0x1d]	7874	1			T15	8		T16	4041		T75	12
alert[0x1e]	4233	1			T4	11		T16	1210		T75	21
alert[0x1f]	9945	1			T9	1		T75	1		T221	1
alert[0x20]	4936	1			T4	912		T17	29		T5	1
alert[0x21]	8350	1			T4	29		T5	3		T10	1
alert[0x22]	8489	1			T4	312		T17	15		T5	1
alert[0x23]	4865	1			T4	46		T14	3		T37	1
alert[0x24]	8398	1			T4	91		T17	1		T10	1
alert[0x25]	5142	1			T10	1		T75	183		T71	11
alert[0x26]	2066	1			T4	92		T75	13		T43	468
alert[0x27]	5318	1			T4	940		T17	4		T5	1
alert[0x28]	8981	1			T4	177		T9	1		T37	3
alert[0x29]	6685	1			T5	1		T37	4		T71	10
alert[0x2a]	3238	1			T4	59		T14	7		T37	104
alert[0x2b]	5463	1			T8	2		T75	297		T221	1
alert[0x2c]	4789	1			T5	1		T16	11		T75	226
alert[0x2d]	5644	1			T15	5		T75	85		T71	212
alert[0x2e]	16899	1			T15	6		T16	169		T43	2
alert[0x2f]	8825	1			T73	1		T15	14		T37	70
alert[0x30]	16073	1			T5	1		T16	437		T75	61
alert[0x31]	3273	1			T9	1		T15	78		T71	555
alert[0x32]	4180	1			T9	1		T15	2		T16	10
alert[0x33]	5829	1			T4	392		T15	4		T16	472
alert[0x34]	12884	1			T4	7		T17	2		T9	1
alert[0x35]	8572	1			T9	1		T15	1		T16	2
alert[0x36]	8491	1			T9	1		T15	17		T75	390
alert[0x37]	7101	1			T17	28		T73	2		T14	3
alert[0x38]	8654	1			T4	446		T17	20		T9	1
alert[0x39]	10768	1			T16	2232		T225	1		T78	108
alert[0x3a]	2256	1			T4	14		T5	1		T10	1
alert[0x3b]	3922	1			T4	39		T14	2		T10	1
alert[0x3c]	3849	1			T71	67		T43	10		T25	4
alert[0x3d]	3801	1			T73	1		T15	19		T10	1
alert[0x3e]	4402	1			T4	20		T37	2		T10	1
alert[0x3f]	7590	1			T4	312		T9	1		T15	5
alert[0x40]	3322	1			T17	7		T14	1		T68	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	142361	1			T4	9173		T17	5		T9	2
class_i[0x1]	85338	1			T4	24		T5	19		T9	6
class_i[0x2]	109667	1			T9	1		T73	2		T14	10
class_i[0x3]	81481	1			T4	44		T17	723		T9	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

418162

1

T4

9241

T17

728

T73

72

alert_ping_fail

685

1

T5

19

T9

12

T10

17

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4203	1			T4	1055		T71	22		T78	9
alert_integrity_fail	alert[0x1]	9222	1			T4	127		T17	2		T16	196
alert_integrity_fail	alert[0x2]	5166	1			T17	2		T75	44		T78	175
alert_integrity_fail	alert[0x3]	6549	1			T4	29		T17	19		T16	105
alert_integrity_fail	alert[0x4]	2639	1			T43	21		T25	2		T46	4
alert_integrity_fail	alert[0x5]	4899	1			T17	1		T16	401		T75	75
alert_integrity_fail	alert[0x6]	4940	1			T15	4		T16	30		T71	3
alert_integrity_fail	alert[0x7]	7212	1			T37	1		T75	176		T43	830
alert_integrity_fail	alert[0x8]	2299	1			T16	82		T68	2		T71	19
alert_integrity_fail	alert[0x9]	3463	1			T4	3		T15	21		T16	17
alert_integrity_fail	alert[0xa]	9897	1			T15	3		T75	843		T71	221
alert_integrity_fail	alert[0xb]	9160	1			T73	51		T16	212		T75	81
alert_integrity_fail	alert[0xc]	9133	1			T4	28		T15	16		T71	16
alert_integrity_fail	alert[0xd]	8035	1			T4	2626		T75	16		T71	260
alert_integrity_fail	alert[0xe]	4687	1			T15	6		T37	23		T16	650
alert_integrity_fail	alert[0xf]	5815	1			T4	65		T17	17		T15	16
alert_integrity_fail	alert[0x10]	3070	1			T73	3		T16	43		T43	531
alert_integrity_fail	alert[0x11]	4168	1			T17	43		T16	13		T75	34
alert_integrity_fail	alert[0x12]	4699	1			T73	7		T16	20		T75	17
alert_integrity_fail	alert[0x13]	6302	1			T4	24		T43	13		T79	2
alert_integrity_fail	alert[0x14]	5181	1			T4	146		T15	3		T16	20
alert_integrity_fail	alert[0x15]	6132	1			T4	291		T75	12		T43	62
alert_integrity_fail	alert[0x16]	5322	1			T4	123		T17	13		T14	1
alert_integrity_fail	alert[0x17]	12988	1			T15	2		T37	2		T16	473
alert_integrity_fail	alert[0x18]	6723	1			T15	1		T16	28		T75	323
alert_integrity_fail	alert[0x19]	2403	1			T37	11		T16	372		T71	41
alert_integrity_fail	alert[0x1a]	7242	1			T4	784		T17	525		T15	8
alert_integrity_fail	alert[0x1b]	4956	1			T15	6		T16	14		T75	45
alert_integrity_fail	alert[0x1c]	6897	1			T4	41		T16	275		T70	7
alert_integrity_fail	alert[0x1d]	7866	1			T15	8		T16	4041		T75	12
alert_integrity_fail	alert[0x1e]	4225	1			T4	11		T16	1210		T75	21
alert_integrity_fail	alert[0x1f]	9930	1			T75	1		T43	210		T25	51
alert_integrity_fail	alert[0x20]	4928	1			T4	912		T17	29		T73	7
alert_integrity_fail	alert[0x21]	8336	1			T4	29		T68	36		T75	15
alert_integrity_fail	alert[0x22]	8478	1			T4	312		T17	15		T37	4
alert_integrity_fail	alert[0x23]	4853	1			T4	46		T14	3		T37	1
alert_integrity_fail	alert[0x24]	8388	1			T4	91		T17	1		T78	359
alert_integrity_fail	alert[0x25]	5133	1			T75	183		T71	11		T43	313
alert_integrity_fail	alert[0x26]	2059	1			T4	92		T75	13		T43	468
alert_integrity_fail	alert[0x27]	5311	1			T4	940		T17	4		T37	11
alert_integrity_fail	alert[0x28]	8970	1			T4	177		T37	3		T16	2752
alert_integrity_fail	alert[0x29]	6679	1			T37	4		T71	10		T43	1149
alert_integrity_fail	alert[0x2a]	3228	1			T4	59		T14	7		T37	104
alert_integrity_fail	alert[0x2b]	5456	1			T75	297		T43	625		T62	2
alert_integrity_fail	alert[0x2c]	4775	1			T16	11		T75	226		T71	182
alert_integrity_fail	alert[0x2d]	5626	1			T15	5		T75	85		T71	212
alert_integrity_fail	alert[0x2e]	16889	1			T15	6		T16	169		T43	2
alert_integrity_fail	alert[0x2f]	8818	1			T73	1		T15	14		T37	70
alert_integrity_fail	alert[0x30]	16055	1			T16	437		T75	61		T71	9
alert_integrity_fail	alert[0x31]	3263	1			T15	78		T71	555		T25	1
alert_integrity_fail	alert[0x32]	4169	1			T15	2		T16	10		T75	911
alert_integrity_fail	alert[0x33]	5823	1			T4	392		T15	4		T16	472
alert_integrity_fail	alert[0x34]	12871	1			T4	7		T17	2		T37	33
alert_integrity_fail	alert[0x35]	8563	1			T15	1		T16	2		T75	547
alert_integrity_fail	alert[0x36]	8482	1			T15	17		T75	390		T71	11
alert_integrity_fail	alert[0x37]	7095	1			T17	28		T73	2		T14	3
alert_integrity_fail	alert[0x38]	8649	1			T4	446		T17	20		T16	1353
alert_integrity_fail	alert[0x39]	10762	1			T16	2232		T78	108		T47	1
alert_integrity_fail	alert[0x3a]	2244	1			T4	14		T75	16		T71	137
alert_integrity_fail	alert[0x3b]	3912	1			T4	39		T14	2		T16	17
alert_integrity_fail	alert[0x3c]	3840	1			T71	67		T43	10		T25	4
alert_integrity_fail	alert[0x3d]	3792	1			T73	1		T15	19		T16	58
alert_integrity_fail	alert[0x3e]	4392	1			T4	20		T37	2		T71	68
alert_integrity_fail	alert[0x3f]	7584	1			T4	312		T15	5		T37	3
alert_integrity_fail	alert[0x40]	3316	1			T17	7		T14	1		T68	1
alert_ping_fail	alert[0x0]	9	1			T5	1		T10	1		T221	1
alert_ping_fail	alert[0x1]	9	1			T10	1		T283	1		T284	1
alert_ping_fail	alert[0x2]	10	1			T221	1		T285	1		T286	1
alert_ping_fail	alert[0x3]	10	1			T220	1		T287	2		T288	1
alert_ping_fail	alert[0x4]	14	1			T9	1		T289	1		T290	1
alert_ping_fail	alert[0x5]	15	1			T9	1		T10	1		T91	1
alert_ping_fail	alert[0x6]	15	1			T289	1		T291	1		T292	1
alert_ping_fail	alert[0x7]	18	1			T5	1		T218	3		T290	1
alert_ping_fail	alert[0x8]	24	1			T5	3		T8	1		T225	1
alert_ping_fail	alert[0x9]	11	1			T10	1		T293	1		T294	1
alert_ping_fail	alert[0xa]	12	1			T290	1		T285	1		T259	1
alert_ping_fail	alert[0xb]	5	1			T225	1		T284	1		T286	1
alert_ping_fail	alert[0xc]	11	1			T5	2		T10	1		T293	1
alert_ping_fail	alert[0xd]	9	1			T295	1		T284	1		T288	2
alert_ping_fail	alert[0xe]	10	1			T283	1		T293	1		T288	1
alert_ping_fail	alert[0xf]	8	1			T296	2		T293	1		T297	1
alert_ping_fail	alert[0x10]	10	1			T285	1		T286	3		T298	1
alert_ping_fail	alert[0x11]	6	1			T289	1		T299	1		T300	1
alert_ping_fail	alert[0x12]	10	1			T220	1		T284	2		T288	1
alert_ping_fail	alert[0x13]	19	1			T9	1		T289	2		T223	1
alert_ping_fail	alert[0x14]	15	1			T220	1		T285	1		T301	1
alert_ping_fail	alert[0x15]	16	1			T296	1		T282	1		T285	2
alert_ping_fail	alert[0x16]	8	1			T221	1		T296	2		T287	1
alert_ping_fail	alert[0x17]	6	1			T283	1		T301	1		T302	1
alert_ping_fail	alert[0x18]	9	1			T5	1		T10	2		T296	1
alert_ping_fail	alert[0x19]	11	1			T225	1		T218	1		T296	1
alert_ping_fail	alert[0x1a]	14	1			T218	1		T291	1		T292	1
alert_ping_fail	alert[0x1b]	8	1			T291	1		T296	1		T292	1
alert_ping_fail	alert[0x1c]	16	1			T5	1		T221	1		T282	1
alert_ping_fail	alert[0x1d]	8	1			T284	1		T301	1		T303	1
alert_ping_fail	alert[0x1e]	8	1			T218	1		T292	1		T287	1
alert_ping_fail	alert[0x1f]	15	1			T9	1		T221	1		T296	1
alert_ping_fail	alert[0x20]	8	1			T5	1		T283	1		T287	1
alert_ping_fail	alert[0x21]	14	1			T5	3		T10	1		T225	1
alert_ping_fail	alert[0x22]	11	1			T5	1		T221	1		T286	1
alert_ping_fail	alert[0x23]	12	1			T221	1		T290	1		T283	1
alert_ping_fail	alert[0x24]	10	1			T10	1		T285	1		T286	1
alert_ping_fail	alert[0x25]	9	1			T10	1		T225	1		T292	1
alert_ping_fail	alert[0x26]	7	1			T220	1		T283	1		T294	1
alert_ping_fail	alert[0x27]	7	1			T5	1		T10	1		T304	1
alert_ping_fail	alert[0x28]	11	1			T9	1		T10	1		T225	1
alert_ping_fail	alert[0x29]	6	1			T5	1		T218	1		T285	1
alert_ping_fail	alert[0x2a]	10	1			T10	1		T225	1		T284	1
alert_ping_fail	alert[0x2b]	7	1			T8	2		T221	1		T284	1
alert_ping_fail	alert[0x2c]	14	1			T5	1		T280	1		T299	1
alert_ping_fail	alert[0x2d]	18	1			T220	1		T296	1		T287	1
alert_ping_fail	alert[0x2e]	10	1			T284	1		T305	1		T306	1
alert_ping_fail	alert[0x2f]	7	1			T24	1		T295	1		T296	1
alert_ping_fail	alert[0x30]	18	1			T5	1		T295	1		T28	2
alert_ping_fail	alert[0x31]	10	1			T9	1		T293	1		T301	1
alert_ping_fail	alert[0x32]	11	1			T9	1		T225	1		T290	1
alert_ping_fail	alert[0x33]	6	1			T225	1		T289	1		T301	1
alert_ping_fail	alert[0x34]	13	1			T9	1		T225	1		T218	2
alert_ping_fail	alert[0x35]	9	1			T9	1		T287	1		T293	1
alert_ping_fail	alert[0x36]	9	1			T9	1		T225	1		T283	1
alert_ping_fail	alert[0x37]	6	1			T286	1		T300	1		T294	1
alert_ping_fail	alert[0x38]	5	1			T9	1		T220	1		T293	1
alert_ping_fail	alert[0x39]	6	1			T225	1		T296	1		T301	1
alert_ping_fail	alert[0x3a]	12	1			T5	1		T10	1		T220	1
alert_ping_fail	alert[0x3b]	10	1			T10	1		T291	1		T296	1
alert_ping_fail	alert[0x3c]	9	1			T288	1		T298	1		T307	1
alert_ping_fail	alert[0x3d]	9	1			T10	1		T218	1		T301	1
alert_ping_fail	alert[0x3e]	10	1			T10	1		T289	1		T296	1
alert_ping_fail	alert[0x3f]	6	1			T9	1		T225	1		T283	1
alert_ping_fail	alert[0x40]	6	1			T225	1		T300	2		T308	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	142153	1			T4	9173		T17	5		T14	7
alert_integrity_fail	class_i[0x1]	85197	1			T4	24		T73	9		T16	19922
alert_integrity_fail	class_i[0x2]	109543	1			T73	2		T14	10		T70	4
alert_integrity_fail	class_i[0x3]	81269	1			T4	44		T17	723		T73	61
alert_ping_fail	class_i[0x0]	208	1			T9	2		T225	2		T290	9
alert_ping_fail	class_i[0x1]	141	1			T5	19		T9	6		T10	2
alert_ping_fail	class_i[0x2]	124	1			T9	1		T10	1		T225	1
alert_ping_fail	class_i[0x3]	212	1			T9	3		T10	14		T225	5