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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.62 100.00 100.00 100.00 99.38 99.56


Total test records in report: 824
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T141 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.970797755 May 14 01:30:07 PM PDT 24 May 14 01:47:36 PM PDT 24 24557151469 ps
T771 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3924968450 May 14 01:30:30 PM PDT 24 May 14 01:30:34 PM PDT 24 16175558 ps
T772 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1940692846 May 14 01:30:29 PM PDT 24 May 14 01:30:33 PM PDT 24 10846076 ps
T773 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3482473264 May 14 01:30:25 PM PDT 24 May 14 01:30:40 PM PDT 24 637404868 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2743329728 May 14 01:30:01 PM PDT 24 May 14 01:30:24 PM PDT 24 961812651 ps
T775 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.622277217 May 14 01:30:20 PM PDT 24 May 14 01:30:26 PM PDT 24 222241080 ps
T776 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2250147684 May 14 01:30:24 PM PDT 24 May 14 01:30:36 PM PDT 24 576568923 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.877925782 May 14 01:30:07 PM PDT 24 May 14 01:30:16 PM PDT 24 53206089 ps
T778 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3083480756 May 14 01:30:07 PM PDT 24 May 14 01:30:19 PM PDT 24 237365750 ps
T779 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2181301341 May 14 01:30:09 PM PDT 24 May 14 01:30:32 PM PDT 24 791543265 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1752221568 May 14 01:30:10 PM PDT 24 May 14 01:30:15 PM PDT 24 8085722 ps
T781 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3497702019 May 14 01:30:22 PM PDT 24 May 14 01:30:42 PM PDT 24 187174703 ps
T782 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1420556314 May 14 01:30:30 PM PDT 24 May 14 01:30:34 PM PDT 24 78933205 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.442201668 May 14 01:29:59 PM PDT 24 May 14 01:34:59 PM PDT 24 4236558239 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.899844989 May 14 01:30:07 PM PDT 24 May 14 01:33:46 PM PDT 24 25914844373 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1242993287 May 14 01:30:01 PM PDT 24 May 14 01:31:53 PM PDT 24 11352256347 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3151500925 May 14 01:30:09 PM PDT 24 May 14 01:30:38 PM PDT 24 763697608 ps
T787 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2364370544 May 14 01:29:58 PM PDT 24 May 14 01:30:01 PM PDT 24 9363976 ps
T138 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1505189948 May 14 01:30:09 PM PDT 24 May 14 01:40:12 PM PDT 24 23336085384 ps
T162 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4074154415 May 14 01:30:07 PM PDT 24 May 14 01:30:13 PM PDT 24 115698758 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2402541063 May 14 01:30:12 PM PDT 24 May 14 01:30:17 PM PDT 24 11297113 ps
T161 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2210338172 May 14 01:30:02 PM PDT 24 May 14 01:30:09 PM PDT 24 105106006 ps
T789 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3412291301 May 14 01:30:34 PM PDT 24 May 14 01:30:38 PM PDT 24 15953723 ps
T173 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2911102959 May 14 01:30:09 PM PDT 24 May 14 01:30:17 PM PDT 24 182115986 ps
T144 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4203314775 May 14 01:30:23 PM PDT 24 May 14 01:40:47 PM PDT 24 4475819072 ps
T790 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3608695343 May 14 01:30:30 PM PDT 24 May 14 01:30:34 PM PDT 24 8927839 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1960836130 May 14 01:30:09 PM PDT 24 May 14 01:30:18 PM PDT 24 215996092 ps
T792 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4127850479 May 14 01:30:28 PM PDT 24 May 14 01:30:43 PM PDT 24 900897362 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1510867108 May 14 01:30:24 PM PDT 24 May 14 01:30:38 PM PDT 24 259261933 ps
T145 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3723552570 May 14 01:30:25 PM PDT 24 May 14 01:34:04 PM PDT 24 6224796461 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2986263220 May 14 01:30:22 PM PDT 24 May 14 01:30:27 PM PDT 24 13905815 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4059445382 May 14 01:30:28 PM PDT 24 May 14 01:30:36 PM PDT 24 273865584 ps
T796 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3313289263 May 14 01:30:21 PM PDT 24 May 14 01:30:23 PM PDT 24 11379991 ps
T142 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.106016727 May 14 01:30:08 PM PDT 24 May 14 01:39:27 PM PDT 24 15378226977 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3533569910 May 14 01:30:09 PM PDT 24 May 14 01:30:22 PM PDT 24 200210539 ps
T798 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.221304481 May 14 01:30:23 PM PDT 24 May 14 01:30:53 PM PDT 24 181741767 ps
T149 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1904108970 May 14 01:30:08 PM PDT 24 May 14 01:38:31 PM PDT 24 12475619996 ps
T139 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4222555208 May 14 01:30:23 PM PDT 24 May 14 01:32:52 PM PDT 24 4000707122 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.527280318 May 14 01:30:02 PM PDT 24 May 14 01:30:12 PM PDT 24 855988295 ps
T151 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1396591929 May 14 01:30:07 PM PDT 24 May 14 01:42:28 PM PDT 24 9710975842 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3069102042 May 14 01:29:59 PM PDT 24 May 14 01:30:07 PM PDT 24 135736042 ps
T165 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3171279131 May 14 01:30:08 PM PDT 24 May 14 01:30:53 PM PDT 24 2642956932 ps
T261 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2395430537 May 14 01:30:01 PM PDT 24 May 14 01:30:27 PM PDT 24 320978847 ps
T801 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.857041255 May 14 01:30:31 PM PDT 24 May 14 01:30:35 PM PDT 24 8730773 ps
T137 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.579282453 May 14 01:30:22 PM PDT 24 May 14 01:45:42 PM PDT 24 12866923115 ps
T802 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1816691495 May 14 01:30:09 PM PDT 24 May 14 01:30:18 PM PDT 24 191365752 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1187410933 May 14 01:30:21 PM PDT 24 May 14 01:30:36 PM PDT 24 216886105 ps
T804 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.20047607 May 14 01:30:23 PM PDT 24 May 14 01:30:35 PM PDT 24 127134603 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4028524395 May 14 01:30:22 PM PDT 24 May 14 01:30:46 PM PDT 24 177548493 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4005278673 May 14 01:30:00 PM PDT 24 May 14 01:34:56 PM PDT 24 4501073098 ps
T159 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2803178055 May 14 01:30:22 PM PDT 24 May 14 01:31:08 PM PDT 24 579084640 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3154164475 May 14 01:30:09 PM PDT 24 May 14 01:30:18 PM PDT 24 236305088 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.632902211 May 14 01:30:26 PM PDT 24 May 14 01:30:33 PM PDT 24 66773539 ps
T140 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3840440949 May 14 01:30:23 PM PDT 24 May 14 01:36:14 PM PDT 24 18700596865 ps
T170 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.72562578 May 14 01:30:06 PM PDT 24 May 14 01:30:11 PM PDT 24 51727055 ps
T809 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1579617884 May 14 01:30:11 PM PDT 24 May 14 01:30:19 PM PDT 24 24704229 ps
T810 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2570417594 May 14 01:30:10 PM PDT 24 May 14 01:30:24 PM PDT 24 133965154 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.202394278 May 14 01:30:02 PM PDT 24 May 14 01:31:50 PM PDT 24 837955729 ps
T132 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1164097224 May 14 01:29:51 PM PDT 24 May 14 01:40:20 PM PDT 24 17148098303 ps
T167 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2449931821 May 14 01:29:59 PM PDT 24 May 14 01:31:11 PM PDT 24 1548032422 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3592405705 May 14 01:30:01 PM PDT 24 May 14 01:35:30 PM PDT 24 4383753729 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3206450894 May 14 01:30:08 PM PDT 24 May 14 01:32:27 PM PDT 24 2155404132 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.302846375 May 14 01:30:10 PM PDT 24 May 14 01:30:18 PM PDT 24 64339367 ps
T815 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1220317994 May 14 01:30:28 PM PDT 24 May 14 01:30:31 PM PDT 24 14887242 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3472787087 May 14 01:30:22 PM PDT 24 May 14 01:30:28 PM PDT 24 23081933 ps
T817 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3303634336 May 14 01:30:13 PM PDT 24 May 14 01:30:35 PM PDT 24 511033248 ps
T818 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3429350788 May 14 01:30:23 PM PDT 24 May 14 01:31:07 PM PDT 24 1321049413 ps
T819 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3477180436 May 14 01:30:31 PM PDT 24 May 14 01:30:35 PM PDT 24 19841222 ps
T820 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1134510251 May 14 01:30:10 PM PDT 24 May 14 01:30:19 PM PDT 24 55316693 ps
T821 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3123713275 May 14 01:30:10 PM PDT 24 May 14 01:30:17 PM PDT 24 34679867 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3028736271 May 14 01:30:11 PM PDT 24 May 14 01:30:18 PM PDT 24 20708241 ps
T823 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.132464675 May 14 01:30:34 PM PDT 24 May 14 01:30:38 PM PDT 24 15918576 ps
T824 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4094306118 May 14 01:29:58 PM PDT 24 May 14 01:30:43 PM PDT 24 1261593361 ps
T148 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3279380447 May 14 01:30:08 PM PDT 24 May 14 01:31:46 PM PDT 24 3105976163 ps

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2216637109
Short name T17
Test name
Test status
Simulation time 230119048824 ps
CPU time 3733.98 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 02:34:05 PM PDT 24
Peak memory 305476 kb
Host smart-d113fe2a-c071-49f3-88aa-5be7f0422ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216637109 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2216637109
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.920211798
Short name T4
Test name
Test status
Simulation time 279045368777 ps
CPU time 3429.13 seconds
Started May 14 01:32:25 PM PDT 24
Finished May 14 02:29:35 PM PDT 24
Peak memory 289736 kb
Host smart-8b02f8a2-8f5f-41ce-b26d-49989a152b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920211798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.920211798
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1269748029
Short name T11
Test name
Test status
Simulation time 244181769 ps
CPU time 13.51 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:01 PM PDT 24
Peak memory 271440 kb
Host smart-02117cd5-a503-4367-a72c-2757a28312b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1269748029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1269748029
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1243842973
Short name T15
Test name
Test status
Simulation time 264801781296 ps
CPU time 5460.5 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 03:02:21 PM PDT 24
Peak memory 322640 kb
Host smart-b9bb0724-ea60-47ce-a023-3920a4d503d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243842973 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1243842973
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4052460488
Short name T154
Test name
Test status
Simulation time 1239989359 ps
CPU time 41.15 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:56 PM PDT 24
Peak memory 236640 kb
Host smart-0b55a564-3390-4b1f-9ba0-7251c03bce4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4052460488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4052460488
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1415214922
Short name T43
Test name
Test status
Simulation time 39106287137 ps
CPU time 4941.72 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 02:54:37 PM PDT 24
Peak memory 334060 kb
Host smart-b1105afe-c93c-4e82-af6b-7dbafd581ab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415214922 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1415214922
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1652823906
Short name T24
Test name
Test status
Simulation time 90585161520 ps
CPU time 2469.38 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 02:13:58 PM PDT 24
Peak memory 285960 kb
Host smart-a5707bc1-56b8-4b2d-88c8-65c4c34b4f01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652823906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1652823906
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.533923740
Short name T49
Test name
Test status
Simulation time 41997112781 ps
CPU time 3287.21 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 02:25:27 PM PDT 24
Peak memory 298136 kb
Host smart-250bf4ec-eff0-444a-972d-7efbf3c9bc3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533923740 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.533923740
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2037857056
Short name T129
Test name
Test status
Simulation time 4538421193 ps
CPU time 700.61 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:42:04 PM PDT 24
Peak memory 272684 kb
Host smart-5c71e5c2-45f0-4cc9-a306-5abc62a9314f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037857056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2037857056
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1949037627
Short name T18
Test name
Test status
Simulation time 9325165212 ps
CPU time 520.09 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:40:56 PM PDT 24
Peak memory 256980 kb
Host smart-199ba68d-4721-494c-ae43-cefc1b7f2cc0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949037627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1949037627
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.333311417
Short name T113
Test name
Test status
Simulation time 17445021880 ps
CPU time 304.48 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:35:29 PM PDT 24
Peak memory 271264 kb
Host smart-4053c88f-2812-4f09-bdd7-5203dc588509
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=333311417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.333311417
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1889249495
Short name T6
Test name
Test status
Simulation time 1495897585 ps
CPU time 18.51 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:26 PM PDT 24
Peak memory 240468 kb
Host smart-4be81c66-4c78-4bba-a0eb-386b83cfdbe3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1889249495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1889249495
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2571487381
Short name T134
Test name
Test status
Simulation time 17655775753 ps
CPU time 1172.63 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:49:47 PM PDT 24
Peak memory 265256 kb
Host smart-5cada4ac-d6c0-45f3-8c25-91165bba1b0e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571487381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2571487381
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1267721114
Short name T87
Test name
Test status
Simulation time 32544183629 ps
CPU time 1389.91 seconds
Started May 14 01:31:23 PM PDT 24
Finished May 14 01:54:34 PM PDT 24
Peak memory 285680 kb
Host smart-b3c85af0-cba0-4a4c-a774-e9d1b30b7f03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267721114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1267721114
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3171184409
Short name T118
Test name
Test status
Simulation time 17350451741 ps
CPU time 1161.12 seconds
Started May 14 01:30:14 PM PDT 24
Finished May 14 01:49:37 PM PDT 24
Peak memory 265032 kb
Host smart-4da9c6d4-b4a5-43d6-b20e-732031ca4d11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171184409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3171184409
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.62337624
Short name T281
Test name
Test status
Simulation time 57828353153 ps
CPU time 3427.18 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 02:30:14 PM PDT 24
Peak memory 288976 kb
Host smart-b6ac6a1b-64e9-4717-9471-68feb09d7245
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62337624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.62337624
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3426461326
Short name T232
Test name
Test status
Simulation time 19222355 ps
CPU time 1.48 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 236544 kb
Host smart-4e621223-55e5-4a99-a0f4-4c1759548b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3426461326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3426461326
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2570286272
Short name T10
Test name
Test status
Simulation time 13937620382 ps
CPU time 486.94 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:40:54 PM PDT 24
Peak memory 247104 kb
Host smart-95527949-44d7-4bc0-9eef-578ef88ccb33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570286272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2570286272
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3723552570
Short name T145
Test name
Test status
Simulation time 6224796461 ps
CPU time 216.49 seconds
Started May 14 01:30:25 PM PDT 24
Finished May 14 01:34:04 PM PDT 24
Peak memory 272464 kb
Host smart-70718803-5c9c-43a0-8063-5b9331302f7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3723552570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3723552570
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4203314775
Short name T144
Test name
Test status
Simulation time 4475819072 ps
CPU time 620.9 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:40:47 PM PDT 24
Peak memory 272744 kb
Host smart-628ac41a-2273-4705-bcdf-07ae1b68f912
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203314775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4203314775
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2902599852
Short name T91
Test name
Test status
Simulation time 100180567644 ps
CPU time 2656.97 seconds
Started May 14 01:33:35 PM PDT 24
Finished May 14 02:17:54 PM PDT 24
Peak memory 289200 kb
Host smart-1a7db812-dbd5-4cbc-9bd3-9510fa6d7f8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902599852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2902599852
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1390807829
Short name T287
Test name
Test status
Simulation time 42144338628 ps
CPU time 452.58 seconds
Started May 14 01:31:22 PM PDT 24
Finished May 14 01:38:56 PM PDT 24
Peak memory 247984 kb
Host smart-81f65066-885e-42fb-8bf5-bf26a0edf058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390807829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1390807829
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2151965276
Short name T120
Test name
Test status
Simulation time 103251552384 ps
CPU time 389.18 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:36:39 PM PDT 24
Peak memory 273240 kb
Host smart-d4f78d01-e9e1-472a-af4d-e21c6fd6cd47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2151965276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2151965276
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3479147776
Short name T305
Test name
Test status
Simulation time 31087139555 ps
CPU time 528.14 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 247992 kb
Host smart-894640c5-9bd2-40a0-889b-4cf56e00b6dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479147776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3479147776
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.475610485
Short name T279
Test name
Test status
Simulation time 199947385971 ps
CPU time 2473.5 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 02:12:33 PM PDT 24
Peak memory 289380 kb
Host smart-7ea4666a-15e1-4ec9-920c-9cd2468bad85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475610485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.475610485
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.998656033
Short name T50
Test name
Test status
Simulation time 26643577090 ps
CPU time 1075.13 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:49:54 PM PDT 24
Peak memory 289244 kb
Host smart-94be0483-a61b-4293-b446-dc8e32bede59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998656033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.998656033
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3321724350
Short name T294
Test name
Test status
Simulation time 13354915334 ps
CPU time 530.34 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 01:40:25 PM PDT 24
Peak memory 254924 kb
Host smart-55d42de5-985e-4ace-83f3-14d2b7c1cfdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321724350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3321724350
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4000467613
Short name T71
Test name
Test status
Simulation time 105614616801 ps
CPU time 1803.64 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 02:00:44 PM PDT 24
Peak memory 271608 kb
Host smart-f53a0476-20f1-4768-b4b3-6882a6c24599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000467613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4000467613
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3518853029
Short name T115
Test name
Test status
Simulation time 8444403827 ps
CPU time 596.08 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:39:58 PM PDT 24
Peak memory 268516 kb
Host smart-984b3d9d-0e85-446a-b491-fe953d0486b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518853029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3518853029
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.6386115
Short name T259
Test name
Test status
Simulation time 129056249831 ps
CPU time 2092.84 seconds
Started May 14 01:32:06 PM PDT 24
Finished May 14 02:07:00 PM PDT 24
Peak memory 272932 kb
Host smart-a8a1fad2-cee2-46e1-8a7d-4647d8012dc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6386115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.6386115
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1164097224
Short name T132
Test name
Test status
Simulation time 17148098303 ps
CPU time 627.83 seconds
Started May 14 01:29:51 PM PDT 24
Finished May 14 01:40:20 PM PDT 24
Peak memory 272044 kb
Host smart-4b171bf7-002b-4a8b-bbf6-9f957b6305af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164097224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1164097224
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3705635310
Short name T233
Test name
Test status
Simulation time 92151014 ps
CPU time 1.55 seconds
Started May 14 01:30:29 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 236540 kb
Host smart-69b35dde-912a-40ad-8030-b1fd2336cf96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3705635310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3705635310
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.418104618
Short name T284
Test name
Test status
Simulation time 159893805595 ps
CPU time 565.91 seconds
Started May 14 01:31:54 PM PDT 24
Finished May 14 01:41:21 PM PDT 24
Peak memory 248344 kb
Host smart-68775507-e3cd-4637-b53a-20e0d837a3c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418104618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.418104618
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3285425839
Short name T317
Test name
Test status
Simulation time 64503083554 ps
CPU time 1884.11 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 02:03:38 PM PDT 24
Peak memory 273388 kb
Host smart-c02130fc-431e-4da7-8d08-ea336ef5d8c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285425839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3285425839
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2687948408
Short name T130
Test name
Test status
Simulation time 1578449187 ps
CPU time 206.21 seconds
Started May 14 01:30:20 PM PDT 24
Finished May 14 01:33:48 PM PDT 24
Peak memory 270540 kb
Host smart-280d80b9-11f5-45d0-b3ab-cbdd31ad3e1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2687948408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2687948408
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2545651695
Short name T166
Test name
Test status
Simulation time 760040762 ps
CPU time 21.71 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 244616 kb
Host smart-b670df2e-4dba-4851-b9ec-c5b8e819ab80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2545651695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2545651695
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3695284365
Short name T27
Test name
Test status
Simulation time 297709005 ps
CPU time 13.22 seconds
Started May 14 01:30:35 PM PDT 24
Finished May 14 01:30:50 PM PDT 24
Peak memory 266928 kb
Host smart-4945e675-2e34-489b-a803-97c5593a60f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3695284365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3695284365
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2804508988
Short name T83
Test name
Test status
Simulation time 58177441429 ps
CPU time 3123.73 seconds
Started May 14 01:31:20 PM PDT 24
Finished May 14 02:23:25 PM PDT 24
Peak memory 297924 kb
Host smart-6a668c3f-8a70-43ae-ba55-f3980fe8a953
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804508988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2804508988
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3037210074
Short name T245
Test name
Test status
Simulation time 77879143375 ps
CPU time 974.19 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 01:46:54 PM PDT 24
Peak memory 289736 kb
Host smart-587fd182-a573-4b3a-9323-a049055eddb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037210074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3037210074
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2016424640
Short name T84
Test name
Test status
Simulation time 97901905961 ps
CPU time 2189.72 seconds
Started May 14 01:30:42 PM PDT 24
Finished May 14 02:07:13 PM PDT 24
Peak memory 322660 kb
Host smart-f81f2857-93fa-4a08-ab0e-715857e25ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016424640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2016424640
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3161686309
Short name T308
Test name
Test status
Simulation time 23881876997 ps
CPU time 512.11 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:41:11 PM PDT 24
Peak memory 248260 kb
Host smart-2f5648ca-9299-4412-b158-a8f9e330c099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161686309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3161686309
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2528060866
Short name T311
Test name
Test status
Simulation time 51975563207 ps
CPU time 3013.64 seconds
Started May 14 01:33:20 PM PDT 24
Finished May 14 02:23:35 PM PDT 24
Peak memory 288956 kb
Host smart-525854ed-d330-4651-8ce4-85d496337189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528060866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2528060866
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3254043624
Short name T107
Test name
Test status
Simulation time 53832993397 ps
CPU time 1484.38 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:55:50 PM PDT 24
Peak memory 285276 kb
Host smart-1484e24f-cd81-4a1b-a9a1-c87841cf2a60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254043624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3254043624
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2715671112
Short name T106
Test name
Test status
Simulation time 451312915 ps
CPU time 27.98 seconds
Started May 14 01:31:09 PM PDT 24
Finished May 14 01:31:39 PM PDT 24
Peak memory 255540 kb
Host smart-770c6490-db80-4276-9984-aa3ce4b4db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27156
71112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2715671112
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1905117166
Short name T117
Test name
Test status
Simulation time 1177707339 ps
CPU time 108.09 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:31:49 PM PDT 24
Peak memory 264984 kb
Host smart-b04654a4-1b66-44bb-9ca8-a0fec4869ed8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1905117166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1905117166
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.579282453
Short name T137
Test name
Test status
Simulation time 12866923115 ps
CPU time 916.19 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:45:42 PM PDT 24
Peak memory 266032 kb
Host smart-4758b2ca-c5c7-4b74-b4ac-c603b09ac558
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579282453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.579282453
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2988345999
Short name T301
Test name
Test status
Simulation time 69981107691 ps
CPU time 302.81 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:36:10 PM PDT 24
Peak memory 248016 kb
Host smart-cbb7e67b-56ac-40b7-8645-d6ec94eb9612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988345999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2988345999
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1338810841
Short name T244
Test name
Test status
Simulation time 7605860788 ps
CPU time 804.18 seconds
Started May 14 01:33:37 PM PDT 24
Finished May 14 01:47:02 PM PDT 24
Peak memory 273120 kb
Host smart-3e7ff0d9-cbb4-4cb9-bf95-8ee6718893fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338810841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1338810841
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2210338172
Short name T161
Test name
Test status
Simulation time 105106006 ps
CPU time 6.07 seconds
Started May 14 01:30:02 PM PDT 24
Finished May 14 01:30:09 PM PDT 24
Peak memory 236576 kb
Host smart-b6d0e300-12fb-4562-a23a-6f8f8bb0a868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2210338172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2210338172
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3297954172
Short name T193
Test name
Test status
Simulation time 24236269 ps
CPU time 2.73 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 01:30:43 PM PDT 24
Peak memory 248840 kb
Host smart-bc3c787e-97d9-468c-80ed-73f8ff971d38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3297954172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3297954172
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.554662958
Short name T208
Test name
Test status
Simulation time 143977557 ps
CPU time 3.13 seconds
Started May 14 01:30:35 PM PDT 24
Finished May 14 01:30:40 PM PDT 24
Peak memory 248880 kb
Host smart-0d96a3a0-0238-4314-9437-1a15f47404a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=554662958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.554662958
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3527405229
Short name T202
Test name
Test status
Simulation time 53547826 ps
CPU time 3.18 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:31:15 PM PDT 24
Peak memory 248916 kb
Host smart-1f9800a3-c462-4257-aecc-2a44783a2fd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3527405229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3527405229
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3265198015
Short name T203
Test name
Test status
Simulation time 185427802 ps
CPU time 2.98 seconds
Started May 14 01:31:19 PM PDT 24
Finished May 14 01:31:23 PM PDT 24
Peak memory 248880 kb
Host smart-9764cdba-18ec-4985-bbd2-7b278e538fce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3265198015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3265198015
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1769839182
Short name T121
Test name
Test status
Simulation time 9651788325 ps
CPU time 178.1 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:32:59 PM PDT 24
Peak memory 264980 kb
Host smart-51d122e4-28a4-4a2c-b4e5-3e41888c6a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769839182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1769839182
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3180471065
Short name T254
Test name
Test status
Simulation time 236983445 ps
CPU time 26.66 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:34 PM PDT 24
Peak memory 248644 kb
Host smart-663ec68e-f9cf-4fa1-91c6-8573b5c9f3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31804
71065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3180471065
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2303300529
Short name T266
Test name
Test status
Simulation time 253119158247 ps
CPU time 8367.65 seconds
Started May 14 01:32:06 PM PDT 24
Finished May 14 03:51:35 PM PDT 24
Peak memory 371480 kb
Host smart-05cd9ff9-fa22-484f-81bf-0762e35fb9e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303300529 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2303300529
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1109662403
Short name T51
Test name
Test status
Simulation time 131544892177 ps
CPU time 5283.97 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 03:00:18 PM PDT 24
Peak memory 306220 kb
Host smart-b053fc55-af77-4cf5-9f53-69b285427cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109662403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1109662403
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3188435213
Short name T315
Test name
Test status
Simulation time 29039251254 ps
CPU time 1678.12 seconds
Started May 14 01:32:14 PM PDT 24
Finished May 14 02:00:14 PM PDT 24
Peak memory 272760 kb
Host smart-c961c770-876c-4cc4-b060-574073a9c069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188435213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3188435213
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.341885361
Short name T296
Test name
Test status
Simulation time 42851328219 ps
CPU time 460.78 seconds
Started May 14 01:30:48 PM PDT 24
Finished May 14 01:38:31 PM PDT 24
Peak memory 248260 kb
Host smart-c086b181-3c18-4431-b911-fc829c452120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341885361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.341885361
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1669597756
Short name T88
Test name
Test status
Simulation time 3380447575 ps
CPU time 26.79 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:31:07 PM PDT 24
Peak memory 256156 kb
Host smart-66b577fb-916b-4153-bdf1-6ffd0d231a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16695
97756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1669597756
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1430493009
Short name T158
Test name
Test status
Simulation time 166205447 ps
CPU time 21.19 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:47 PM PDT 24
Peak memory 240044 kb
Host smart-da59dab9-ba64-4acd-982a-5b2c6970c94c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1430493009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1430493009
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1623436683
Short name T23
Test name
Test status
Simulation time 5268277926 ps
CPU time 34.2 seconds
Started May 14 01:31:45 PM PDT 24
Finished May 14 01:32:21 PM PDT 24
Peak memory 247712 kb
Host smart-d009f185-d943-4c8f-8140-f137b4a05f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16234
36683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1623436683
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.579270439
Short name T128
Test name
Test status
Simulation time 2210564617 ps
CPU time 281.09 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:35:05 PM PDT 24
Peak memory 265180 kb
Host smart-3013be49-6f23-4e44-93c7-dbfebf8f46ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579270439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.579270439
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2506741533
Short name T725
Test name
Test status
Simulation time 13742843 ps
CPU time 1.71 seconds
Started May 14 01:30:13 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236500 kb
Host smart-ff9703e2-5d13-41a8-93a6-2dd59f92147d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2506741533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2506741533
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1390711238
Short name T691
Test name
Test status
Simulation time 91752847841 ps
CPU time 4535.06 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 02:46:12 PM PDT 24
Peak memory 305616 kb
Host smart-c54624f3-2104-42f7-ba6b-1c08e96df3f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390711238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1390711238
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2816206264
Short name T185
Test name
Test status
Simulation time 57320493912 ps
CPU time 2551.97 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 02:13:44 PM PDT 24
Peak memory 305472 kb
Host smart-b031bdf8-9475-43f8-b062-2a9286452fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816206264 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2816206264
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2786291710
Short name T276
Test name
Test status
Simulation time 47493765093 ps
CPU time 988.68 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:47:33 PM PDT 24
Peak memory 265208 kb
Host smart-ae93a141-ae52-4404-b330-3efe1209abb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786291710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2786291710
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1095923043
Short name T98
Test name
Test status
Simulation time 38331323270 ps
CPU time 4024.59 seconds
Started May 14 01:31:42 PM PDT 24
Finished May 14 02:38:48 PM PDT 24
Peak memory 339024 kb
Host smart-fb04f2ae-3dbe-4fbc-8e1a-9e9cf24f3c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095923043 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1095923043
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.44689130
Short name T96
Test name
Test status
Simulation time 510972191255 ps
CPU time 9972.47 seconds
Started May 14 01:31:44 PM PDT 24
Finished May 14 04:18:00 PM PDT 24
Peak memory 338416 kb
Host smart-b7131175-40c3-41b4-96ae-ed33ccc65ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44689130 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.44689130
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3267093262
Short name T226
Test name
Test status
Simulation time 62085638496 ps
CPU time 3777.37 seconds
Started May 14 01:31:42 PM PDT 24
Finished May 14 02:34:41 PM PDT 24
Peak memory 298004 kb
Host smart-c4bf74bf-442e-4c23-9c4b-f98a5892a845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267093262 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3267093262
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1379257356
Short name T25
Test name
Test status
Simulation time 146186592029 ps
CPU time 2464.49 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 02:13:04 PM PDT 24
Peak memory 301268 kb
Host smart-db5f4dad-8cfe-4b70-a375-c84f6405d5ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379257356 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1379257356
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4174137084
Short name T68
Test name
Test status
Simulation time 3590170254 ps
CPU time 57.78 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:33:36 PM PDT 24
Peak memory 255604 kb
Host smart-f91048e3-1f31-45c5-a6e0-e93449b1ae80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41741
37084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4174137084
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1135084695
Short name T56
Test name
Test status
Simulation time 704221340 ps
CPU time 44.8 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:31:25 PM PDT 24
Peak memory 248720 kb
Host smart-f0f9df31-57e1-4730-ba1a-1c3c18640e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11350
84695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1135084695
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1965342725
Short name T268
Test name
Test status
Simulation time 4045858312 ps
CPU time 59.29 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 01:33:56 PM PDT 24
Peak memory 256824 kb
Host smart-24c41c3e-1d2c-4df8-ba03-9b579c7976af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
42725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1965342725
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3471605603
Short name T234
Test name
Test status
Simulation time 442664218403 ps
CPU time 7261.3 seconds
Started May 14 01:33:04 PM PDT 24
Finished May 14 03:34:08 PM PDT 24
Peak memory 371084 kb
Host smart-a6be8745-f4a9-4788-9043-2490215ad70b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471605603 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3471605603
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3438592498
Short name T265
Test name
Test status
Simulation time 47719100338 ps
CPU time 2665.33 seconds
Started May 14 01:33:30 PM PDT 24
Finished May 14 02:17:56 PM PDT 24
Peak memory 287196 kb
Host smart-ef47a631-73d6-4e3b-9850-eca0b7b58b37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438592498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3438592498
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3340794791
Short name T262
Test name
Test status
Simulation time 576006938 ps
CPU time 37.66 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 248756 kb
Host smart-cbfdb5f2-80c7-4763-a6f0-211444e540cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
94791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3340794791
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1290742075
Short name T239
Test name
Test status
Simulation time 1103461180 ps
CPU time 51.73 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:49 PM PDT 24
Peak memory 256916 kb
Host smart-1d7293b1-9ee5-410a-ba33-668b74573d83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290742075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1290742075
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2803178055
Short name T159
Test name
Test status
Simulation time 579084640 ps
CPU time 43.55 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:31:08 PM PDT 24
Peak memory 244788 kb
Host smart-c75766fe-ecd6-4952-a970-28dc6ba666d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2803178055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2803178055
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1396591929
Short name T151
Test name
Test status
Simulation time 9710975842 ps
CPU time 737.67 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:42:28 PM PDT 24
Peak memory 273212 kb
Host smart-8ee84754-7fe6-4f4c-b025-87d19935d78a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396591929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1396591929
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2411055223
Short name T153
Test name
Test status
Simulation time 72244844 ps
CPU time 4.69 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:20 PM PDT 24
Peak memory 236512 kb
Host smart-d2d9fb80-4176-4c0c-8f00-233f0067b22f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2411055223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2411055223
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1547337288
Short name T125
Test name
Test status
Simulation time 8421738598 ps
CPU time 679.45 seconds
Started May 14 01:30:19 PM PDT 24
Finished May 14 01:41:40 PM PDT 24
Peak memory 266080 kb
Host smart-8788a763-5e11-4076-ac17-03fe0be32055
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547337288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1547337288
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2527245619
Short name T164
Test name
Test status
Simulation time 1284824033 ps
CPU time 78.35 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:31:42 PM PDT 24
Peak memory 239400 kb
Host smart-ad1871bd-9aac-4011-a2f2-5ea339285f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2527245619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2527245619
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1550236167
Short name T169
Test name
Test status
Simulation time 422845666 ps
CPU time 23.1 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 244864 kb
Host smart-25f047af-a34a-4608-bfa3-bf3e92fc9667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1550236167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1550236167
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2803325656
Short name T124
Test name
Test status
Simulation time 22671450764 ps
CPU time 210.56 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:33:45 PM PDT 24
Peak memory 265044 kb
Host smart-5b85929f-085b-4a71-acd9-ce73872c7cfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2803325656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2803325656
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3173741582
Short name T133
Test name
Test status
Simulation time 4193867719 ps
CPU time 662.16 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:41:28 PM PDT 24
Peak memory 265008 kb
Host smart-13b1294d-1a76-4b8d-af2f-8279202a8185
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173741582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3173741582
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.561777531
Short name T163
Test name
Test status
Simulation time 67835906 ps
CPU time 4.07 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:29 PM PDT 24
Peak memory 235484 kb
Host smart-c03813c1-3e0d-4c6e-936d-d2aab013da12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=561777531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.561777531
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1068995913
Short name T127
Test name
Test status
Simulation time 4064594571 ps
CPU time 156.2 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:32:50 PM PDT 24
Peak memory 265080 kb
Host smart-c6e92694-01ce-49cf-ac55-c83e0233bb46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1068995913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1068995913
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4074154415
Short name T162
Test name
Test status
Simulation time 115698758 ps
CPU time 2.92 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:13 PM PDT 24
Peak memory 235588 kb
Host smart-e8f018c9-2aed-4131-b931-824524c4f59a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4074154415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4074154415
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2449931821
Short name T167
Test name
Test status
Simulation time 1548032422 ps
CPU time 70.65 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:31:11 PM PDT 24
Peak memory 240012 kb
Host smart-0a81b765-16d1-4922-9d30-51bc3bfac6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2449931821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2449931821
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.11980161
Short name T168
Test name
Test status
Simulation time 35252462 ps
CPU time 2.37 seconds
Started May 14 01:30:26 PM PDT 24
Finished May 14 01:30:30 PM PDT 24
Peak memory 236592 kb
Host smart-d4aa16ba-1c96-47e4-9a9d-88d64150fee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=11980161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.11980161
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.734780211
Short name T160
Test name
Test status
Simulation time 28797170 ps
CPU time 2.47 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:25 PM PDT 24
Peak memory 236732 kb
Host smart-453f2597-931b-410e-a1da-acd94fff3a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=734780211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.734780211
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.72562578
Short name T170
Test name
Test status
Simulation time 51727055 ps
CPU time 2.36 seconds
Started May 14 01:30:06 PM PDT 24
Finished May 14 01:30:11 PM PDT 24
Peak memory 235536 kb
Host smart-1d494849-ff80-40ad-9f86-90df023b2a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=72562578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.72562578
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3171279131
Short name T165
Test name
Test status
Simulation time 2642956932 ps
CPU time 41.9 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:53 PM PDT 24
Peak memory 240124 kb
Host smart-76fed410-fda5-45bb-8654-489bc07a799e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3171279131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3171279131
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2911102959
Short name T173
Test name
Test status
Simulation time 182115986 ps
CPU time 3.83 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236488 kb
Host smart-844f5415-adb4-4716-8b1b-d9e07eee94c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2911102959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2911102959
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2760547418
Short name T22
Test name
Test status
Simulation time 54653421225 ps
CPU time 1669.13 seconds
Started May 14 01:31:02 PM PDT 24
Finished May 14 01:58:52 PM PDT 24
Peak memory 289400 kb
Host smart-032fdfbd-2c95-4cbb-b8f4-a52626e05ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760547418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2760547418
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1242993287
Short name T785
Test name
Test status
Simulation time 11352256347 ps
CPU time 110.37 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:31:53 PM PDT 24
Peak memory 236660 kb
Host smart-a9ac1c19-f402-4ccd-9f90-ba9806d2b885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1242993287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1242993287
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.202394278
Short name T811
Test name
Test status
Simulation time 837955729 ps
CPU time 106.08 seconds
Started May 14 01:30:02 PM PDT 24
Finished May 14 01:31:50 PM PDT 24
Peak memory 240024 kb
Host smart-87460ec5-1a46-4f71-97f5-b06688b910b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=202394278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.202394278
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2236921106
Short name T712
Test name
Test status
Simulation time 38269113 ps
CPU time 6.48 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:06 PM PDT 24
Peak memory 240064 kb
Host smart-5296fbf3-7d93-4ca6-ac3c-15d20c86dcd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2236921106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2236921106
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.443958754
Short name T713
Test name
Test status
Simulation time 113616511 ps
CPU time 8.6 seconds
Started May 14 01:30:04 PM PDT 24
Finished May 14 01:30:14 PM PDT 24
Peak memory 239640 kb
Host smart-e2d88667-8a90-4df2-ab5c-a24737fa9a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443958754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.443958754
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4040416550
Short name T720
Test name
Test status
Simulation time 65099724 ps
CPU time 3.83 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:30:06 PM PDT 24
Peak memory 239344 kb
Host smart-e035ce25-67bc-4ec7-9e3a-af0d29ce88dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4040416550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4040416550
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.281109608
Short name T757
Test name
Test status
Simulation time 7802485 ps
CPU time 1.47 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:30:03 PM PDT 24
Peak memory 234504 kb
Host smart-ff70e9cd-c389-4b2b-b54a-f0f9bc21e4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=281109608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.281109608
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3621747194
Short name T192
Test name
Test status
Simulation time 909884971 ps
CPU time 19.51 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:30:20 PM PDT 24
Peak memory 244720 kb
Host smart-59a51b2b-6c8e-4f50-8d41-a2175249df1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621747194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3621747194
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2467533188
Short name T714
Test name
Test status
Simulation time 99113697 ps
CPU time 13.67 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:14 PM PDT 24
Peak memory 248300 kb
Host smart-764d1aa5-368e-4e62-a351-e381f44ec35e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2467533188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2467533188
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4094306118
Short name T824
Test name
Test status
Simulation time 1261593361 ps
CPU time 43.13 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:43 PM PDT 24
Peak memory 237476 kb
Host smart-121b3567-ab7c-49e2-ac98-f8a4d04e0ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4094306118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4094306118
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.442201668
Short name T783
Test name
Test status
Simulation time 4236558239 ps
CPU time 298.92 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:34:59 PM PDT 24
Peak memory 239996 kb
Host smart-2a55be75-850d-4893-9f2c-1ebefe542542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=442201668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.442201668
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4036417660
Short name T723
Test name
Test status
Simulation time 2595874796 ps
CPU time 230.79 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 236552 kb
Host smart-2ad3ffd0-d5f6-4c7d-9f54-5d92c7d32202
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4036417660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4036417660
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3069102042
Short name T800
Test name
Test status
Simulation time 135736042 ps
CPU time 6 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:30:07 PM PDT 24
Peak memory 240044 kb
Host smart-0b4bb193-75b9-40c4-b78f-35cb2603cbad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3069102042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3069102042
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.879506420
Short name T763
Test name
Test status
Simulation time 66515431 ps
CPU time 9.54 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:30:12 PM PDT 24
Peak memory 256408 kb
Host smart-9d06d1ee-51cd-4050-95f9-e92485855506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879506420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.879506420
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2380204891
Short name T727
Test name
Test status
Simulation time 109247478 ps
CPU time 8.76 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:30:09 PM PDT 24
Peak memory 240036 kb
Host smart-7f1ecd03-c3c8-4f2b-8ba9-22008be583bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2380204891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2380204891
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3403456789
Short name T230
Test name
Test status
Simulation time 25616012 ps
CPU time 2.48 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:30:04 PM PDT 24
Peak memory 235616 kb
Host smart-d4668135-4e5d-47dc-b875-5b6db3482120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3403456789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3403456789
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1157285140
Short name T186
Test name
Test status
Simulation time 553258582 ps
CPU time 23.54 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:23 PM PDT 24
Peak memory 244692 kb
Host smart-f06874ff-8d85-44c0-a7c2-fe947e768431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1157285140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1157285140
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3776541215
Short name T131
Test name
Test status
Simulation time 8926097022 ps
CPU time 365.25 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:36:06 PM PDT 24
Peak memory 265320 kb
Host smart-ddb71e45-6bc9-490e-b736-81d6cc4d813d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776541215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3776541215
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2275489889
Short name T724
Test name
Test status
Simulation time 440854955 ps
CPU time 5.96 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:30:06 PM PDT 24
Peak memory 248280 kb
Host smart-20f14ec4-3415-4474-b7d0-cf5ab7a3fa9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2275489889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2275489889
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.788130014
Short name T329
Test name
Test status
Simulation time 283705823 ps
CPU time 8.97 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 238716 kb
Host smart-21e3f07b-ea6a-46fb-be3c-190d0f03c004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788130014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.788130014
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2570417594
Short name T810
Test name
Test status
Simulation time 133965154 ps
CPU time 9.94 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 236448 kb
Host smart-32c6a29c-5966-4a58-b865-68b3c735fc01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2570417594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2570417594
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3303634336
Short name T817
Test name
Test status
Simulation time 511033248 ps
CPU time 19.72 seconds
Started May 14 01:30:13 PM PDT 24
Finished May 14 01:30:35 PM PDT 24
Peak memory 239912 kb
Host smart-429b5e37-e65b-4b79-a81b-3f35b2b4d7a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303634336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3303634336
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3279380447
Short name T148
Test name
Test status
Simulation time 3105976163 ps
CPU time 94.29 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:31:46 PM PDT 24
Peak memory 256756 kb
Host smart-28262204-f186-4209-9400-eb494a025d7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3279380447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3279380447
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1920026450
Short name T150
Test name
Test status
Simulation time 56992617227 ps
CPU time 634.13 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:40:47 PM PDT 24
Peak memory 265120 kb
Host smart-c4e9f59b-da03-4236-be1f-e6e414b39363
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920026450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1920026450
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1579617884
Short name T809
Test name
Test status
Simulation time 24704229 ps
CPU time 4.28 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:19 PM PDT 24
Peak memory 247944 kb
Host smart-a1b28dec-07ae-461b-be9e-cf21641f3efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1579617884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1579617884
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2132029252
Short name T736
Test name
Test status
Simulation time 29178359 ps
CPU time 4.65 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 240076 kb
Host smart-1f1b73be-1d52-43f5-ad41-4aa31e39a24e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132029252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2132029252
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.302846375
Short name T814
Test name
Test status
Simulation time 64339367 ps
CPU time 3.21 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 235988 kb
Host smart-e7855be9-a687-46c9-a2e7-441092957a2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=302846375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.302846375
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4192325709
Short name T231
Test name
Test status
Simulation time 9809887 ps
CPU time 1.58 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:13 PM PDT 24
Peak memory 235576 kb
Host smart-ded63059-e18a-4383-8f8f-dd775d4586b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4192325709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4192325709
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1804122160
Short name T760
Test name
Test status
Simulation time 175151127 ps
CPU time 22.09 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 244604 kb
Host smart-11d0781a-2641-4288-8e8f-ecb175f70981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1804122160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1804122160
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.409312816
Short name T731
Test name
Test status
Simulation time 121955428 ps
CPU time 15.23 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:25 PM PDT 24
Peak memory 247804 kb
Host smart-10aacc37-3b4e-4528-9b06-7b8c8c8d0e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=409312816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.409312816
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3501022445
Short name T742
Test name
Test status
Simulation time 139096669 ps
CPU time 8.21 seconds
Started May 14 01:30:12 PM PDT 24
Finished May 14 01:30:23 PM PDT 24
Peak memory 240096 kb
Host smart-1efacfaa-3de0-4ca7-b765-023b30c24ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501022445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3501022445
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3949133182
Short name T762
Test name
Test status
Simulation time 66645367 ps
CPU time 5.65 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236412 kb
Host smart-072a2887-45ba-4b25-8881-a58c786b9dc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3949133182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3949133182
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.586182705
Short name T716
Test name
Test status
Simulation time 14285460 ps
CPU time 1.32 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:15 PM PDT 24
Peak memory 234592 kb
Host smart-9f3c926a-80c2-4345-ae35-d58f11bb3203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=586182705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.586182705
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3290824028
Short name T753
Test name
Test status
Simulation time 170945135 ps
CPU time 21.73 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 244688 kb
Host smart-236c26f9-9823-4130-adda-f9b20ba20d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3290824028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3290824028
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3193488935
Short name T147
Test name
Test status
Simulation time 3444251137 ps
CPU time 104.21 seconds
Started May 14 01:30:13 PM PDT 24
Finished May 14 01:32:00 PM PDT 24
Peak memory 264992 kb
Host smart-8b7623a9-04f7-412a-9d7e-7094599c9bfe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193488935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3193488935
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3151500925
Short name T786
Test name
Test status
Simulation time 763697608 ps
CPU time 24.2 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 253332 kb
Host smart-39e34153-9832-4862-a3a1-00f864439c13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151500925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3151500925
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2250147684
Short name T776
Test name
Test status
Simulation time 576568923 ps
CPU time 9.5 seconds
Started May 14 01:30:24 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 240080 kb
Host smart-cda2e968-2bab-4099-bf08-caedb4f203d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250147684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2250147684
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.924909418
Short name T747
Test name
Test status
Simulation time 108636210 ps
CPU time 7.84 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 235548 kb
Host smart-0044889d-4022-451b-aeed-11402e950b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=924909418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.924909418
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3311246386
Short name T750
Test name
Test status
Simulation time 6767816 ps
CPU time 1.56 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 235512 kb
Host smart-0a90055f-8c2f-498f-9df8-0371452e2a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3311246386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3311246386
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4200486492
Short name T735
Test name
Test status
Simulation time 3396113318 ps
CPU time 43.24 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:31:09 PM PDT 24
Peak memory 244620 kb
Host smart-5ac2421d-7bbf-4e95-8c58-45680a12fbac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4200486492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4200486492
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3840440949
Short name T140
Test name
Test status
Simulation time 18700596865 ps
CPU time 347.66 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:36:14 PM PDT 24
Peak memory 265076 kb
Host smart-ec9483ab-5335-42c9-ad80-06e6bee4030f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840440949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3840440949
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1504115210
Short name T744
Test name
Test status
Simulation time 65261764 ps
CPU time 7.33 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 248252 kb
Host smart-3053198b-bc14-4fae-8aa3-4d7ecf67a687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1504115210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1504115210
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1019484964
Short name T728
Test name
Test status
Simulation time 45681437 ps
CPU time 6.02 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:30 PM PDT 24
Peak memory 241336 kb
Host smart-6ff9f220-4a99-4389-a076-ca67b7c361db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019484964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1019484964
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2384726356
Short name T227
Test name
Test status
Simulation time 266335613 ps
CPU time 5.86 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:32 PM PDT 24
Peak memory 236468 kb
Host smart-ff1abc59-a435-49ba-af17-b4d5f65cc813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2384726356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2384726356
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3294338624
Short name T323
Test name
Test status
Simulation time 15181622 ps
CPU time 1.82 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:27 PM PDT 24
Peak memory 235540 kb
Host smart-b7d566ae-4509-4721-beae-1f34be873010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3294338624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3294338624
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1641771507
Short name T726
Test name
Test status
Simulation time 178920729 ps
CPU time 22.8 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:46 PM PDT 24
Peak memory 243756 kb
Host smart-875d42ed-a87d-4c33-b8c2-61cc788d1fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1641771507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1641771507
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1807472970
Short name T765
Test name
Test status
Simulation time 132803411 ps
CPU time 8.49 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 248164 kb
Host smart-2d60ca12-fe9a-4ca7-a3aa-519e330d3f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1807472970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1807472970
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.622277217
Short name T775
Test name
Test status
Simulation time 222241080 ps
CPU time 5.51 seconds
Started May 14 01:30:20 PM PDT 24
Finished May 14 01:30:26 PM PDT 24
Peak memory 239020 kb
Host smart-b4b1ec91-69af-498d-8bc0-0bca9b71885f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622277217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.622277217
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3025529114
Short name T191
Test name
Test status
Simulation time 121138110 ps
CPU time 5.16 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:28 PM PDT 24
Peak memory 235560 kb
Host smart-a9eddb52-c512-4ccc-9137-210718593d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3025529114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3025529114
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2764274659
Short name T733
Test name
Test status
Simulation time 10425860 ps
CPU time 1.63 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:26 PM PDT 24
Peak memory 236524 kb
Host smart-02c11621-7c91-4c07-bbf8-44985aa1a4fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764274659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2764274659
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2569490926
Short name T187
Test name
Test status
Simulation time 1464304211 ps
CPU time 25.7 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:51 PM PDT 24
Peak memory 244668 kb
Host smart-5a2db7c2-1e9b-4178-881f-df57fcb9168a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2569490926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2569490926
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3364651019
Short name T749
Test name
Test status
Simulation time 93111183 ps
CPU time 10.02 seconds
Started May 14 01:30:20 PM PDT 24
Finished May 14 01:30:31 PM PDT 24
Peak memory 252940 kb
Host smart-3dda4ce0-0279-49cd-987d-1b041a3f380a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3364651019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3364651019
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3429350788
Short name T818
Test name
Test status
Simulation time 1321049413 ps
CPU time 41.41 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:31:07 PM PDT 24
Peak memory 240064 kb
Host smart-2c7cb821-30b1-4e2d-abe9-3790ffe2fead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3429350788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3429350788
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4248208932
Short name T746
Test name
Test status
Simulation time 841646143 ps
CPU time 12.29 seconds
Started May 14 01:30:25 PM PDT 24
Finished May 14 01:30:40 PM PDT 24
Peak memory 251308 kb
Host smart-37e76682-c288-4965-bfd6-1b14a30f75fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248208932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4248208932
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3472787087
Short name T816
Test name
Test status
Simulation time 23081933 ps
CPU time 3.9 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:28 PM PDT 24
Peak memory 236480 kb
Host smart-b1611b07-0eb6-4416-a556-76d7e2aeef67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3472787087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3472787087
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2501540783
Short name T764
Test name
Test status
Simulation time 8575249 ps
CPU time 1.53 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:27 PM PDT 24
Peak memory 236528 kb
Host smart-468f3c4b-58d7-4ff7-bf10-eacaa581abd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501540783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2501540783
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2231319409
Short name T737
Test name
Test status
Simulation time 324305044 ps
CPU time 14.58 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:39 PM PDT 24
Peak memory 244660 kb
Host smart-b47e6dd9-c953-4236-a8b7-2befab4789ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2231319409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2231319409
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4222555208
Short name T139
Test name
Test status
Simulation time 4000707122 ps
CPU time 145.24 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:32:52 PM PDT 24
Peak memory 268124 kb
Host smart-2c32bccd-5df8-4667-90bb-246fc969d915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4222555208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4222555208
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.20047607
Short name T804
Test name
Test status
Simulation time 127134603 ps
CPU time 9.05 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:35 PM PDT 24
Peak memory 248256 kb
Host smart-c1dd77b5-b28b-420f-903b-58e825b965da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=20047607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.20047607
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4127850479
Short name T792
Test name
Test status
Simulation time 900897362 ps
CPU time 13.61 seconds
Started May 14 01:30:28 PM PDT 24
Finished May 14 01:30:43 PM PDT 24
Peak memory 251360 kb
Host smart-68e39e78-1e3c-4107-b9b9-3c74cfe61f8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127850479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4127850479
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1510867108
Short name T793
Test name
Test status
Simulation time 259261933 ps
CPU time 11.3 seconds
Started May 14 01:30:24 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 239996 kb
Host smart-e4c60011-1f2d-47db-a796-1b5bccb7f069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1510867108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1510867108
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3313289263
Short name T796
Test name
Test status
Simulation time 11379991 ps
CPU time 1.45 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:23 PM PDT 24
Peak memory 235576 kb
Host smart-244114f9-894d-49a5-9b8c-488551718bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3313289263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3313289263
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3519646992
Short name T743
Test name
Test status
Simulation time 511377553 ps
CPU time 37.8 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:31:03 PM PDT 24
Peak memory 244684 kb
Host smart-ab0a8180-a232-422d-b1ba-94c9e2a8e8e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3519646992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3519646992
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2443147290
Short name T135
Test name
Test status
Simulation time 10731860940 ps
CPU time 371.86 seconds
Started May 14 01:30:24 PM PDT 24
Finished May 14 01:36:39 PM PDT 24
Peak memory 265020 kb
Host smart-60ac5991-ca13-439b-9946-d1815292007f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443147290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2443147290
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3497702019
Short name T781
Test name
Test status
Simulation time 187174703 ps
CPU time 16.9 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:42 PM PDT 24
Peak memory 248276 kb
Host smart-1192bfc0-dea9-4485-9e17-250b11b154fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497702019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3497702019
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4059445382
Short name T795
Test name
Test status
Simulation time 273865584 ps
CPU time 5.99 seconds
Started May 14 01:30:28 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 240120 kb
Host smart-d59a8100-2b89-4d4b-be78-67d303fe7b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059445382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4059445382
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.632902211
Short name T808
Test name
Test status
Simulation time 66773539 ps
CPU time 6.02 seconds
Started May 14 01:30:26 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 236436 kb
Host smart-c8a4757a-9201-4cbb-890e-4567d886398d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=632902211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.632902211
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.566511142
Short name T756
Test name
Test status
Simulation time 11288426 ps
CPU time 1.47 seconds
Started May 14 01:30:24 PM PDT 24
Finished May 14 01:30:28 PM PDT 24
Peak memory 234496 kb
Host smart-f9feb61f-4a7a-43d5-b551-d119e8d574e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=566511142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.566511142
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4028524395
Short name T805
Test name
Test status
Simulation time 177548493 ps
CPU time 21.4 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:46 PM PDT 24
Peak memory 243728 kb
Host smart-11b25890-88eb-40dd-91ec-228274b71115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4028524395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.4028524395
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3341365997
Short name T119
Test name
Test status
Simulation time 2271126971 ps
CPU time 156.27 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:33:01 PM PDT 24
Peak memory 265020 kb
Host smart-80fcd635-499f-4c87-ac59-06e7d5f13b39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3341365997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3341365997
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1187410933
Short name T803
Test name
Test status
Simulation time 216886105 ps
CPU time 13.55 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 247856 kb
Host smart-e7261993-20fc-4b2a-9b74-da32f5bc1d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1187410933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1187410933
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3482473264
Short name T773
Test name
Test status
Simulation time 637404868 ps
CPU time 12.41 seconds
Started May 14 01:30:25 PM PDT 24
Finished May 14 01:30:40 PM PDT 24
Peak memory 249248 kb
Host smart-99d6843d-0d2e-452a-8621-9622b947e6d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482473264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3482473264
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2660966484
Short name T758
Test name
Test status
Simulation time 130715358 ps
CPU time 6.09 seconds
Started May 14 01:30:25 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 236468 kb
Host smart-035d4b03-ec6b-4a31-9c95-1525374949dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2660966484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2660966484
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2986263220
Short name T794
Test name
Test status
Simulation time 13905815 ps
CPU time 1.45 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:27 PM PDT 24
Peak memory 235460 kb
Host smart-db462ce2-1e7a-40f4-9ef6-4f61d897b217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2986263220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2986263220
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.221304481
Short name T798
Test name
Test status
Simulation time 181741767 ps
CPU time 27.09 seconds
Started May 14 01:30:23 PM PDT 24
Finished May 14 01:30:53 PM PDT 24
Peak memory 244736 kb
Host smart-f964e0b4-a251-4964-bfc2-0aa0e01a41bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=221304481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.221304481
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.555990305
Short name T143
Test name
Test status
Simulation time 1593664740 ps
CPU time 130.07 seconds
Started May 14 01:30:21 PM PDT 24
Finished May 14 01:32:33 PM PDT 24
Peak memory 256824 kb
Host smart-c5741b37-1dfa-4d6d-b8c7-7e18c56b76d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=555990305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.555990305
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.546498865
Short name T770
Test name
Test status
Simulation time 247006546 ps
CPU time 11.48 seconds
Started May 14 01:30:25 PM PDT 24
Finished May 14 01:30:39 PM PDT 24
Peak memory 248228 kb
Host smart-23679b46-69b5-4044-a231-d97fc1ea1159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546498865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.546498865
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4173119936
Short name T189
Test name
Test status
Simulation time 15114482776 ps
CPU time 236.25 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:33:58 PM PDT 24
Peak memory 240112 kb
Host smart-ccd2c3c6-7545-4b58-9832-725fe95050b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4173119936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4173119936
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.743797825
Short name T708
Test name
Test status
Simulation time 5953141586 ps
CPU time 203.62 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:33:23 PM PDT 24
Peak memory 236564 kb
Host smart-e22908c6-3f6a-48a5-addb-2c06892258b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=743797825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.743797825
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.527280318
Short name T799
Test name
Test status
Simulation time 855988295 ps
CPU time 9.22 seconds
Started May 14 01:30:02 PM PDT 24
Finished May 14 01:30:12 PM PDT 24
Peak memory 240048 kb
Host smart-7ef2e61e-3194-4488-91d1-0847ba493b3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=527280318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.527280318
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.747791384
Short name T326
Test name
Test status
Simulation time 259428898 ps
CPU time 5.3 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:30:07 PM PDT 24
Peak memory 255508 kb
Host smart-49b0df6b-c740-4c8f-a8a6-0e180c99767d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747791384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.747791384
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.291851416
Short name T745
Test name
Test status
Simulation time 62913320 ps
CPU time 4.87 seconds
Started May 14 01:30:02 PM PDT 24
Finished May 14 01:30:08 PM PDT 24
Peak memory 235572 kb
Host smart-62fdea27-ea76-4f75-83bd-8c623fc380f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=291851416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.291851416
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2364370544
Short name T787
Test name
Test status
Simulation time 9363976 ps
CPU time 1.42 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:01 PM PDT 24
Peak memory 235556 kb
Host smart-ed9cf612-6957-4c7e-8a25-7a4848817fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2364370544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2364370544
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2743329728
Short name T774
Test name
Test status
Simulation time 961812651 ps
CPU time 20.88 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 244716 kb
Host smart-80dca67e-6beb-463f-955e-04e0d7bfb7d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2743329728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2743329728
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.970797755
Short name T141
Test name
Test status
Simulation time 24557151469 ps
CPU time 1045.8 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:47:36 PM PDT 24
Peak memory 265028 kb
Host smart-98bd7266-d425-4b7b-8456-2cfa33214f5c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970797755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.970797755
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1465070792
Short name T755
Test name
Test status
Simulation time 1880303495 ps
CPU time 16.9 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 248344 kb
Host smart-53df3f7f-26bb-404d-87e2-638a91045415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1465070792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1465070792
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3441898459
Short name T152
Test name
Test status
Simulation time 2020746354 ps
CPU time 33.73 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:44 PM PDT 24
Peak memory 236588 kb
Host smart-c1e5da27-4e37-4a3d-bd22-37504fa22dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3441898459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3441898459
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2599449322
Short name T709
Test name
Test status
Simulation time 11225516 ps
CPU time 1.7 seconds
Started May 14 01:30:28 PM PDT 24
Finished May 14 01:30:31 PM PDT 24
Peak memory 236400 kb
Host smart-5f27cb47-33ba-4acf-9d3d-603c7ba48642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2599449322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2599449322
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1220317994
Short name T815
Test name
Test status
Simulation time 14887242 ps
CPU time 1.39 seconds
Started May 14 01:30:28 PM PDT 24
Finished May 14 01:30:31 PM PDT 24
Peak memory 235576 kb
Host smart-a2ea8df0-55c8-4d9a-9c3d-aa64bda3c8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1220317994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1220317994
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.880698834
Short name T325
Test name
Test status
Simulation time 8781827 ps
CPU time 1.51 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:27 PM PDT 24
Peak memory 235500 kb
Host smart-91155f27-04f8-474a-bb43-f7cc71cfeb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=880698834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.880698834
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1605438989
Short name T157
Test name
Test status
Simulation time 8825390 ps
CPU time 1.53 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:26 PM PDT 24
Peak memory 235572 kb
Host smart-6cc2c906-84f8-4237-814f-fd9add0c7f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1605438989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1605438989
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3955182789
Short name T155
Test name
Test status
Simulation time 22651041 ps
CPU time 1.37 seconds
Started May 14 01:30:22 PM PDT 24
Finished May 14 01:30:26 PM PDT 24
Peak memory 235540 kb
Host smart-a2f56e75-dff3-429b-bf58-03d2ae6df4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3955182789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3955182789
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2203824432
Short name T769
Test name
Test status
Simulation time 23668095 ps
CPU time 1.47 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 235540 kb
Host smart-4bb218c3-eb6f-43de-aa41-e761cde01dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2203824432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2203824432
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1891440081
Short name T718
Test name
Test status
Simulation time 10190303 ps
CPU time 1.57 seconds
Started May 14 01:30:29 PM PDT 24
Finished May 14 01:30:32 PM PDT 24
Peak memory 236532 kb
Host smart-278bb84e-6880-47a1-b5b3-16f5d9efbdea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891440081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1891440081
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.4011474212
Short name T766
Test name
Test status
Simulation time 21869106 ps
CPU time 1.45 seconds
Started May 14 01:30:36 PM PDT 24
Finished May 14 01:30:39 PM PDT 24
Peak memory 235560 kb
Host smart-ae3d96f4-4b1a-4e40-ae05-172f119d58a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4011474212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.4011474212
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3608695343
Short name T790
Test name
Test status
Simulation time 8927839 ps
CPU time 1.52 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 235620 kb
Host smart-011e9a8f-8db7-4a04-bded-202e2322c08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3608695343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3608695343
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3713296583
Short name T190
Test name
Test status
Simulation time 1095794746 ps
CPU time 169.55 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:33:00 PM PDT 24
Peak memory 238772 kb
Host smart-1194bbe8-9a54-47d7-8417-dbc99f4520fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3713296583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3713296583
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4005278673
Short name T806
Test name
Test status
Simulation time 4501073098 ps
CPU time 295.03 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:34:56 PM PDT 24
Peak memory 236552 kb
Host smart-2b19b427-44c6-4102-86c4-6a80835112c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4005278673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4005278673
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1153622943
Short name T188
Test name
Test status
Simulation time 41112580 ps
CPU time 6.51 seconds
Started May 14 01:30:03 PM PDT 24
Finished May 14 01:30:10 PM PDT 24
Peak memory 239992 kb
Host smart-1f30a9b9-8ffb-444d-b419-570f3e79ec3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1153622943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1153622943
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.631657937
Short name T327
Test name
Test status
Simulation time 81178625 ps
CPU time 6.91 seconds
Started May 14 01:30:00 PM PDT 24
Finished May 14 01:30:09 PM PDT 24
Peak memory 240072 kb
Host smart-ba882e64-7645-4d8a-bd25-0cf1f4b26acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631657937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.631657937
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1066167967
Short name T721
Test name
Test status
Simulation time 52662156 ps
CPU time 5.32 seconds
Started May 14 01:29:59 PM PDT 24
Finished May 14 01:30:06 PM PDT 24
Peak memory 236488 kb
Host smart-8f31bff5-01c3-4693-a77b-02d2e5fb0851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1066167967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1066167967
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3972800039
Short name T729
Test name
Test status
Simulation time 24025806 ps
CPU time 1.4 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:01 PM PDT 24
Peak memory 235612 kb
Host smart-03d1a8e9-69a6-49db-9c00-5e97713d6875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3972800039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3972800039
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2191935603
Short name T741
Test name
Test status
Simulation time 337771352 ps
CPU time 23.79 seconds
Started May 14 01:29:58 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 244728 kb
Host smart-c4ee9318-d431-47c4-b2c7-d8f203bedbc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2191935603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2191935603
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4279195586
Short name T136
Test name
Test status
Simulation time 3007757003 ps
CPU time 103.82 seconds
Started May 14 01:30:06 PM PDT 24
Finished May 14 01:31:53 PM PDT 24
Peak memory 256888 kb
Host smart-70b6c15c-bb86-4d54-a2cd-ffbc84c958b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4279195586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4279195586
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2546260535
Short name T751
Test name
Test status
Simulation time 288308385 ps
CPU time 20.05 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:30:23 PM PDT 24
Peak memory 248296 kb
Host smart-f23a2eaf-e2a6-4173-8c3b-c0b59501b410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2546260535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2546260535
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.785124323
Short name T734
Test name
Test status
Simulation time 46271974 ps
CPU time 1.3 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 235364 kb
Host smart-149b8faf-9d8c-4cab-9819-4cac1b0df838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=785124323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.785124323
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1940692846
Short name T772
Test name
Test status
Simulation time 10846076 ps
CPU time 1.58 seconds
Started May 14 01:30:29 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 234792 kb
Host smart-189a13c4-3401-4fb3-bb7c-4f0d0df8eee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1940692846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1940692846
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2130950500
Short name T711
Test name
Test status
Simulation time 12667415 ps
CPU time 1.66 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:30:36 PM PDT 24
Peak memory 235480 kb
Host smart-74774e2c-c2d6-4149-96f9-037b23ab30dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2130950500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2130950500
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1930829029
Short name T719
Test name
Test status
Simulation time 16666259 ps
CPU time 1.3 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 236476 kb
Host smart-ea3a28eb-288b-4ad7-b6dc-794045da136a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1930829029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1930829029
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1420556314
Short name T782
Test name
Test status
Simulation time 78933205 ps
CPU time 1.42 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 235448 kb
Host smart-42e2367a-de5f-4580-8f12-7df7f117e326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420556314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1420556314
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3924968450
Short name T771
Test name
Test status
Simulation time 16175558 ps
CPU time 1.48 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 236540 kb
Host smart-504bb6fa-234f-4d14-8aa7-eca23d06a9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924968450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3924968450
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1568755023
Short name T217
Test name
Test status
Simulation time 11285580 ps
CPU time 1.34 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 236532 kb
Host smart-bee7e221-acd0-43fc-bb64-62b1065b48eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568755023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1568755023
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.37381580
Short name T759
Test name
Test status
Simulation time 10816291 ps
CPU time 1.33 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:37 PM PDT 24
Peak memory 234552 kb
Host smart-9358f5a5-6a16-4b59-b872-08cbc5248588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=37381580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.37381580
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1197220460
Short name T156
Test name
Test status
Simulation time 9754218 ps
CPU time 1.39 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:34 PM PDT 24
Peak memory 236492 kb
Host smart-58ee403c-fe8e-4c6e-bb0f-3e39b174294c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197220460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1197220460
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3206450894
Short name T813
Test name
Test status
Simulation time 2155404132 ps
CPU time 135.27 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:32:27 PM PDT 24
Peak memory 236572 kb
Host smart-54ee6310-6139-4b24-8474-a680d328924e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3206450894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3206450894
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.899844989
Short name T784
Test name
Test status
Simulation time 25914844373 ps
CPU time 214.9 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:33:46 PM PDT 24
Peak memory 240032 kb
Host smart-b51d69e0-4070-4573-9611-2269ee5e295e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=899844989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.899844989
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.877925782
Short name T777
Test name
Test status
Simulation time 53206089 ps
CPU time 5.64 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:16 PM PDT 24
Peak memory 239992 kb
Host smart-43cc47ae-cb61-4101-8703-5e6bf515efd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=877925782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.877925782
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4162891662
Short name T328
Test name
Test status
Simulation time 203139038 ps
CPU time 8.12 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:20 PM PDT 24
Peak memory 249316 kb
Host smart-e642216c-fbc0-49d2-9553-52caa76e311c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162891662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4162891662
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3745307176
Short name T752
Test name
Test status
Simulation time 110174400 ps
CPU time 8.21 seconds
Started May 14 01:30:12 PM PDT 24
Finished May 14 01:30:23 PM PDT 24
Peak memory 240000 kb
Host smart-adf051bd-3cb1-4e6c-a7ef-99b52078ec5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3745307176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3745307176
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2871875402
Short name T705
Test name
Test status
Simulation time 24977810 ps
CPU time 1.42 seconds
Started May 14 01:29:57 PM PDT 24
Finished May 14 01:29:59 PM PDT 24
Peak memory 236528 kb
Host smart-9435ee4c-86e1-4635-af1c-c3ef4040d8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2871875402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2871875402
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.930426545
Short name T748
Test name
Test status
Simulation time 528477642 ps
CPU time 35.73 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:47 PM PDT 24
Peak memory 248240 kb
Host smart-ab5425ea-1b90-4bbc-97c4-8f4eb2a43539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=930426545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.930426545
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.645339469
Short name T123
Test name
Test status
Simulation time 1705180316 ps
CPU time 127.57 seconds
Started May 14 01:30:05 PM PDT 24
Finished May 14 01:32:14 PM PDT 24
Peak memory 256812 kb
Host smart-57644504-8c4c-4e5c-add6-54193d6b4997
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=645339469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.645339469
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3592405705
Short name T812
Test name
Test status
Simulation time 4383753729 ps
CPU time 328.01 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:35:30 PM PDT 24
Peak memory 265008 kb
Host smart-8fefaa2c-d77a-4e74-901e-7e3be86b0651
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592405705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3592405705
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.827043076
Short name T229
Test name
Test status
Simulation time 987368347 ps
CPU time 11.76 seconds
Started May 14 01:30:02 PM PDT 24
Finished May 14 01:30:15 PM PDT 24
Peak memory 252052 kb
Host smart-c0abb5da-5653-425f-80e1-a49a289f6311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=827043076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.827043076
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2395430537
Short name T261
Test name
Test status
Simulation time 320978847 ps
CPU time 25.15 seconds
Started May 14 01:30:01 PM PDT 24
Finished May 14 01:30:27 PM PDT 24
Peak memory 236952 kb
Host smart-d5e73633-7642-4c52-b3ed-7b2efe954808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2395430537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2395430537
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2499416133
Short name T706
Test name
Test status
Simulation time 13794756 ps
CPU time 1.47 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 236476 kb
Host smart-8ef786e0-f8f3-4390-bd51-eee79d480398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499416133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2499416133
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3789017478
Short name T739
Test name
Test status
Simulation time 20680410 ps
CPU time 1.37 seconds
Started May 14 01:30:28 PM PDT 24
Finished May 14 01:30:31 PM PDT 24
Peak memory 236524 kb
Host smart-fee54e81-ac31-4f09-aec2-e44ccdfca2c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3789017478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3789017478
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3412291301
Short name T789
Test name
Test status
Simulation time 15953723 ps
CPU time 1.43 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 236540 kb
Host smart-3bb08e8e-6bf5-492d-b851-e8799fea56d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412291301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3412291301
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1094165370
Short name T715
Test name
Test status
Simulation time 7860084 ps
CPU time 1.4 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 235540 kb
Host smart-9a84efe5-00d0-47a8-920e-7b70f80c3287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1094165370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1094165370
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.881875137
Short name T732
Test name
Test status
Simulation time 8931214 ps
CPU time 1.58 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 234572 kb
Host smart-b7a0c8c5-eb9c-46e2-86df-b89d11deb8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=881875137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.881875137
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3477180436
Short name T819
Test name
Test status
Simulation time 19841222 ps
CPU time 1.36 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:30:35 PM PDT 24
Peak memory 236508 kb
Host smart-3b390e8f-2a26-40bf-afa2-909045c68d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3477180436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3477180436
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.547070266
Short name T704
Test name
Test status
Simulation time 15715967 ps
CPU time 1.53 seconds
Started May 14 01:30:29 PM PDT 24
Finished May 14 01:30:32 PM PDT 24
Peak memory 236536 kb
Host smart-3950249f-c896-4963-867f-d0c1bbc0d336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=547070266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.547070266
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2505284524
Short name T324
Test name
Test status
Simulation time 23451590 ps
CPU time 1.17 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:33 PM PDT 24
Peak memory 234608 kb
Host smart-e0b30c86-3005-41d4-95a5-9f767fee9e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2505284524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2505284524
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.857041255
Short name T801
Test name
Test status
Simulation time 8730773 ps
CPU time 1.27 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:30:35 PM PDT 24
Peak memory 236540 kb
Host smart-55a42ad5-e470-4ccf-bbd7-697dd76707b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=857041255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.857041255
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.132464675
Short name T823
Test name
Test status
Simulation time 15918576 ps
CPU time 1.37 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:30:38 PM PDT 24
Peak memory 235472 kb
Host smart-2279744d-360c-4432-8255-d4fa51a7d16c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=132464675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.132464675
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3883172080
Short name T717
Test name
Test status
Simulation time 57819982 ps
CPU time 4.81 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:19 PM PDT 24
Peak memory 240040 kb
Host smart-a85de3c2-b220-465e-9994-f7821fd0adf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883172080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3883172080
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1960836130
Short name T791
Test name
Test status
Simulation time 215996092 ps
CPU time 5.24 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 235496 kb
Host smart-a2fa6fef-fa8c-426a-86d0-9a1c40817b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1960836130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1960836130
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3831741503
Short name T710
Test name
Test status
Simulation time 62091915 ps
CPU time 1.44 seconds
Started May 14 01:30:13 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236344 kb
Host smart-928cd920-3a44-4d5b-bdc9-482d1c51beac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3831741503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3831741503
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.524184312
Short name T172
Test name
Test status
Simulation time 530342753 ps
CPU time 46.59 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:31:01 PM PDT 24
Peak memory 244236 kb
Host smart-bb572443-3025-4c6d-922f-769624e09183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=524184312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.524184312
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3133521241
Short name T126
Test name
Test status
Simulation time 11727131926 ps
CPU time 173.79 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:33:06 PM PDT 24
Peak memory 256868 kb
Host smart-4c3c0537-cc12-4885-8f91-b7bf586d7e01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3133521241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3133521241
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3558611014
Short name T116
Test name
Test status
Simulation time 12462070981 ps
CPU time 555.05 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 269196 kb
Host smart-2afeabe6-4749-4a9c-ada1-ffddbb37c3b7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558611014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3558611014
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1640570921
Short name T754
Test name
Test status
Simulation time 1189106822 ps
CPU time 21.46 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:35 PM PDT 24
Peak memory 255656 kb
Host smart-4290b3e5-506f-4dd0-935d-2000d2802a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1640570921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1640570921
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3533569910
Short name T797
Test name
Test status
Simulation time 200210539 ps
CPU time 9.12 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:22 PM PDT 24
Peak memory 236900 kb
Host smart-28d9dfd5-4260-416e-be8c-a5a680aacbb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533569910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3533569910
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3126145974
Short name T767
Test name
Test status
Simulation time 49056131 ps
CPU time 4.83 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236464 kb
Host smart-3bf77db9-bca7-412c-a1f6-8842eb0e09aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3126145974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3126145974
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1762443245
Short name T722
Test name
Test status
Simulation time 10804657 ps
CPU time 1.38 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:16 PM PDT 24
Peak memory 235556 kb
Host smart-92860345-79c6-46a6-bffd-b084330818b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762443245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1762443245
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2921788559
Short name T761
Test name
Test status
Simulation time 91849308 ps
CPU time 11.59 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 244692 kb
Host smart-57e351a2-3b7a-4bce-b837-4d56b063f922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2921788559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2921788559
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2878645281
Short name T122
Test name
Test status
Simulation time 2549008434 ps
CPU time 171.66 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:33:07 PM PDT 24
Peak memory 256680 kb
Host smart-9c2345db-2b76-486f-ba79-2f8f63d5b4eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2878645281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2878645281
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3324328250
Short name T228
Test name
Test status
Simulation time 905084470 ps
CPU time 8.53 seconds
Started May 14 01:30:12 PM PDT 24
Finished May 14 01:30:24 PM PDT 24
Peak memory 248332 kb
Host smart-5af288b5-2ff7-49c5-aae6-2b06e6257075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324328250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3324328250
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1134510251
Short name T820
Test name
Test status
Simulation time 55316693 ps
CPU time 4.73 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:19 PM PDT 24
Peak memory 248132 kb
Host smart-a749a9eb-e33b-499d-a0e2-1bc67f8bb738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134510251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1134510251
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3123713275
Short name T821
Test name
Test status
Simulation time 34679867 ps
CPU time 3.35 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 236500 kb
Host smart-9599ea9a-b6be-4ad5-beba-c49b1949491c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3123713275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3123713275
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3762460034
Short name T768
Test name
Test status
Simulation time 6478509 ps
CPU time 1.38 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:13 PM PDT 24
Peak memory 235580 kb
Host smart-2f29e709-e7d1-4008-8eaf-abe7b43d5423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762460034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3762460034
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2160537847
Short name T740
Test name
Test status
Simulation time 450170869 ps
CPU time 10.43 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:25 PM PDT 24
Peak memory 240008 kb
Host smart-aca7b38b-5af5-4680-bace-6f8226bf6896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2160537847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2160537847
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.106016727
Short name T142
Test name
Test status
Simulation time 15378226977 ps
CPU time 554.91 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 265268 kb
Host smart-350bba20-9dff-43f6-ac18-6672c7106b58
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106016727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.106016727
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2576485434
Short name T707
Test name
Test status
Simulation time 61982941 ps
CPU time 7.17 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 247960 kb
Host smart-1b9069c1-0fa0-454a-9a2f-939e56f45db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2576485434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2576485434
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3154164475
Short name T807
Test name
Test status
Simulation time 236305088 ps
CPU time 5.65 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 248436 kb
Host smart-3dd8f105-4865-4eeb-8590-f221402c10e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154164475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3154164475
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3028736271
Short name T822
Test name
Test status
Simulation time 20708241 ps
CPU time 3.42 seconds
Started May 14 01:30:11 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 239332 kb
Host smart-4313feef-8145-4f74-a286-1b7e9faec16e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3028736271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3028736271
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2402541063
Short name T788
Test name
Test status
Simulation time 11297113 ps
CPU time 1.44 seconds
Started May 14 01:30:12 PM PDT 24
Finished May 14 01:30:17 PM PDT 24
Peak memory 235616 kb
Host smart-5c641edb-ba65-411b-a7d1-50b527bc48b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2402541063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2402541063
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2181301341
Short name T779
Test name
Test status
Simulation time 791543265 ps
CPU time 18.67 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:32 PM PDT 24
Peak memory 248224 kb
Host smart-dc5cf067-8b17-4823-bd64-c9e296d97098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2181301341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2181301341
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.693926196
Short name T114
Test name
Test status
Simulation time 4224320573 ps
CPU time 105.13 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:31:59 PM PDT 24
Peak memory 265044 kb
Host smart-a50069aa-479d-430e-95b8-886d02cc2951
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693926196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.693926196
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1904108970
Short name T149
Test name
Test status
Simulation time 12475619996 ps
CPU time 499.18 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:38:31 PM PDT 24
Peak memory 265040 kb
Host smart-be492684-ecf3-4be9-b6d5-4108437e072f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904108970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1904108970
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2562940433
Short name T730
Test name
Test status
Simulation time 129643810 ps
CPU time 9.95 seconds
Started May 14 01:30:08 PM PDT 24
Finished May 14 01:30:22 PM PDT 24
Peak memory 248328 kb
Host smart-f260455b-5fa1-408a-a2b7-0bc221fc1bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562940433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2562940433
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2191039516
Short name T171
Test name
Test status
Simulation time 113538932 ps
CPU time 5.11 seconds
Started May 14 01:30:13 PM PDT 24
Finished May 14 01:30:21 PM PDT 24
Peak memory 240048 kb
Host smart-8d917f72-b651-425f-9ad8-6393e86f62f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191039516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2191039516
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1816691495
Short name T802
Test name
Test status
Simulation time 191365752 ps
CPU time 4.96 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:18 PM PDT 24
Peak memory 236440 kb
Host smart-e92b75e3-c91b-4cef-85be-e18a14793f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1816691495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1816691495
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1752221568
Short name T780
Test name
Test status
Simulation time 8085722 ps
CPU time 1.56 seconds
Started May 14 01:30:10 PM PDT 24
Finished May 14 01:30:15 PM PDT 24
Peak memory 234524 kb
Host smart-b6e17ad3-d9a0-4c23-8b17-f892a483fd35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1752221568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1752221568
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4134518758
Short name T738
Test name
Test status
Simulation time 2230287024 ps
CPU time 36.96 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:30:50 PM PDT 24
Peak memory 243760 kb
Host smart-c3266679-8795-4b94-beab-f815f3c5ef9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4134518758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4134518758
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.626933168
Short name T146
Test name
Test status
Simulation time 11063915995 ps
CPU time 116.28 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:32:06 PM PDT 24
Peak memory 265004 kb
Host smart-51fc1e8f-7510-44dc-b443-3d307008ce73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=626933168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.626933168
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1505189948
Short name T138
Test name
Test status
Simulation time 23336085384 ps
CPU time 599.3 seconds
Started May 14 01:30:09 PM PDT 24
Finished May 14 01:40:12 PM PDT 24
Peak memory 265048 kb
Host smart-49022183-65c1-46a3-9e85-8d11a28100c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505189948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1505189948
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3083480756
Short name T778
Test name
Test status
Simulation time 237365750 ps
CPU time 9.15 seconds
Started May 14 01:30:07 PM PDT 24
Finished May 14 01:30:19 PM PDT 24
Peak memory 248284 kb
Host smart-64b5ddb2-eb91-45b8-94ab-9a2d1261c443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3083480756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3083480756
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3116824376
Short name T54
Test name
Test status
Simulation time 29714027490 ps
CPU time 1007.56 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:47:24 PM PDT 24
Peak memory 265196 kb
Host smart-c0a885b2-787f-4f73-bb99-b6cac7ac4418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116824376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3116824376
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3818781948
Short name T375
Test name
Test status
Simulation time 814301312 ps
CPU time 35.08 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:31:07 PM PDT 24
Peak memory 248784 kb
Host smart-66b911c0-53d6-4261-a653-e5d2fb6a46d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3818781948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3818781948
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.755823902
Short name T429
Test name
Test status
Simulation time 19385143283 ps
CPU time 133.86 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:32:50 PM PDT 24
Peak memory 256892 kb
Host smart-a2306816-754c-4865-81bd-720e580a5806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75582
3902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.755823902
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.371620338
Short name T418
Test name
Test status
Simulation time 598633816 ps
CPU time 11.04 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:47 PM PDT 24
Peak memory 251980 kb
Host smart-468d7d43-ba4c-4ee2-aeed-ca381aa34ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
0338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.371620338
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1488207330
Short name T647
Test name
Test status
Simulation time 12658273995 ps
CPU time 1047.26 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:48:00 PM PDT 24
Peak memory 273408 kb
Host smart-061ad597-c32e-43af-bbbd-b98ba62b1a88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488207330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1488207330
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3658463717
Short name T59
Test name
Test status
Simulation time 10433968973 ps
CPU time 658.75 seconds
Started May 14 01:30:35 PM PDT 24
Finished May 14 01:41:36 PM PDT 24
Peak memory 265384 kb
Host smart-33a83f44-50ce-4217-8640-484d1a13c87d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658463717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3658463717
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1457233319
Short name T695
Test name
Test status
Simulation time 7108817749 ps
CPU time 172.36 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:33:26 PM PDT 24
Peak memory 254152 kb
Host smart-79466e69-e51d-44ea-bd45-ced1115d0978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457233319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1457233319
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1539169302
Short name T575
Test name
Test status
Simulation time 2299232980 ps
CPU time 33.63 seconds
Started May 14 01:30:32 PM PDT 24
Finished May 14 01:31:08 PM PDT 24
Peak memory 248732 kb
Host smart-d0131f67-3ab4-41e4-ae71-63a6ea6f0040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15391
69302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1539169302
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1545182474
Short name T29
Test name
Test status
Simulation time 1361420563 ps
CPU time 28.06 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:31:00 PM PDT 24
Peak memory 248860 kb
Host smart-16accaff-72f8-46a9-8633-f53b4652529f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15451
82474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1545182474
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3593629465
Short name T331
Test name
Test status
Simulation time 478959221 ps
CPU time 9.87 seconds
Started May 14 01:30:29 PM PDT 24
Finished May 14 01:30:40 PM PDT 24
Peak memory 254964 kb
Host smart-fcbfc869-f35d-43c5-943e-fafb4bdb5ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
29465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3593629465
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1861675105
Short name T78
Test name
Test status
Simulation time 23554770505 ps
CPU time 1092.45 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:48:46 PM PDT 24
Peak memory 289760 kb
Host smart-2740fc80-3b0d-465d-85dc-f27431ca35a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861675105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1861675105
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2810653815
Short name T356
Test name
Test status
Simulation time 34604412871 ps
CPU time 2181.69 seconds
Started May 14 01:30:36 PM PDT 24
Finished May 14 02:07:00 PM PDT 24
Peak memory 289072 kb
Host smart-1987316f-9d8c-41aa-afad-f314c3f241a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810653815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2810653815
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.173672229
Short name T348
Test name
Test status
Simulation time 763810721 ps
CPU time 18.75 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:30:55 PM PDT 24
Peak memory 240524 kb
Host smart-9061bdfb-b0a4-4ccb-93f9-16e79a9be2b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173672229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.173672229
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4003366541
Short name T528
Test name
Test status
Simulation time 7871817620 ps
CPU time 93.75 seconds
Started May 14 01:30:37 PM PDT 24
Finished May 14 01:32:12 PM PDT 24
Peak memory 256920 kb
Host smart-92dba49f-2cf7-46e4-8ffa-3b94143faa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
66541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4003366541
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1058603219
Short name T472
Test name
Test status
Simulation time 663754872 ps
CPU time 37.89 seconds
Started May 14 01:30:37 PM PDT 24
Finished May 14 01:31:16 PM PDT 24
Peak memory 248692 kb
Host smart-b6f4f8b3-8ec0-4bc4-b727-e5c3a667a31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
03219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1058603219
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2676552056
Short name T681
Test name
Test status
Simulation time 36097493806 ps
CPU time 2126.39 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 02:06:01 PM PDT 24
Peak memory 289284 kb
Host smart-58c2dfed-39eb-44d3-811b-2c3ecc71a019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676552056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2676552056
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3030524466
Short name T427
Test name
Test status
Simulation time 22293524655 ps
CPU time 945.84 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:46:20 PM PDT 24
Peak memory 271868 kb
Host smart-11cadaf9-ee5b-4284-8df7-dd9c8c8ce3c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030524466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3030524466
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3892396929
Short name T221
Test name
Test status
Simulation time 25139311826 ps
CPU time 243.39 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 247696 kb
Host smart-44cf592b-6749-4cd6-a87d-fd273c7bd2c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892396929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3892396929
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.129171824
Short name T399
Test name
Test status
Simulation time 112827508 ps
CPU time 4.1 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:40 PM PDT 24
Peak memory 240476 kb
Host smart-8e93442a-2ef6-4ea2-ae1d-443bf38ec644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917
1824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.129171824
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.401858868
Short name T437
Test name
Test status
Simulation time 4472268071 ps
CPU time 69.56 seconds
Started May 14 01:30:34 PM PDT 24
Finished May 14 01:31:46 PM PDT 24
Peak memory 255636 kb
Host smart-0c4a3cc5-b2b5-459d-ab30-3c5e6584a36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
8868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.401858868
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4022603628
Short name T26
Test name
Test status
Simulation time 415318460 ps
CPU time 13.02 seconds
Started May 14 01:30:32 PM PDT 24
Finished May 14 01:30:49 PM PDT 24
Peak memory 266280 kb
Host smart-3a55fa7b-ab63-479e-a840-6742076c4adb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022603628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4022603628
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2388538624
Short name T417
Test name
Test status
Simulation time 326991102 ps
CPU time 11.03 seconds
Started May 14 01:30:36 PM PDT 24
Finished May 14 01:30:48 PM PDT 24
Peak memory 248708 kb
Host smart-4f0cdc7f-0082-4c56-8290-85cd28fee559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
38624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2388538624
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3294304024
Short name T405
Test name
Test status
Simulation time 5725890527 ps
CPU time 22.05 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:30:58 PM PDT 24
Peak memory 248780 kb
Host smart-3e21d7fc-dbeb-45dd-9987-cd5eea47fe11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943
04024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3294304024
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.576292954
Short name T199
Test name
Test status
Simulation time 82097786 ps
CPU time 3.86 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:10 PM PDT 24
Peak memory 248912 kb
Host smart-a36f9bae-4f47-4526-9e6e-472222ba60d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=576292954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.576292954
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1906695862
Short name T349
Test name
Test status
Simulation time 266748976902 ps
CPU time 2032.27 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 02:04:58 PM PDT 24
Peak memory 273352 kb
Host smart-7c726d63-6d02-4ec6-b1ca-a691f96b64eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906695862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1906695862
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1153862879
Short name T581
Test name
Test status
Simulation time 1546901419 ps
CPU time 66.92 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:32:14 PM PDT 24
Peak memory 256692 kb
Host smart-33f51779-6f35-4245-8a5e-5b61ea2b9781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
62879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1153862879
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2542828351
Short name T401
Test name
Test status
Simulation time 291100275 ps
CPU time 24.13 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:31:29 PM PDT 24
Peak memory 248736 kb
Host smart-d9d5daf5-a10f-4997-aa33-fab91a2cca39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25428
28351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2542828351
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2187379761
Short name T302
Test name
Test status
Simulation time 33529315550 ps
CPU time 860.46 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:45:24 PM PDT 24
Peak memory 267240 kb
Host smart-a63f39e9-56db-4669-a7e4-88e7bbd4331d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187379761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2187379761
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4226276886
Short name T579
Test name
Test status
Simulation time 37520586403 ps
CPU time 2482.46 seconds
Started May 14 01:31:06 PM PDT 24
Finished May 14 02:12:31 PM PDT 24
Peak memory 289168 kb
Host smart-1c5f73f4-c545-4659-bb89-260c2859450f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226276886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4226276886
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1294185877
Short name T295
Test name
Test status
Simulation time 10091428287 ps
CPU time 97.53 seconds
Started May 14 01:31:09 PM PDT 24
Finished May 14 01:32:48 PM PDT 24
Peak memory 248064 kb
Host smart-07692d18-0124-4871-a1cc-92097fc29269
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294185877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1294185877
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3109260646
Short name T237
Test name
Test status
Simulation time 570712741 ps
CPU time 23.07 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:30 PM PDT 24
Peak memory 249100 kb
Host smart-c3944cd5-f67d-4f51-be4b-e96a244b07a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31092
60646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3109260646
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3378568243
Short name T449
Test name
Test status
Simulation time 2857732922 ps
CPU time 44.88 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:52 PM PDT 24
Peak memory 248800 kb
Host smart-a20b0ce7-3010-4c58-afec-1b54c87f1239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785
68243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3378568243
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3289510320
Short name T86
Test name
Test status
Simulation time 603413192 ps
CPU time 36.67 seconds
Started May 14 01:31:01 PM PDT 24
Finished May 14 01:31:39 PM PDT 24
Peak memory 248992 kb
Host smart-ea1b24ae-e20d-452e-bca9-d7978eb43902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
10320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3289510320
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3483774449
Short name T498
Test name
Test status
Simulation time 610077014 ps
CPU time 9.34 seconds
Started May 14 01:31:06 PM PDT 24
Finished May 14 01:31:17 PM PDT 24
Peak memory 254444 kb
Host smart-d3f10094-c9f0-44e4-8c67-2f0d16c808fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34837
74449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3483774449
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2555306906
Short name T264
Test name
Test status
Simulation time 858972804 ps
CPU time 86.61 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:32:32 PM PDT 24
Peak memory 256736 kb
Host smart-5ef58607-2fed-4778-acae-d4498f12f3f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555306906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2555306906
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.4109187222
Short name T204
Test name
Test status
Simulation time 16078817 ps
CPU time 2.5 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:09 PM PDT 24
Peak memory 248904 kb
Host smart-f2b426e1-ff3b-4e38-8892-e97159887920
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4109187222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.4109187222
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2880077566
Short name T380
Test name
Test status
Simulation time 192649928690 ps
CPU time 2896.43 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 02:19:21 PM PDT 24
Peak memory 288088 kb
Host smart-502be93b-2ae3-4ead-bc75-265c626a2ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880077566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2880077566
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1979695310
Short name T604
Test name
Test status
Simulation time 257486254 ps
CPU time 12.88 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:19 PM PDT 24
Peak memory 240536 kb
Host smart-1f2eb3e8-997b-41c9-a059-8e07a780317d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1979695310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1979695310
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3734080816
Short name T180
Test name
Test status
Simulation time 1114115783 ps
CPU time 48.92 seconds
Started May 14 01:31:02 PM PDT 24
Finished May 14 01:31:52 PM PDT 24
Peak memory 256952 kb
Host smart-31fff962-a3ec-4ae3-a4a6-87abdeeca3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
80816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3734080816
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3926152408
Short name T548
Test name
Test status
Simulation time 652251017 ps
CPU time 41.71 seconds
Started May 14 01:31:02 PM PDT 24
Finished May 14 01:31:44 PM PDT 24
Peak memory 256020 kb
Host smart-3c9219cf-67f9-45e4-ace8-ea840fa003f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39261
52408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3926152408
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3272052779
Short name T184
Test name
Test status
Simulation time 23418442756 ps
CPU time 1294.1 seconds
Started May 14 01:31:06 PM PDT 24
Finished May 14 01:52:42 PM PDT 24
Peak memory 273248 kb
Host smart-f8fc19eb-025c-4151-9ed0-315d8c19e09f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272052779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3272052779
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.17381927
Short name T258
Test name
Test status
Simulation time 410567419 ps
CPU time 37.7 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:31:43 PM PDT 24
Peak memory 248740 kb
Host smart-34045ac8-6312-4812-bf04-9d7d1229cb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17381
927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.17381927
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4191426225
Short name T363
Test name
Test status
Simulation time 763611733 ps
CPU time 25.72 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:31:31 PM PDT 24
Peak memory 249184 kb
Host smart-bad4f7be-a798-4fec-905d-16bacd0c21fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41914
26225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4191426225
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3610239804
Short name T442
Test name
Test status
Simulation time 1693566789 ps
CPU time 28.89 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:36 PM PDT 24
Peak memory 248736 kb
Host smart-ca72260b-84a5-44d7-8767-9c519bd356bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
39804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3610239804
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3460003387
Short name T1
Test name
Test status
Simulation time 30289818024 ps
CPU time 1932.64 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 02:03:20 PM PDT 24
Peak memory 298008 kb
Host smart-f7f80d54-7540-47ff-811a-bd6e3bbbc119
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460003387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3460003387
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3178040905
Short name T270
Test name
Test status
Simulation time 43144302660 ps
CPU time 4565.37 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 02:47:12 PM PDT 24
Peak memory 338164 kb
Host smart-7c6d1c9c-1ac5-4b8a-86ee-3e1e3fcc8e81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178040905 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3178040905
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.238449696
Short name T194
Test name
Test status
Simulation time 183936354 ps
CPU time 4.37 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:31:10 PM PDT 24
Peak memory 248864 kb
Host smart-69c4ea67-e21b-4bdb-a07b-fbf4ea892622
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=238449696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.238449696
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2944845077
Short name T60
Test name
Test status
Simulation time 29606748402 ps
CPU time 696.62 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:42:43 PM PDT 24
Peak memory 273320 kb
Host smart-250ea7d3-1280-4ac4-bffd-c447bc960035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944845077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2944845077
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3884434378
Short name T374
Test name
Test status
Simulation time 565051658 ps
CPU time 25.39 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:33 PM PDT 24
Peak memory 240464 kb
Host smart-c6ad621d-33d5-4562-b27f-bdfa24e0e0a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3884434378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3884434378
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4284847530
Short name T330
Test name
Test status
Simulation time 42431145 ps
CPU time 3.77 seconds
Started May 14 01:31:02 PM PDT 24
Finished May 14 01:31:07 PM PDT 24
Peak memory 239108 kb
Host smart-e8c0e991-13aa-44be-8317-589269f9862f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42848
47530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4284847530
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4009146648
Short name T583
Test name
Test status
Simulation time 950291020 ps
CPU time 53.34 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:32:00 PM PDT 24
Peak memory 255984 kb
Host smart-c3f95f0d-e6ea-4903-85f6-fdd8e46a4d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
46648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4009146648
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3067833287
Short name T609
Test name
Test status
Simulation time 113196319738 ps
CPU time 1675.65 seconds
Started May 14 01:31:06 PM PDT 24
Finished May 14 01:59:04 PM PDT 24
Peak memory 265220 kb
Host smart-952728ba-6ed6-4f38-ad21-52488d636b6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067833287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3067833287
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.486213636
Short name T561
Test name
Test status
Simulation time 1412228908 ps
CPU time 47.53 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 01:31:54 PM PDT 24
Peak memory 248712 kb
Host smart-998e58f4-6d21-4cf4-95d0-8654aca80ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48621
3636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.486213636
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4129130141
Short name T257
Test name
Test status
Simulation time 2588339479 ps
CPU time 26.55 seconds
Started May 14 01:31:02 PM PDT 24
Finished May 14 01:31:30 PM PDT 24
Peak memory 248832 kb
Host smart-ef4d6e5e-74db-4f22-ba1f-54697b9905eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41291
30141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4129130141
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.79968026
Short name T453
Test name
Test status
Simulation time 166676003 ps
CPU time 6.06 seconds
Started May 14 01:31:09 PM PDT 24
Finished May 14 01:31:17 PM PDT 24
Peak memory 250660 kb
Host smart-7d963ab5-4bbb-4692-adac-fbb7b5c35846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79968
026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.79968026
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.694266621
Short name T473
Test name
Test status
Simulation time 251238367 ps
CPU time 19.57 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:31:23 PM PDT 24
Peak memory 248720 kb
Host smart-e235cf68-e6ba-435e-ae8c-2ce2835789b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69426
6621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.694266621
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2504112336
Short name T274
Test name
Test status
Simulation time 147144720139 ps
CPU time 4170.84 seconds
Started May 14 01:31:04 PM PDT 24
Finished May 14 02:40:38 PM PDT 24
Peak memory 338952 kb
Host smart-1d8560bf-5704-4a99-aa80-39df0027ce09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504112336 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2504112336
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.507479122
Short name T207
Test name
Test status
Simulation time 58905528 ps
CPU time 4.37 seconds
Started May 14 01:31:09 PM PDT 24
Finished May 14 01:31:15 PM PDT 24
Peak memory 248880 kb
Host smart-e6d99413-3b10-4fd3-be8f-60af79d7d2ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=507479122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.507479122
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2219245715
Short name T628
Test name
Test status
Simulation time 17349449134 ps
CPU time 1703.89 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:59:36 PM PDT 24
Peak memory 288808 kb
Host smart-b0fd95d4-c2c0-4aab-b47f-297cbf73b530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219245715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2219245715
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3460789757
Short name T467
Test name
Test status
Simulation time 190438023 ps
CPU time 6.47 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:31:22 PM PDT 24
Peak memory 248728 kb
Host smart-8e470b92-b8ad-40e2-b854-e92faadb909c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3460789757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3460789757
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3043118306
Short name T211
Test name
Test status
Simulation time 3710976563 ps
CPU time 97.94 seconds
Started May 14 01:31:03 PM PDT 24
Finished May 14 01:32:42 PM PDT 24
Peak memory 256936 kb
Host smart-ca161d6b-1087-465d-b365-048ff7beed2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30431
18306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3043118306
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.103745985
Short name T627
Test name
Test status
Simulation time 299454915 ps
CPU time 6.87 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:14 PM PDT 24
Peak memory 248756 kb
Host smart-ae183ede-1d5a-4274-aeda-a0f066f52a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374
5985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.103745985
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4030561039
Short name T282
Test name
Test status
Simulation time 39476623504 ps
CPU time 2325.7 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 02:10:00 PM PDT 24
Peak memory 273428 kb
Host smart-2798080e-09de-4705-a92d-cff5dafd2dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030561039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4030561039
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2690614373
Short name T443
Test name
Test status
Simulation time 164500298554 ps
CPU time 2349.43 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 281092 kb
Host smart-6546ee8a-8435-414c-bf6f-99f6cddb8c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690614373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2690614373
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1502567730
Short name T531
Test name
Test status
Simulation time 13500038065 ps
CPU time 305.61 seconds
Started May 14 01:31:15 PM PDT 24
Finished May 14 01:36:21 PM PDT 24
Peak memory 246968 kb
Host smart-8d577c95-59cc-480c-8c07-6348c2813d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502567730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1502567730
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3722248174
Short name T470
Test name
Test status
Simulation time 80611558 ps
CPU time 9.91 seconds
Started May 14 01:31:06 PM PDT 24
Finished May 14 01:31:18 PM PDT 24
Peak memory 254904 kb
Host smart-03624c1d-93af-4509-b4c6-f7cf4e0f95b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37222
48174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3722248174
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2679939270
Short name T411
Test name
Test status
Simulation time 311288699 ps
CPU time 27.65 seconds
Started May 14 01:31:01 PM PDT 24
Finished May 14 01:31:30 PM PDT 24
Peak memory 256016 kb
Host smart-ade1f91c-9f5d-4735-b2f0-3185669cd6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26799
39270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2679939270
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2104409416
Short name T278
Test name
Test status
Simulation time 281520197 ps
CPU time 31.55 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:31:47 PM PDT 24
Peak memory 248724 kb
Host smart-a045e0c9-c946-437d-80e0-cfcadc94ca18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044
09416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2104409416
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.359058314
Short name T462
Test name
Test status
Simulation time 2375519068 ps
CPU time 48.92 seconds
Started May 14 01:31:05 PM PDT 24
Finished May 14 01:31:56 PM PDT 24
Peak memory 248752 kb
Host smart-86883feb-0d55-4a50-bfc2-078fb7fa20ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
8314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.359058314
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3812055116
Short name T80
Test name
Test status
Simulation time 33399705260 ps
CPU time 2295.15 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 02:09:28 PM PDT 24
Peak memory 287504 kb
Host smart-205ad661-2e95-4e95-a605-1ed24a7b733f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812055116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3812055116
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2905900666
Short name T176
Test name
Test status
Simulation time 124447961010 ps
CPU time 6363.73 seconds
Started May 14 01:31:13 PM PDT 24
Finished May 14 03:17:19 PM PDT 24
Peak memory 355376 kb
Host smart-01f94482-d8db-4c92-9e5e-9232fc60753d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905900666 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2905900666
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.362957243
Short name T206
Test name
Test status
Simulation time 47447748 ps
CPU time 3.94 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:31:16 PM PDT 24
Peak memory 248872 kb
Host smart-01e1f73a-e818-45b0-87e2-9c0eec3de075
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=362957243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.362957243
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.185120542
Short name T16
Test name
Test status
Simulation time 11345584787 ps
CPU time 940.5 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:46:53 PM PDT 24
Peak memory 288680 kb
Host smart-5df64b6c-0e9e-4149-bf4c-be109c1a85b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185120542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.185120542
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.604557751
Short name T216
Test name
Test status
Simulation time 920274092 ps
CPU time 43.64 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:31:59 PM PDT 24
Peak memory 248736 kb
Host smart-4f3e84d0-3cf5-42d4-af28-a49367e23d64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=604557751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.604557751
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2823874261
Short name T454
Test name
Test status
Simulation time 2332980219 ps
CPU time 154.05 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:33:45 PM PDT 24
Peak memory 256912 kb
Host smart-c2fbb871-b232-42e4-881c-3cfdd13c18d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28238
74261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2823874261
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1315666824
Short name T464
Test name
Test status
Simulation time 506834817 ps
CPU time 11.95 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:25 PM PDT 24
Peak memory 254040 kb
Host smart-824cc1e8-65cb-4394-8311-ea8f73ef5e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13156
66824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1315666824
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.681716188
Short name T599
Test name
Test status
Simulation time 44287327029 ps
CPU time 1596.85 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 01:57:51 PM PDT 24
Peak memory 289696 kb
Host smart-4dcae963-9fda-4b64-b88e-51efb5c9dced
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681716188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.681716188
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.926499541
Short name T337
Test name
Test status
Simulation time 143338853280 ps
CPU time 1632.87 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:58:24 PM PDT 24
Peak memory 289524 kb
Host smart-a1f9a836-181b-4c3f-843b-4e69a4090e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926499541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.926499541
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1512307050
Short name T661
Test name
Test status
Simulation time 3382083641 ps
CPU time 134.2 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 01:33:28 PM PDT 24
Peak memory 248208 kb
Host smart-935f88c8-7ae9-482d-b87a-f4c1e92b85be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512307050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1512307050
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3087391379
Short name T444
Test name
Test status
Simulation time 400583415 ps
CPU time 27.59 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:40 PM PDT 24
Peak memory 248556 kb
Host smart-2465fadd-9039-4f81-be4c-590db6c408be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
91379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3087391379
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2849556737
Short name T430
Test name
Test status
Simulation time 5255981695 ps
CPU time 60.45 seconds
Started May 14 01:31:09 PM PDT 24
Finished May 14 01:32:11 PM PDT 24
Peak memory 255644 kb
Host smart-ce244bf7-5b2e-410b-9a2a-ea0d43df304a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
56737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2849556737
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1350184466
Short name T461
Test name
Test status
Simulation time 331497487 ps
CPU time 7.54 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:21 PM PDT 24
Peak memory 248728 kb
Host smart-f934bca9-880d-4186-917e-19c65a074536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13501
84466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1350184466
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3054394575
Short name T492
Test name
Test status
Simulation time 368224866 ps
CPU time 26.38 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 01:31:40 PM PDT 24
Peak memory 248728 kb
Host smart-d6095511-5bf1-4edd-9b0b-188eb7653bee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054394575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3054394575
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3724505800
Short name T409
Test name
Test status
Simulation time 18000358667 ps
CPU time 1243.26 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 01:51:57 PM PDT 24
Peak memory 266196 kb
Host smart-3d2c5d4d-33cc-4fbd-a23c-c8d8d386ea67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724505800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3724505800
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2498654838
Short name T638
Test name
Test status
Simulation time 190339498 ps
CPU time 11.42 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:31:27 PM PDT 24
Peak memory 240416 kb
Host smart-c42b0a6f-6758-4699-b560-dee7524d36e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2498654838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2498654838
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.101666662
Short name T358
Test name
Test status
Simulation time 192827042 ps
CPU time 16.06 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:29 PM PDT 24
Peak memory 256684 kb
Host smart-c16d1d0d-e92d-4c4e-bf6b-36883b1d8470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
6662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.101666662
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3742283207
Short name T494
Test name
Test status
Simulation time 5066498077 ps
CPU time 76.39 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:32:30 PM PDT 24
Peak memory 256988 kb
Host smart-91001e3c-67f4-4381-83b6-6db86c780cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37422
83207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3742283207
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2748846401
Short name T280
Test name
Test status
Simulation time 36510026899 ps
CPU time 2037.34 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 02:05:09 PM PDT 24
Peak memory 288096 kb
Host smart-62c5cf12-e615-4392-ac9e-7a853c13a5d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748846401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2748846401
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2535673389
Short name T415
Test name
Test status
Simulation time 128454214141 ps
CPU time 1962.21 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 02:03:58 PM PDT 24
Peak memory 272972 kb
Host smart-357a1646-4421-4bac-9df1-180fd2794170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535673389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2535673389
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2319927182
Short name T286
Test name
Test status
Simulation time 25740782972 ps
CPU time 546.77 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:40:22 PM PDT 24
Peak memory 248196 kb
Host smart-a197126f-8b58-45ee-87d6-445eacd9fab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319927182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2319927182
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.305470118
Short name T253
Test name
Test status
Simulation time 2230760782 ps
CPU time 29.65 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:31:42 PM PDT 24
Peak memory 248728 kb
Host smart-9e716711-0ae6-4690-ac31-1bb132e6be93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30547
0118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.305470118
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.99119759
Short name T40
Test name
Test status
Simulation time 1007197201 ps
CPU time 31.11 seconds
Started May 14 01:31:14 PM PDT 24
Finished May 14 01:31:47 PM PDT 24
Peak memory 255976 kb
Host smart-d8de3710-cff9-42a1-8ad5-0ca4531a36e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99119
759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.99119759
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.619506811
Short name T595
Test name
Test status
Simulation time 205075457 ps
CPU time 3.1 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:16 PM PDT 24
Peak memory 240520 kb
Host smart-f5849c94-443a-455a-a0ca-a890c04bdd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61950
6811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.619506811
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.714981753
Short name T536
Test name
Test status
Simulation time 581635376 ps
CPU time 14.64 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:28 PM PDT 24
Peak memory 248684 kb
Host smart-943220c2-83f6-476a-b6e9-6bd34d0342ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71498
1753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.714981753
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.25165661
Short name T82
Test name
Test status
Simulation time 344617864901 ps
CPU time 1439.58 seconds
Started May 14 01:31:12 PM PDT 24
Finished May 14 01:55:14 PM PDT 24
Peak memory 273364 kb
Host smart-4171e592-6050-483e-abb0-6407cc870971
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25165661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_hand
ler_stress_all.25165661
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1073635184
Short name T196
Test name
Test status
Simulation time 338862123 ps
CPU time 3.71 seconds
Started May 14 01:31:19 PM PDT 24
Finished May 14 01:31:24 PM PDT 24
Peak memory 248900 kb
Host smart-cbe550d7-684a-4f97-b6c4-fe072ef623d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1073635184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1073635184
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2313541199
Short name T92
Test name
Test status
Simulation time 126395555584 ps
CPU time 1571.36 seconds
Started May 14 01:31:17 PM PDT 24
Finished May 14 01:57:30 PM PDT 24
Peak memory 273288 kb
Host smart-a475cc81-20be-4afc-821e-a258a9dc6a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313541199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2313541199
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.256683221
Short name T483
Test name
Test status
Simulation time 445305836 ps
CPU time 7.81 seconds
Started May 14 01:31:21 PM PDT 24
Finished May 14 01:31:29 PM PDT 24
Peak memory 248704 kb
Host smart-786d4b9f-3a80-4446-9175-86dda01ff0fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=256683221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.256683221
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.390994606
Short name T41
Test name
Test status
Simulation time 1779923548 ps
CPU time 130.95 seconds
Started May 14 01:31:21 PM PDT 24
Finished May 14 01:33:33 PM PDT 24
Peak memory 256788 kb
Host smart-ad7db976-aede-4041-840d-cd183c423ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
4606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.390994606
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2221434061
Short name T436
Test name
Test status
Simulation time 371567180 ps
CPU time 22.24 seconds
Started May 14 01:31:20 PM PDT 24
Finished May 14 01:31:43 PM PDT 24
Peak memory 248728 kb
Host smart-9bcba56f-59f5-4651-b223-3469977550fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22214
34061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2221434061
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1796187124
Short name T365
Test name
Test status
Simulation time 20105937447 ps
CPU time 1197.7 seconds
Started May 14 01:31:19 PM PDT 24
Finished May 14 01:51:18 PM PDT 24
Peak memory 281532 kb
Host smart-ecbba24d-152f-4113-86fa-2a8d1ba61ab9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796187124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1796187124
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4185971247
Short name T283
Test name
Test status
Simulation time 6740424673 ps
CPU time 281.51 seconds
Started May 14 01:31:17 PM PDT 24
Finished May 14 01:36:00 PM PDT 24
Peak memory 248192 kb
Host smart-5521c3c4-d887-4a85-840c-5fca7223aa0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185971247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4185971247
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.542050383
Short name T339
Test name
Test status
Simulation time 8566219769 ps
CPU time 41.07 seconds
Started May 14 01:31:13 PM PDT 24
Finished May 14 01:31:56 PM PDT 24
Peak memory 248944 kb
Host smart-a37d84fb-7dfb-4155-94f7-97125e1ede28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54205
0383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.542050383
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4274644076
Short name T576
Test name
Test status
Simulation time 653483079 ps
CPU time 23.79 seconds
Started May 14 01:31:11 PM PDT 24
Finished May 14 01:31:37 PM PDT 24
Peak memory 254724 kb
Host smart-990005b4-ba65-4719-8949-54d45685b3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
44076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4274644076
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2788939317
Short name T493
Test name
Test status
Simulation time 2162403960 ps
CPU time 22.35 seconds
Started May 14 01:31:17 PM PDT 24
Finished May 14 01:31:41 PM PDT 24
Peak memory 248772 kb
Host smart-583777b2-2427-44a7-9d4a-804e0929ec82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
39317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2788939317
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.906005394
Short name T516
Test name
Test status
Simulation time 3883179229 ps
CPU time 51.31 seconds
Started May 14 01:31:10 PM PDT 24
Finished May 14 01:32:02 PM PDT 24
Peak memory 248764 kb
Host smart-eba56d46-793e-4245-91f9-92e27afdc523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90600
5394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.906005394
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3865495387
Short name T97
Test name
Test status
Simulation time 7541216923 ps
CPU time 442.63 seconds
Started May 14 01:31:19 PM PDT 24
Finished May 14 01:38:43 PM PDT 24
Peak memory 256932 kb
Host smart-f6b7fc80-2317-47af-9146-d57d05bfa921
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865495387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3865495387
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3561194038
Short name T100
Test name
Test status
Simulation time 21367053902 ps
CPU time 1403.27 seconds
Started May 14 01:31:22 PM PDT 24
Finished May 14 01:54:47 PM PDT 24
Peak memory 273348 kb
Host smart-7531897e-9e77-4884-9b3f-e2ca2158e39f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561194038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3561194038
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.964191628
Short name T474
Test name
Test status
Simulation time 567714590 ps
CPU time 27.32 seconds
Started May 14 01:31:23 PM PDT 24
Finished May 14 01:31:51 PM PDT 24
Peak memory 240744 kb
Host smart-0f87d478-3b69-449f-905b-10b9490c7084
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=964191628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.964191628
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1274540753
Short name T414
Test name
Test status
Simulation time 5139759561 ps
CPU time 141.84 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 01:33:48 PM PDT 24
Peak memory 250420 kb
Host smart-ddc3b291-7642-4577-8684-efda9cf43021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12745
40753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1274540753
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.271025381
Short name T359
Test name
Test status
Simulation time 391367931 ps
CPU time 15.51 seconds
Started May 14 01:31:17 PM PDT 24
Finished May 14 01:31:34 PM PDT 24
Peak memory 254612 kb
Host smart-6d0fa5bc-6ddd-4434-bee8-4cc812014fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27102
5381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.271025381
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1841850139
Short name T321
Test name
Test status
Simulation time 55038940148 ps
CPU time 1255.33 seconds
Started May 14 01:31:24 PM PDT 24
Finished May 14 01:52:20 PM PDT 24
Peak memory 272964 kb
Host smart-4f3c3679-36f5-45b8-8886-866d8f1e96bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841850139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1841850139
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2125836809
Short name T416
Test name
Test status
Simulation time 121827360755 ps
CPU time 1687.45 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:59:27 PM PDT 24
Peak memory 266288 kb
Host smart-40cabf19-7fc6-4a74-a9d3-e4d22f83508f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125836809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2125836809
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.300251472
Short name T5
Test name
Test status
Simulation time 26248559451 ps
CPU time 533.12 seconds
Started May 14 01:31:23 PM PDT 24
Finished May 14 01:40:17 PM PDT 24
Peak memory 256580 kb
Host smart-a55a2482-6e84-408c-8e0d-35b3e969a68d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300251472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.300251472
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.375415635
Short name T338
Test name
Test status
Simulation time 831187781 ps
CPU time 23.91 seconds
Started May 14 01:31:20 PM PDT 24
Finished May 14 01:31:45 PM PDT 24
Peak memory 248744 kb
Host smart-1a98ec1e-75eb-45f9-a450-ca7957ca7c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541
5635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.375415635
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3156093595
Short name T109
Test name
Test status
Simulation time 753403396 ps
CPU time 49.31 seconds
Started May 14 01:31:19 PM PDT 24
Finished May 14 01:32:09 PM PDT 24
Peak memory 247668 kb
Host smart-cd0324e1-aaef-44cc-8681-cd1b657b5dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560
93595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3156093595
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2394495664
Short name T45
Test name
Test status
Simulation time 805475454 ps
CPU time 55.86 seconds
Started May 14 01:31:24 PM PDT 24
Finished May 14 01:32:21 PM PDT 24
Peak memory 248964 kb
Host smart-8a4066d2-cc98-41d6-b610-5112b40f8dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23944
95664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2394495664
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4146116093
Short name T364
Test name
Test status
Simulation time 488048874 ps
CPU time 19.76 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:31:39 PM PDT 24
Peak memory 248740 kb
Host smart-05185c9c-42c3-4a96-be32-2d51026fea92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
16093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4146116093
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3808584792
Short name T200
Test name
Test status
Simulation time 189523795 ps
CPU time 3.76 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:31:23 PM PDT 24
Peak memory 248880 kb
Host smart-4aea8cb9-ca65-410b-98bc-fdf653baf8e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3808584792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3808584792
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1773184847
Short name T481
Test name
Test status
Simulation time 9898237538 ps
CPU time 792.16 seconds
Started May 14 01:31:22 PM PDT 24
Finished May 14 01:44:35 PM PDT 24
Peak memory 265444 kb
Host smart-ab1bef49-be5e-494c-a692-06d29240d5e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773184847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1773184847
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.349356945
Short name T398
Test name
Test status
Simulation time 2848066366 ps
CPU time 33.95 seconds
Started May 14 01:31:22 PM PDT 24
Finished May 14 01:31:57 PM PDT 24
Peak memory 240544 kb
Host smart-861672c6-ba4b-4f5b-90c7-104d5d364bf9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=349356945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.349356945
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3416297313
Short name T235
Test name
Test status
Simulation time 2087666688 ps
CPU time 76.81 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:32:36 PM PDT 24
Peak memory 249824 kb
Host smart-ec42633a-2f1a-4246-bb95-bbf05d077dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162
97313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3416297313
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.90042600
Short name T485
Test name
Test status
Simulation time 495778535 ps
CPU time 15.42 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:31:35 PM PDT 24
Peak memory 256900 kb
Host smart-12a5a3d9-bacd-4a55-8a16-9b4f4a43f3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90042
600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.90042600
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.995079176
Short name T541
Test name
Test status
Simulation time 14912783511 ps
CPU time 1147.66 seconds
Started May 14 01:31:20 PM PDT 24
Finished May 14 01:50:28 PM PDT 24
Peak memory 289504 kb
Host smart-c373f91b-c305-4acb-9913-948fe5a69bc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995079176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.995079176
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3150073748
Short name T422
Test name
Test status
Simulation time 40149011529 ps
CPU time 2296.18 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 287356 kb
Host smart-462598f2-56cd-44d7-818a-f3d45b4f7ff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150073748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3150073748
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4034869858
Short name T353
Test name
Test status
Simulation time 645234389 ps
CPU time 40.86 seconds
Started May 14 01:31:17 PM PDT 24
Finished May 14 01:32:00 PM PDT 24
Peak memory 249096 kb
Host smart-3af25429-c9c1-4e5c-a9ff-322da27c6616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
69858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4034869858
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.742359525
Short name T433
Test name
Test status
Simulation time 898926624 ps
CPU time 50.97 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 01:32:17 PM PDT 24
Peak memory 255548 kb
Host smart-54f37d35-df64-46a6-b820-5e5f23ad80ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74235
9525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.742359525
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2153240564
Short name T412
Test name
Test status
Simulation time 1413017843 ps
CPU time 46.93 seconds
Started May 14 01:31:18 PM PDT 24
Finished May 14 01:32:06 PM PDT 24
Peak memory 248732 kb
Host smart-a3f20d8d-712f-46ea-9835-acd0c16ee593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21532
40564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2153240564
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2109233406
Short name T34
Test name
Test status
Simulation time 1106233774 ps
CPU time 64.67 seconds
Started May 14 01:31:22 PM PDT 24
Finished May 14 01:32:28 PM PDT 24
Peak memory 255916 kb
Host smart-f7b690b6-b8c9-402e-919b-bbdcaf7ec19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
33406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2109233406
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3944916349
Short name T277
Test name
Test status
Simulation time 91599118638 ps
CPU time 1642.63 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 01:58:49 PM PDT 24
Peak memory 289872 kb
Host smart-96d42142-be4d-4a95-acdd-d6e1dd768540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944916349 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3944916349
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1005995358
Short name T201
Test name
Test status
Simulation time 24984185 ps
CPU time 2.58 seconds
Started May 14 01:31:27 PM PDT 24
Finished May 14 01:31:31 PM PDT 24
Peak memory 248924 kb
Host smart-c624e147-ffff-474e-ae26-bdb36f35a625
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005995358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1005995358
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1464989437
Short name T256
Test name
Test status
Simulation time 98083666216 ps
CPU time 1505.8 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:56:35 PM PDT 24
Peak memory 272868 kb
Host smart-9e2d5a20-dc95-4294-8446-b04b624f5959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464989437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1464989437
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3468239039
Short name T613
Test name
Test status
Simulation time 682995157 ps
CPU time 11.17 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 01:31:38 PM PDT 24
Peak memory 248744 kb
Host smart-c254fa0b-0a20-46da-880b-1200a9f4a673
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3468239039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3468239039
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2647251844
Short name T351
Test name
Test status
Simulation time 852511978 ps
CPU time 27.15 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 01:31:55 PM PDT 24
Peak memory 256020 kb
Host smart-40ea82bc-961e-4cc6-8c6f-ea3196a437af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
51844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2647251844
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.556443366
Short name T538
Test name
Test status
Simulation time 1344630531 ps
CPU time 49.25 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:32:18 PM PDT 24
Peak memory 249148 kb
Host smart-6681f092-6500-4a80-bbd9-28e8ba9fd2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55644
3366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.556443366
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.284117239
Short name T222
Test name
Test status
Simulation time 29147834978 ps
CPU time 2008.61 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 02:04:55 PM PDT 24
Peak memory 283640 kb
Host smart-f8aa173d-b525-4b68-8dac-d477d09531a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284117239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.284117239
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3407007409
Short name T529
Test name
Test status
Simulation time 41332825601 ps
CPU time 2434.13 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 02:12:04 PM PDT 24
Peak memory 288988 kb
Host smart-d791b632-4011-4bc5-88a6-c57cc3c0de02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407007409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3407007409
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2490783268
Short name T679
Test name
Test status
Simulation time 13154684725 ps
CPU time 285.53 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:36:14 PM PDT 24
Peak memory 248092 kb
Host smart-6a8198b0-1ff9-4fe9-8f14-91b28b61867f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490783268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2490783268
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2270532391
Short name T44
Test name
Test status
Simulation time 2688600768 ps
CPU time 42.61 seconds
Started May 14 01:31:27 PM PDT 24
Finished May 14 01:32:11 PM PDT 24
Peak memory 248780 kb
Host smart-38dd8a8a-b843-4816-8222-4943ebaf44f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22705
32391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2270532391
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2079007710
Short name T248
Test name
Test status
Simulation time 2164432794 ps
CPU time 60.73 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:32:30 PM PDT 24
Peak memory 248700 kb
Host smart-bba1c246-6361-47be-8369-dbf75cae92d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
07710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2079007710
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3357433781
Short name T434
Test name
Test status
Simulation time 1751410007 ps
CPU time 55.43 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:32:24 PM PDT 24
Peak memory 255580 kb
Host smart-55c2dba9-7dc0-4581-912e-38b2449381c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
33781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3357433781
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2502088786
Short name T439
Test name
Test status
Simulation time 147749071 ps
CPU time 10.36 seconds
Started May 14 01:31:29 PM PDT 24
Finished May 14 01:31:40 PM PDT 24
Peak memory 254132 kb
Host smart-98a91183-2659-496f-b6c5-784c5334b5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
88786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2502088786
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4059223094
Short name T101
Test name
Test status
Simulation time 9466955087 ps
CPU time 466.18 seconds
Started May 14 01:31:27 PM PDT 24
Finished May 14 01:39:15 PM PDT 24
Peak memory 256976 kb
Host smart-d8f754ec-04b0-496b-be28-d34bbfc925cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059223094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4059223094
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1724002148
Short name T445
Test name
Test status
Simulation time 70500717531 ps
CPU time 1199.16 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 01:51:26 PM PDT 24
Peak memory 281660 kb
Host smart-1aba6d6b-c749-4ca0-a85f-1230dd5881cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724002148 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1724002148
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3379215954
Short name T2
Test name
Test status
Simulation time 152941246 ps
CPU time 3.92 seconds
Started May 14 01:30:44 PM PDT 24
Finished May 14 01:30:49 PM PDT 24
Peak memory 248876 kb
Host smart-be62341d-e6ca-4c60-bb44-dd6db9d2334c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3379215954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3379215954
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1350422965
Short name T698
Test name
Test status
Simulation time 32869091882 ps
CPU time 1760.25 seconds
Started May 14 01:30:32 PM PDT 24
Finished May 14 01:59:56 PM PDT 24
Peak memory 273384 kb
Host smart-f2a7d1f9-8042-4aec-8bc8-c7133dcb0517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350422965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1350422965
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2156943247
Short name T476
Test name
Test status
Simulation time 770706544 ps
CPU time 10.88 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:30:59 PM PDT 24
Peak memory 240536 kb
Host smart-dfdaf3fe-853f-4b5a-b4f3-1b723a1c49ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2156943247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2156943247
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.889774139
Short name T629
Test name
Test status
Simulation time 543308716 ps
CPU time 25.27 seconds
Started May 14 01:30:30 PM PDT 24
Finished May 14 01:30:58 PM PDT 24
Peak memory 255488 kb
Host smart-c0275ecc-8808-4e04-be50-c174764a1267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88977
4139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.889774139
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3049810234
Short name T502
Test name
Test status
Simulation time 463674987 ps
CPU time 4.45 seconds
Started May 14 01:30:32 PM PDT 24
Finished May 14 01:30:39 PM PDT 24
Peak memory 240444 kb
Host smart-7a8e3785-d651-451b-ad20-65ac98801e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
10234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3049810234
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1521162813
Short name T571
Test name
Test status
Simulation time 12856648426 ps
CPU time 767.41 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:43:29 PM PDT 24
Peak memory 268232 kb
Host smart-c0ad9279-8e19-4ad4-8b8e-cdd2971246db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521162813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1521162813
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.182469385
Short name T382
Test name
Test status
Simulation time 22300794721 ps
CPU time 1106.74 seconds
Started May 14 01:30:37 PM PDT 24
Finished May 14 01:49:05 PM PDT 24
Peak memory 289088 kb
Host smart-716d15d7-36d0-4371-b76a-01094707733b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182469385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.182469385
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3961710385
Short name T290
Test name
Test status
Simulation time 5299157450 ps
CPU time 213.72 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:34:09 PM PDT 24
Peak memory 247140 kb
Host smart-8b463443-ef9c-4ea0-a4ce-0ba033b8ab04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961710385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3961710385
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.465608963
Short name T360
Test name
Test status
Simulation time 4956278543 ps
CPU time 59.25 seconds
Started May 14 01:30:36 PM PDT 24
Finished May 14 01:31:37 PM PDT 24
Peak memory 248772 kb
Host smart-b077da2c-bf0d-4a78-88bc-07eb253f1e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46560
8963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.465608963
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1769608759
Short name T673
Test name
Test status
Simulation time 718105113 ps
CPU time 17.38 seconds
Started May 14 01:30:31 PM PDT 24
Finished May 14 01:30:50 PM PDT 24
Peak memory 255408 kb
Host smart-e31c2b00-8c6a-49b0-b561-75d8ed299a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17696
08759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1769608759
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1758205127
Short name T13
Test name
Test status
Simulation time 1285756156 ps
CPU time 20.5 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:08 PM PDT 24
Peak memory 275032 kb
Host smart-299cffd2-89c9-4b49-96cc-f1de001ea841
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1758205127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1758205127
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1102634696
Short name T179
Test name
Test status
Simulation time 1107617337 ps
CPU time 66.97 seconds
Started May 14 01:30:32 PM PDT 24
Finished May 14 01:31:41 PM PDT 24
Peak memory 256744 kb
Host smart-76319123-0c47-4a80-8327-dace90b90621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
34696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1102634696
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3533559391
Short name T484
Test name
Test status
Simulation time 793260254 ps
CPU time 45.64 seconds
Started May 14 01:30:33 PM PDT 24
Finished May 14 01:31:22 PM PDT 24
Peak memory 248744 kb
Host smart-3ab6f080-f8e0-4f94-a77c-03e03de3ab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35335
59391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3533559391
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1678047443
Short name T35
Test name
Test status
Simulation time 53785126862 ps
CPU time 3341.61 seconds
Started May 14 01:31:29 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 289716 kb
Host smart-b8bb7e7a-282f-4b75-9ced-20463de777b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678047443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1678047443
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4165573108
Short name T459
Test name
Test status
Simulation time 8497101019 ps
CPU time 228.14 seconds
Started May 14 01:31:27 PM PDT 24
Finished May 14 01:35:16 PM PDT 24
Peak memory 256908 kb
Host smart-ab0a5e2b-cf32-4033-b70b-659701f693d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
73108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4165573108
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2581066845
Short name T505
Test name
Test status
Simulation time 344076789 ps
CPU time 18.21 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 01:31:46 PM PDT 24
Peak memory 248896 kb
Host smart-451d25a5-065f-4a23-949e-e8cd5b8b91ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25810
66845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2581066845
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1096470115
Short name T322
Test name
Test status
Simulation time 10185815801 ps
CPU time 960.86 seconds
Started May 14 01:31:34 PM PDT 24
Finished May 14 01:47:36 PM PDT 24
Peak memory 281792 kb
Host smart-4cd88fe5-2885-469f-a238-b4e794770335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096470115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1096470115
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1969246633
Short name T696
Test name
Test status
Simulation time 28233464232 ps
CPU time 1487.57 seconds
Started May 14 01:31:35 PM PDT 24
Finished May 14 01:56:24 PM PDT 24
Peak memory 267280 kb
Host smart-66b4efd9-ccab-4748-be12-fffbb6724e7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969246633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1969246633
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4023128414
Short name T580
Test name
Test status
Simulation time 50495845140 ps
CPU time 532.28 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 01:40:19 PM PDT 24
Peak memory 256388 kb
Host smart-38477577-ebfa-4ccd-87c5-e2acf401ccc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023128414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4023128414
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1705035099
Short name T540
Test name
Test status
Simulation time 232266846 ps
CPU time 4.86 seconds
Started May 14 01:31:29 PM PDT 24
Finished May 14 01:31:35 PM PDT 24
Peak memory 240524 kb
Host smart-e4db3db0-8202-43da-8a54-dbfed34e7712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
35099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1705035099
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3050098242
Short name T376
Test name
Test status
Simulation time 58669655 ps
CPU time 6.81 seconds
Started May 14 01:31:25 PM PDT 24
Finished May 14 01:31:33 PM PDT 24
Peak memory 254340 kb
Host smart-45996c02-1775-4047-85ba-d37468d9f68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
98242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3050098242
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1121466865
Short name T479
Test name
Test status
Simulation time 1145983817 ps
CPU time 45.98 seconds
Started May 14 01:31:26 PM PDT 24
Finished May 14 01:32:13 PM PDT 24
Peak memory 248596 kb
Host smart-84b7034b-1419-4fd3-aa73-add7df6f0a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
66865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1121466865
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1587090379
Short name T343
Test name
Test status
Simulation time 549088842 ps
CPU time 29.73 seconds
Started May 14 01:31:28 PM PDT 24
Finished May 14 01:31:59 PM PDT 24
Peak memory 255884 kb
Host smart-2aad29e3-50a8-46d7-835b-33fb491b610d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
90379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1587090379
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3411418865
Short name T104
Test name
Test status
Simulation time 21979041257 ps
CPU time 543.78 seconds
Started May 14 01:31:34 PM PDT 24
Finished May 14 01:40:39 PM PDT 24
Peak memory 265184 kb
Host smart-7ec4a0a9-9d36-48f3-b881-3c95b41119c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411418865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3411418865
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3368633767
Short name T55
Test name
Test status
Simulation time 287629178787 ps
CPU time 4681.95 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 02:49:37 PM PDT 24
Peak memory 305744 kb
Host smart-a356ff03-c898-4bfa-b553-be0c5daef90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368633767 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3368633767
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1616167804
Short name T400
Test name
Test status
Simulation time 40722463906 ps
CPU time 1036.03 seconds
Started May 14 01:31:36 PM PDT 24
Finished May 14 01:48:53 PM PDT 24
Peak memory 273392 kb
Host smart-9a08feed-6542-4e40-be80-95c8ed6cbf8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616167804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1616167804
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3387524835
Short name T404
Test name
Test status
Simulation time 1770820381 ps
CPU time 17.39 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 01:31:52 PM PDT 24
Peak memory 255948 kb
Host smart-77f2ee08-7a66-4bca-9db4-c227a16aca66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33875
24835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3387524835
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2459013493
Short name T660
Test name
Test status
Simulation time 837114847 ps
CPU time 34.33 seconds
Started May 14 01:31:35 PM PDT 24
Finished May 14 01:32:11 PM PDT 24
Peak memory 255892 kb
Host smart-6042fd3d-dba9-470b-8bfb-4adbc4b2b66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590
13493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2459013493
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.167110010
Short name T316
Test name
Test status
Simulation time 12797368867 ps
CPU time 1049.19 seconds
Started May 14 01:31:35 PM PDT 24
Finished May 14 01:49:05 PM PDT 24
Peak memory 280916 kb
Host smart-10daaeaf-ee99-46fb-b05b-abe1a8a3cbee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167110010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.167110010
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1541659164
Short name T533
Test name
Test status
Simulation time 12214094852 ps
CPU time 1360.5 seconds
Started May 14 01:31:36 PM PDT 24
Finished May 14 01:54:17 PM PDT 24
Peak memory 289200 kb
Host smart-4aa0b5e5-df74-404b-965c-760f7683049f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541659164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1541659164
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1710738469
Short name T48
Test name
Test status
Simulation time 1514650621 ps
CPU time 31.5 seconds
Started May 14 01:31:41 PM PDT 24
Finished May 14 01:32:13 PM PDT 24
Peak memory 256032 kb
Host smart-73081656-b9ab-47a9-b428-8f27795895a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
38469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1710738469
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.408153075
Short name T682
Test name
Test status
Simulation time 213117196 ps
CPU time 20.37 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 01:31:54 PM PDT 24
Peak memory 255588 kb
Host smart-0d8eea76-e17d-4842-a6b3-1c8907cb234e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40815
3075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.408153075
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3019268948
Short name T534
Test name
Test status
Simulation time 520102315 ps
CPU time 37.22 seconds
Started May 14 01:31:34 PM PDT 24
Finished May 14 01:32:12 PM PDT 24
Peak memory 255320 kb
Host smart-4be57d9e-08d1-473d-8dca-83861aac7a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30192
68948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3019268948
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3048482426
Short name T621
Test name
Test status
Simulation time 827383440 ps
CPU time 16.16 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 01:31:50 PM PDT 24
Peak memory 248688 kb
Host smart-08e42ebf-af82-43c8-bf20-330bc20377b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
82426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3048482426
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3540104206
Short name T73
Test name
Test status
Simulation time 110200357689 ps
CPU time 1699.74 seconds
Started May 14 01:31:33 PM PDT 24
Finished May 14 01:59:54 PM PDT 24
Peak memory 273344 kb
Host smart-c99721d6-1601-4008-a995-8e25b1456d8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540104206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3540104206
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3422218862
Short name T90
Test name
Test status
Simulation time 193623551225 ps
CPU time 2957.95 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 281592 kb
Host smart-aebd18d7-3a8d-4541-97d3-643e4bb38642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422218862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3422218862
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1678787509
Short name T475
Test name
Test status
Simulation time 1323914295 ps
CPU time 45.32 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:32:31 PM PDT 24
Peak memory 255684 kb
Host smart-e63b360f-5a80-454e-a76f-5fe7d9cf5322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16787
87509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1678787509
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2836935009
Short name T478
Test name
Test status
Simulation time 1702463316 ps
CPU time 23.4 seconds
Started May 14 01:31:37 PM PDT 24
Finished May 14 01:32:01 PM PDT 24
Peak memory 248800 kb
Host smart-75ed17a1-aead-4335-9b6c-db6b8bf8c871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
35009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2836935009
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2398148349
Short name T318
Test name
Test status
Simulation time 19922665160 ps
CPU time 1413.47 seconds
Started May 14 01:31:42 PM PDT 24
Finished May 14 01:55:17 PM PDT 24
Peak memory 286200 kb
Host smart-4cc6dbae-92e2-4866-bcab-d3c011eca458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398148349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2398148349
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.515773433
Short name T486
Test name
Test status
Simulation time 139450568320 ps
CPU time 2162 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 02:07:47 PM PDT 24
Peak memory 271656 kb
Host smart-b708e8c1-9aa3-4328-88ee-bc448fb48986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515773433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.515773433
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.116802816
Short name T567
Test name
Test status
Simulation time 123760922786 ps
CPU time 578.99 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:41:23 PM PDT 24
Peak memory 248228 kb
Host smart-4f00dab8-0638-4e24-8fb3-fa92e751d597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116802816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.116802816
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.883182392
Short name T369
Test name
Test status
Simulation time 137190356 ps
CPU time 9.35 seconds
Started May 14 01:31:36 PM PDT 24
Finished May 14 01:31:47 PM PDT 24
Peak memory 248708 kb
Host smart-66fbf46a-cc1a-4f4f-bb2c-5d62fb5a7601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88318
2392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.883182392
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.835142039
Short name T656
Test name
Test status
Simulation time 809551176 ps
CPU time 16.44 seconds
Started May 14 01:31:36 PM PDT 24
Finished May 14 01:31:53 PM PDT 24
Peak memory 248692 kb
Host smart-484f186d-e4b3-4466-9c2e-d7f39c01c24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83514
2039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.835142039
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1911624707
Short name T373
Test name
Test status
Simulation time 1226221810 ps
CPU time 21.29 seconds
Started May 14 01:31:44 PM PDT 24
Finished May 14 01:32:08 PM PDT 24
Peak memory 248836 kb
Host smart-7ff68880-960b-4232-9399-e58d05951763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19116
24707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1911624707
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2106273030
Short name T469
Test name
Test status
Simulation time 2168071488 ps
CPU time 37.37 seconds
Started May 14 01:31:34 PM PDT 24
Finished May 14 01:32:13 PM PDT 24
Peak memory 256952 kb
Host smart-7dbfb2e3-9c3f-4353-9b58-fe998f36a0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21062
73030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2106273030
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1690547180
Short name T260
Test name
Test status
Simulation time 69134687912 ps
CPU time 2139.51 seconds
Started May 14 01:31:45 PM PDT 24
Finished May 14 02:07:27 PM PDT 24
Peak memory 289516 kb
Host smart-85c613bd-9984-44ce-adba-71867b14f512
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690547180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1690547180
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.317721074
Short name T219
Test name
Test status
Simulation time 264146914737 ps
CPU time 2398.82 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 02:11:45 PM PDT 24
Peak memory 289408 kb
Host smart-07f07be5-6ce3-4beb-bf97-dae1095732a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317721074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.317721074
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1052049176
Short name T426
Test name
Test status
Simulation time 21907943783 ps
CPU time 283.27 seconds
Started May 14 01:31:44 PM PDT 24
Finished May 14 01:36:30 PM PDT 24
Peak memory 257012 kb
Host smart-5623bb06-e87b-48b4-96e5-148ece6abd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
49176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1052049176
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1437523948
Short name T642
Test name
Test status
Simulation time 317659987 ps
CPU time 29.27 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:32:14 PM PDT 24
Peak memory 255944 kb
Host smart-cb619b58-bfa5-4f0f-bf3c-c23ff272613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
23948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1437523948
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.46644122
Short name T649
Test name
Test status
Simulation time 357605609121 ps
CPU time 2885.18 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 02:19:50 PM PDT 24
Peak memory 289184 kb
Host smart-24702dc3-b1b0-4522-a65f-3381eac8baa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46644122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.46644122
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2112727724
Short name T370
Test name
Test status
Simulation time 13320350365 ps
CPU time 724.33 seconds
Started May 14 01:31:46 PM PDT 24
Finished May 14 01:43:53 PM PDT 24
Peak memory 273344 kb
Host smart-58de0c6e-d6de-493a-b20a-267460dc3af3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112727724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2112727724
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.817707685
Short name T544
Test name
Test status
Simulation time 3680211144 ps
CPU time 71.37 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:32:57 PM PDT 24
Peak memory 253732 kb
Host smart-60b93030-922a-4790-aaf5-82d33f1f8c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817707685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.817707685
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.846027085
Short name T643
Test name
Test status
Simulation time 9478656921 ps
CPU time 66.41 seconds
Started May 14 01:31:46 PM PDT 24
Finished May 14 01:32:55 PM PDT 24
Peak memory 248780 kb
Host smart-2cf42176-96bb-44ac-915d-5bc6edd75ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84602
7085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.846027085
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1566951070
Short name T110
Test name
Test status
Simulation time 1618765109 ps
CPU time 31.32 seconds
Started May 14 01:31:44 PM PDT 24
Finished May 14 01:32:18 PM PDT 24
Peak memory 255944 kb
Host smart-ed4eddbf-0381-4a1f-b061-435c72d5f149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
51070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1566951070
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2482257731
Short name T586
Test name
Test status
Simulation time 115339981 ps
CPU time 8.59 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:31:54 PM PDT 24
Peak memory 248724 kb
Host smart-02878c00-7db3-4282-8f78-99e83b5fdf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
57731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2482257731
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2738711910
Short name T577
Test name
Test status
Simulation time 76179424488 ps
CPU time 2539.03 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 02:14:05 PM PDT 24
Peak memory 289564 kb
Host smart-33726bd0-5260-4b22-86e3-3c466c13971c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738711910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2738711910
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1733170082
Short name T678
Test name
Test status
Simulation time 141761880488 ps
CPU time 2066.49 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 02:06:19 PM PDT 24
Peak memory 273396 kb
Host smart-24d8d156-d7ce-433c-84bc-17b9e2de369c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733170082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1733170082
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.646646256
Short name T210
Test name
Test status
Simulation time 2764863847 ps
CPU time 150.64 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 01:34:23 PM PDT 24
Peak memory 249160 kb
Host smart-7f620829-4f57-4c44-9441-428ebe310e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64664
6256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.646646256
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2580595144
Short name T499
Test name
Test status
Simulation time 155694031 ps
CPU time 14.44 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 01:32:06 PM PDT 24
Peak memory 253704 kb
Host smart-fb6085f2-48fe-49e9-842b-30177ac854a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
95144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2580595144
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3489816405
Short name T313
Test name
Test status
Simulation time 62923057374 ps
CPU time 1921.17 seconds
Started May 14 01:31:49 PM PDT 24
Finished May 14 02:03:52 PM PDT 24
Peak memory 281596 kb
Host smart-ef3d0b20-db7b-4f7f-a320-1c4ebdaa46cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489816405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3489816405
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.632412714
Short name T390
Test name
Test status
Simulation time 230778726710 ps
CPU time 3562.47 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 02:31:21 PM PDT 24
Peak memory 288628 kb
Host smart-d57ffa6e-e489-481e-b56b-9d6a9313b4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632412714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.632412714
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.34072684
Short name T699
Test name
Test status
Simulation time 18857803992 ps
CPU time 324.26 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 248152 kb
Host smart-48d44b80-e825-4031-8e44-fd04c8a98eb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34072684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.34072684
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1615457027
Short name T408
Test name
Test status
Simulation time 816997470 ps
CPU time 49.21 seconds
Started May 14 01:31:53 PM PDT 24
Finished May 14 01:32:43 PM PDT 24
Peak memory 248712 kb
Host smart-efbc333b-b124-4151-88f3-0556ca1ca756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16154
57027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1615457027
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.316391556
Short name T20
Test name
Test status
Simulation time 756046302 ps
CPU time 46.96 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:32:45 PM PDT 24
Peak memory 248684 kb
Host smart-413fcbaa-2191-45d5-966f-53305174a296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
1556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.316391556
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1275037343
Short name T112
Test name
Test status
Simulation time 344659127 ps
CPU time 26.85 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 01:32:19 PM PDT 24
Peak memory 256264 kb
Host smart-3554c763-6420-460d-a30c-b449c5741239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
37343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1275037343
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1384775668
Short name T354
Test name
Test status
Simulation time 4170060925 ps
CPU time 56.62 seconds
Started May 14 01:31:43 PM PDT 24
Finished May 14 01:32:42 PM PDT 24
Peak memory 256968 kb
Host smart-4815c31e-1946-4aad-99ea-8a48415c9080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847
75668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1384775668
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3124529015
Short name T396
Test name
Test status
Simulation time 26080026706 ps
CPU time 304.25 seconds
Started May 14 01:31:49 PM PDT 24
Finished May 14 01:36:55 PM PDT 24
Peak memory 256980 kb
Host smart-4f0b533c-f3bd-43c0-8242-70d0c5c01716
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124529015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3124529015
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1408902047
Short name T451
Test name
Test status
Simulation time 18034217374 ps
CPU time 1560.36 seconds
Started May 14 01:31:51 PM PDT 24
Finished May 14 01:57:53 PM PDT 24
Peak memory 289448 kb
Host smart-d7787194-ee8e-497e-b563-56e8614f5506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408902047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1408902047
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.464708743
Short name T550
Test name
Test status
Simulation time 116207756 ps
CPU time 8.76 seconds
Started May 14 01:31:52 PM PDT 24
Finished May 14 01:32:01 PM PDT 24
Peak memory 254164 kb
Host smart-5e03c2f6-ecc0-4c93-9f60-3537d68649a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46470
8743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.464708743
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1624732561
Short name T385
Test name
Test status
Simulation time 268894109 ps
CPU time 25.7 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 01:32:17 PM PDT 24
Peak memory 248692 kb
Host smart-7e05d8c4-3517-4dd8-afe8-04ed03caf405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16247
32561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1624732561
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.434193853
Short name T554
Test name
Test status
Simulation time 238329456798 ps
CPU time 2009.98 seconds
Started May 14 01:31:53 PM PDT 24
Finished May 14 02:05:24 PM PDT 24
Peak memory 286980 kb
Host smart-b306cdce-3ebe-49d8-a047-3d3d1a6f787d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434193853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.434193853
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.688989162
Short name T387
Test name
Test status
Simulation time 26902120824 ps
CPU time 1935.53 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 02:04:07 PM PDT 24
Peak memory 288916 kb
Host smart-d6dc54b5-927e-450b-aed9-310dae84f61a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688989162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.688989162
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.7802701
Short name T63
Test name
Test status
Simulation time 1241264319 ps
CPU time 40.71 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 01:32:32 PM PDT 24
Peak memory 248712 kb
Host smart-0bd8d437-9e29-4550-b763-d1b4dbdf33b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78027
01 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.7802701
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1643688306
Short name T652
Test name
Test status
Simulation time 6315776547 ps
CPU time 39.28 seconds
Started May 14 01:31:48 PM PDT 24
Finished May 14 01:32:29 PM PDT 24
Peak memory 253972 kb
Host smart-24a0b476-3c89-430b-a23e-c021d7ebf454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
88306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1643688306
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1370644334
Short name T273
Test name
Test status
Simulation time 1220219730 ps
CPU time 27.2 seconds
Started May 14 01:31:53 PM PDT 24
Finished May 14 01:32:21 PM PDT 24
Peak memory 248708 kb
Host smart-b2417eb5-b85a-4698-985b-0439321d8e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13706
44334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1370644334
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.637774655
Short name T333
Test name
Test status
Simulation time 995865270 ps
CPU time 53.54 seconds
Started May 14 01:31:56 PM PDT 24
Finished May 14 01:32:50 PM PDT 24
Peak memory 248740 kb
Host smart-378355b7-cbb6-4843-8ac6-2e3116ff4c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63777
4655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.637774655
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1688474187
Short name T52
Test name
Test status
Simulation time 260899602199 ps
CPU time 3500.49 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 02:30:12 PM PDT 24
Peak memory 297236 kb
Host smart-726903c8-83cf-4e78-b6d8-731cdc0ed06e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688474187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1688474187
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3979457050
Short name T178
Test name
Test status
Simulation time 22368041331 ps
CPU time 667.38 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:43:07 PM PDT 24
Peak memory 265140 kb
Host smart-21020ff2-13ba-4e2d-8b66-36f69e2d9fa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979457050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3979457050
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3192895147
Short name T243
Test name
Test status
Simulation time 4375924678 ps
CPU time 69.59 seconds
Started May 14 01:31:53 PM PDT 24
Finished May 14 01:33:03 PM PDT 24
Peak memory 249000 kb
Host smart-e1048402-940e-4318-8eb8-fbb2ec446f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31928
95147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3192895147
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.160968973
Short name T692
Test name
Test status
Simulation time 849640423 ps
CPU time 51.07 seconds
Started May 14 01:31:56 PM PDT 24
Finished May 14 01:32:47 PM PDT 24
Peak memory 255956 kb
Host smart-456dca33-3dc3-47fa-81dc-3e08fdd09cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
8973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.160968973
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1251076808
Short name T255
Test name
Test status
Simulation time 60562503939 ps
CPU time 3188.86 seconds
Started May 14 01:32:00 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 289376 kb
Host smart-31e9f387-e8dc-425f-8683-7cfc37da2e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251076808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1251076808
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4040414579
Short name T431
Test name
Test status
Simulation time 31283054184 ps
CPU time 2086.21 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 02:06:44 PM PDT 24
Peak memory 284820 kb
Host smart-71ae95e9-4147-4caa-9c73-b5502350ca05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040414579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4040414579
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2585154367
Short name T546
Test name
Test status
Simulation time 83003739579 ps
CPU time 393.13 seconds
Started May 14 01:32:00 PM PDT 24
Finished May 14 01:38:34 PM PDT 24
Peak memory 248192 kb
Host smart-25603eba-2f45-4052-8481-28b16b1891a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585154367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2585154367
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1563642842
Short name T477
Test name
Test status
Simulation time 1218257742 ps
CPU time 24.88 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:25 PM PDT 24
Peak memory 248688 kb
Host smart-de1313eb-b43e-4419-82e0-cb3b95c1e4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15636
42842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1563642842
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.380322547
Short name T564
Test name
Test status
Simulation time 754313478 ps
CPU time 60.45 seconds
Started May 14 01:31:50 PM PDT 24
Finished May 14 01:32:51 PM PDT 24
Peak memory 249016 kb
Host smart-321b1889-9738-4971-90c6-a18d782af1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032
2547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.380322547
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1345099742
Short name T62
Test name
Test status
Simulation time 863277362 ps
CPU time 12.42 seconds
Started May 14 01:31:54 PM PDT 24
Finished May 14 01:32:07 PM PDT 24
Peak memory 254220 kb
Host smart-c217465e-2d1b-4fcf-a234-d0e925507f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13450
99742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1345099742
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2756371585
Short name T547
Test name
Test status
Simulation time 17521020 ps
CPU time 3.42 seconds
Started May 14 01:31:52 PM PDT 24
Finished May 14 01:31:56 PM PDT 24
Peak memory 240548 kb
Host smart-ce45d6ec-dbaa-4eb4-8fdf-f0959d635146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
71585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2756371585
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2730930716
Short name T247
Test name
Test status
Simulation time 31500663870 ps
CPU time 1814.79 seconds
Started May 14 01:31:59 PM PDT 24
Finished May 14 02:02:15 PM PDT 24
Peak memory 289360 kb
Host smart-fe99ea12-a415-445f-8815-aa1d68ab44bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730930716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2730930716
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2046567851
Short name T456
Test name
Test status
Simulation time 32530173207 ps
CPU time 2025.9 seconds
Started May 14 01:31:59 PM PDT 24
Finished May 14 02:05:46 PM PDT 24
Peak memory 281624 kb
Host smart-af01d695-2662-4160-8682-e6bd1980135b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046567851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2046567851
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.761815686
Short name T676
Test name
Test status
Simulation time 118940891 ps
CPU time 9.67 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:32:08 PM PDT 24
Peak memory 254112 kb
Host smart-bdc68158-302a-4cc8-a09a-76594aa9a42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76181
5686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.761815686
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1112851170
Short name T403
Test name
Test status
Simulation time 652803690 ps
CPU time 20.42 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:20 PM PDT 24
Peak memory 255960 kb
Host smart-d79ab76d-d8d1-4337-97d8-8000a56cf8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
51170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1112851170
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3360171348
Short name T683
Test name
Test status
Simulation time 156715185870 ps
CPU time 2270.19 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 02:09:50 PM PDT 24
Peak memory 285300 kb
Host smart-55a80499-bd1f-46ab-91a5-f447aec34956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360171348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3360171348
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3807927183
Short name T610
Test name
Test status
Simulation time 51851240932 ps
CPU time 3142.92 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 02:24:21 PM PDT 24
Peak memory 281612 kb
Host smart-28e31131-38d0-4b97-971e-346fbd2c9457
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807927183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3807927183
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3903969956
Short name T665
Test name
Test status
Simulation time 52195819098 ps
CPU time 400.11 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:38:38 PM PDT 24
Peak memory 254812 kb
Host smart-a0018ce5-91fa-4edd-8b0c-d4238f83062a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903969956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3903969956
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3681232187
Short name T630
Test name
Test status
Simulation time 772889116 ps
CPU time 42.13 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:42 PM PDT 24
Peak memory 248752 kb
Host smart-ed5ca3bb-8507-45a5-b17a-fa206010ac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
32187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3681232187
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3763179209
Short name T651
Test name
Test status
Simulation time 209177820 ps
CPU time 18.22 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:32:16 PM PDT 24
Peak memory 255420 kb
Host smart-c9e3d4f2-0c37-478b-b5f1-febb21dac620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631
79209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3763179209
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1605084984
Short name T504
Test name
Test status
Simulation time 714995761 ps
CPU time 42.2 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:42 PM PDT 24
Peak memory 254972 kb
Host smart-670b4b24-e993-4810-881f-fdad706e72f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16050
84984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1605084984
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3679522576
Short name T480
Test name
Test status
Simulation time 352197070 ps
CPU time 23.15 seconds
Started May 14 01:32:01 PM PDT 24
Finished May 14 01:32:25 PM PDT 24
Peak memory 248680 kb
Host smart-16c7b457-d9c0-4ed1-bdb5-fb36282d5930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
22576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3679522576
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.492537919
Short name T79
Test name
Test status
Simulation time 72559543038 ps
CPU time 779.73 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:45:00 PM PDT 24
Peak memory 273432 kb
Host smart-7b66a29a-b862-40dd-9187-4d3645e886b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492537919 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.492537919
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.308289196
Short name T251
Test name
Test status
Simulation time 69754168563 ps
CPU time 2237.08 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 284780 kb
Host smart-3edd662d-a0ae-4940-b8ad-6c260cb52358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308289196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.308289196
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1412117674
Short name T336
Test name
Test status
Simulation time 360993330 ps
CPU time 17.96 seconds
Started May 14 01:32:06 PM PDT 24
Finished May 14 01:32:25 PM PDT 24
Peak memory 256036 kb
Host smart-0b5c5bc3-b541-4b7b-b4b1-fa297c87e91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14121
17674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1412117674
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2220556114
Short name T532
Test name
Test status
Simulation time 325976355 ps
CPU time 8.12 seconds
Started May 14 01:32:08 PM PDT 24
Finished May 14 01:32:17 PM PDT 24
Peak memory 248748 kb
Host smart-f405f5f7-b484-4744-b866-98ed6f92f110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22205
56114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2220556114
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1854073950
Short name T600
Test name
Test status
Simulation time 25021861183 ps
CPU time 1554.47 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 01:58:08 PM PDT 24
Peak memory 273276 kb
Host smart-98277fbb-8c5d-4fa0-9484-fe43ec249710
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854073950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1854073950
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2440079808
Short name T218
Test name
Test status
Simulation time 72029604766 ps
CPU time 340.33 seconds
Started May 14 01:32:07 PM PDT 24
Finished May 14 01:37:48 PM PDT 24
Peak memory 248148 kb
Host smart-fc212ef0-caae-4587-ac6f-f582564c7b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440079808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2440079808
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2399036027
Short name T501
Test name
Test status
Simulation time 2251372530 ps
CPU time 31.7 seconds
Started May 14 01:31:57 PM PDT 24
Finished May 14 01:32:30 PM PDT 24
Peak memory 248784 kb
Host smart-a60cb1a0-559f-49b0-9341-ba6134d4d876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
36027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2399036027
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1423401767
Short name T592
Test name
Test status
Simulation time 1441649955 ps
CPU time 32.09 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:32 PM PDT 24
Peak memory 248724 kb
Host smart-6ca26570-fb5a-498b-8252-9eb20ba0b77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
01767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1423401767
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3345564575
Short name T585
Test name
Test status
Simulation time 467161116 ps
CPU time 27.89 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 01:32:33 PM PDT 24
Peak memory 255904 kb
Host smart-42310a47-a1d5-4846-a859-4112bcb2b0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33455
64575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3345564575
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2399882588
Short name T697
Test name
Test status
Simulation time 531255016 ps
CPU time 23.53 seconds
Started May 14 01:31:58 PM PDT 24
Finished May 14 01:32:23 PM PDT 24
Peak memory 248716 kb
Host smart-33b2f32b-68c7-4d7a-81f9-080f5afcf8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23998
82588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2399882588
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3648133640
Short name T102
Test name
Test status
Simulation time 75471732439 ps
CPU time 1926.9 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 02:04:14 PM PDT 24
Peak memory 299912 kb
Host smart-db12fbd4-4c6e-4ea1-a8b4-6a12502cdbc6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648133640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3648133640
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3210552902
Short name T666
Test name
Test status
Simulation time 50365791087 ps
CPU time 1479.05 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 01:56:46 PM PDT 24
Peak memory 288292 kb
Host smart-75980352-dc7c-4169-af6e-7014898112a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210552902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3210552902
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3034851039
Short name T650
Test name
Test status
Simulation time 2690693846 ps
CPU time 118.27 seconds
Started May 14 01:32:06 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 256940 kb
Host smart-d6139e2a-7ba7-4962-8bc2-098f7c4d3288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30348
51039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3034851039
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.968147772
Short name T468
Test name
Test status
Simulation time 866802879 ps
CPU time 51.6 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 01:32:57 PM PDT 24
Peak memory 248756 kb
Host smart-1eaf42f3-0f1b-4424-9d99-d01fcb14201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96814
7772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.968147772
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4040900413
Short name T578
Test name
Test status
Simulation time 117536530028 ps
CPU time 1988.97 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 02:05:15 PM PDT 24
Peak memory 281604 kb
Host smart-2f05b8dc-333b-4503-9024-20f4f64ebb09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040900413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4040900413
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.634536187
Short name T487
Test name
Test status
Simulation time 127956159414 ps
CPU time 1846.64 seconds
Started May 14 01:32:07 PM PDT 24
Finished May 14 02:02:55 PM PDT 24
Peak memory 288840 kb
Host smart-fcbd09eb-8b4c-42a1-a454-37e8cf64c31b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634536187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.634536187
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3315499674
Short name T556
Test name
Test status
Simulation time 5415436950 ps
CPU time 231.79 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 01:36:05 PM PDT 24
Peak memory 248232 kb
Host smart-f9e0b8a7-19e6-4cce-ac52-2908b1c6fcd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315499674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3315499674
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2161721764
Short name T389
Test name
Test status
Simulation time 1978460711 ps
CPU time 19.08 seconds
Started May 14 01:32:04 PM PDT 24
Finished May 14 01:32:23 PM PDT 24
Peak memory 248736 kb
Host smart-0778b63b-5cc4-429a-9964-355344a65162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
21764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2161721764
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3022031289
Short name T407
Test name
Test status
Simulation time 55335070 ps
CPU time 6.75 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 01:32:13 PM PDT 24
Peak memory 252636 kb
Host smart-ebe924e0-2e8c-43f6-a4d4-92f09340a3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
31289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3022031289
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.523975412
Short name T646
Test name
Test status
Simulation time 668704991 ps
CPU time 11.42 seconds
Started May 14 01:32:05 PM PDT 24
Finished May 14 01:32:17 PM PDT 24
Peak memory 251952 kb
Host smart-d7b35e96-e567-4cfc-9fd5-2b799b6313f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52397
5412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.523975412
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3719063112
Short name T391
Test name
Test status
Simulation time 1366199729 ps
CPU time 26.93 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 01:32:40 PM PDT 24
Peak memory 255904 kb
Host smart-1b1edf9f-fcd4-4523-9824-735815f4c7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
63112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3719063112
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.854991794
Short name T47
Test name
Test status
Simulation time 179208452258 ps
CPU time 1391.88 seconds
Started May 14 01:32:03 PM PDT 24
Finished May 14 01:55:16 PM PDT 24
Peak memory 289092 kb
Host smart-88694332-13ad-4138-9f42-a7b392757424
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854991794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.854991794
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1459620354
Short name T30
Test name
Test status
Simulation time 53044351 ps
CPU time 4.44 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:30:46 PM PDT 24
Peak memory 248840 kb
Host smart-4b8363a8-5fc5-42c5-9af4-40078faee654
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459620354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1459620354
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2531442788
Short name T594
Test name
Test status
Simulation time 108516666483 ps
CPU time 1516.63 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:56:05 PM PDT 24
Peak memory 273356 kb
Host smart-8ce0cd9f-abfc-40e6-9599-9da280e24dd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531442788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2531442788
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1557803964
Short name T465
Test name
Test status
Simulation time 938053206 ps
CPU time 40.91 seconds
Started May 14 01:30:37 PM PDT 24
Finished May 14 01:31:19 PM PDT 24
Peak memory 252424 kb
Host smart-882e260c-6c7d-4643-a9b4-8b0b61472275
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1557803964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1557803964
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2753168327
Short name T355
Test name
Test status
Simulation time 754867312 ps
CPU time 57.78 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:46 PM PDT 24
Peak memory 256692 kb
Host smart-1fafef7a-b61c-4d39-850d-9fcd78bce9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27531
68327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2753168327
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2020372409
Short name T506
Test name
Test status
Simulation time 1905290737 ps
CPU time 31.66 seconds
Started May 14 01:30:41 PM PDT 24
Finished May 14 01:31:14 PM PDT 24
Peak memory 255808 kb
Host smart-d6bbc1d2-c2fd-4e55-9cec-e192f74505c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20203
72409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2020372409
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3236898322
Short name T565
Test name
Test status
Simulation time 26479219538 ps
CPU time 1316.75 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:52:39 PM PDT 24
Peak memory 289180 kb
Host smart-268f3945-2eaf-489c-83b5-62a42e72f648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236898322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3236898322
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2575233452
Short name T662
Test name
Test status
Simulation time 72079852647 ps
CPU time 2426.4 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 02:11:08 PM PDT 24
Peak memory 289416 kb
Host smart-c07332ee-86de-4ccb-b914-860c49258ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575233452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2575233452
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1870581416
Short name T292
Test name
Test status
Simulation time 2128436019 ps
CPU time 87.35 seconds
Started May 14 01:30:44 PM PDT 24
Finished May 14 01:32:12 PM PDT 24
Peak memory 248176 kb
Host smart-a2ffe966-959c-490e-b61f-4b0b68ddcccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870581416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1870581416
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3673196954
Short name T212
Test name
Test status
Simulation time 1268782234 ps
CPU time 69.63 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:31:51 PM PDT 24
Peak memory 248768 kb
Host smart-00f21446-2772-4af8-8fa4-5a000194f222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731
96954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3673196954
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1673897687
Short name T388
Test name
Test status
Simulation time 358753760 ps
CPU time 13.32 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 01:30:53 PM PDT 24
Peak memory 256644 kb
Host smart-eaa0c7dc-6b22-4941-b0d5-025ab0f170b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
97687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1673897687
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.889568807
Short name T64
Test name
Test status
Simulation time 408028203 ps
CPU time 35.25 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:31:17 PM PDT 24
Peak memory 248700 kb
Host smart-17423f95-bd72-45d4-a129-88e8e6ead8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88956
8807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.889568807
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2373368556
Short name T342
Test name
Test status
Simulation time 8420300343 ps
CPU time 87.45 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:32:08 PM PDT 24
Peak memory 248956 kb
Host smart-38625100-d8b0-48fb-8c4e-5f844bbe7410
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373368556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2373368556
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1261974977
Short name T397
Test name
Test status
Simulation time 51661215962 ps
CPU time 1475.06 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 01:56:49 PM PDT 24
Peak memory 289016 kb
Host smart-899543b4-7bf1-41a6-88ef-61708e16fe4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261974977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1261974977
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.942651692
Short name T242
Test name
Test status
Simulation time 3120319184 ps
CPU time 90.79 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:33:45 PM PDT 24
Peak memory 248720 kb
Host smart-9ab0b475-96ba-4028-9db5-9311e10db365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94265
1692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.942651692
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1644092196
Short name T7
Test name
Test status
Simulation time 2795348437 ps
CPU time 38.69 seconds
Started May 14 01:32:12 PM PDT 24
Finished May 14 01:32:52 PM PDT 24
Peak memory 256984 kb
Host smart-f3cde1b8-9840-4fdb-b1b1-55efafe2c568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16440
92196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1644092196
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3631059655
Short name T368
Test name
Test status
Simulation time 34344428132 ps
CPU time 815.11 seconds
Started May 14 01:32:14 PM PDT 24
Finished May 14 01:45:50 PM PDT 24
Peak memory 272924 kb
Host smart-1de8c1fd-ecbb-4d06-b61f-2d9745cfcbc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631059655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3631059655
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2898065280
Short name T225
Test name
Test status
Simulation time 27820751049 ps
CPU time 424.11 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:39:19 PM PDT 24
Peak memory 248084 kb
Host smart-65d74762-0c96-4528-81f8-a0b2d0744fff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898065280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2898065280
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4098822040
Short name T689
Test name
Test status
Simulation time 51559826 ps
CPU time 4.45 seconds
Started May 14 01:32:14 PM PDT 24
Finished May 14 01:32:20 PM PDT 24
Peak memory 240552 kb
Host smart-34dbf9a5-59d3-42a1-8243-2c9ab71baf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40988
22040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4098822040
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1590763539
Short name T543
Test name
Test status
Simulation time 467832481 ps
CPU time 25.54 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:32:41 PM PDT 24
Peak memory 247528 kb
Host smart-51246c9c-ad36-4a47-9491-3738f505ac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15907
63539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1590763539
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1786825999
Short name T562
Test name
Test status
Simulation time 331031415 ps
CPU time 7.82 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:32:22 PM PDT 24
Peak memory 249788 kb
Host smart-027459b2-4c91-46fa-b2d7-59e0c7008d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
25999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1786825999
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.816544295
Short name T668
Test name
Test status
Simulation time 1151452728 ps
CPU time 18.19 seconds
Started May 14 01:32:04 PM PDT 24
Finished May 14 01:32:23 PM PDT 24
Peak memory 248764 kb
Host smart-13e88f01-660b-49cc-a50f-4c8a5fa2c1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81654
4295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.816544295
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2605916820
Short name T85
Test name
Test status
Simulation time 41950621241 ps
CPU time 1262.43 seconds
Started May 14 01:32:14 PM PDT 24
Finished May 14 01:53:18 PM PDT 24
Peak memory 289052 kb
Host smart-afa1c3b9-ca8a-41c5-b33f-6d10db67cda9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605916820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2605916820
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1826030960
Short name T99
Test name
Test status
Simulation time 16903236492 ps
CPU time 680.23 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:43:35 PM PDT 24
Peak memory 265244 kb
Host smart-42b39075-58f2-4de2-9cad-bbf1dcb6a38b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826030960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1826030960
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1978619021
Short name T332
Test name
Test status
Simulation time 40766994049 ps
CPU time 143.21 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 256016 kb
Host smart-5cb3ff61-2f20-4db2-b82d-0ed20a588f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
19021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1978619021
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3710556239
Short name T563
Test name
Test status
Simulation time 260383119 ps
CPU time 6.69 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:32:23 PM PDT 24
Peak memory 252992 kb
Host smart-1c95931f-6049-48af-a1fa-7c8305856177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105
56239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3710556239
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3724702027
Short name T495
Test name
Test status
Simulation time 27105868498 ps
CPU time 1573.46 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:58:29 PM PDT 24
Peak memory 270508 kb
Host smart-f90f459a-c60c-4083-9eec-dbb8ed08a4e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724702027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3724702027
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1217123123
Short name T293
Test name
Test status
Simulation time 17390427935 ps
CPU time 381.45 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:38:35 PM PDT 24
Peak memory 247804 kb
Host smart-d9cab311-3764-4432-8d45-8d03acbf0188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217123123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1217123123
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.615782327
Short name T33
Test name
Test status
Simulation time 1530894905 ps
CPU time 24.8 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:32:41 PM PDT 24
Peak memory 256000 kb
Host smart-f5eb2eeb-43b5-47f1-9180-15cc5417e52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61578
2327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.615782327
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1028889785
Short name T345
Test name
Test status
Simulation time 4938388064 ps
CPU time 67.14 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:33:22 PM PDT 24
Peak memory 249796 kb
Host smart-1ed5dcdd-f639-49e4-8d5e-43a762b1a247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10288
89785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1028889785
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1425844097
Short name T213
Test name
Test status
Simulation time 381536926 ps
CPU time 14.52 seconds
Started May 14 01:32:15 PM PDT 24
Finished May 14 01:32:31 PM PDT 24
Peak memory 253648 kb
Host smart-7dbc8d72-be5e-4463-9f7b-272ef07f474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258
44097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1425844097
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4005345957
Short name T410
Test name
Test status
Simulation time 1654729701 ps
CPU time 33.72 seconds
Started May 14 01:32:13 PM PDT 24
Finished May 14 01:32:48 PM PDT 24
Peak memory 248736 kb
Host smart-cc6b315b-2759-4a29-8c4c-6f42748ba1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
45957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4005345957
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4034875432
Short name T366
Test name
Test status
Simulation time 1063022308 ps
CPU time 43.55 seconds
Started May 14 01:32:30 PM PDT 24
Finished May 14 01:33:14 PM PDT 24
Peak memory 256552 kb
Host smart-e41479e2-ded2-42e5-933d-791316707a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
75432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4034875432
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.280775719
Short name T19
Test name
Test status
Simulation time 226901594 ps
CPU time 18.77 seconds
Started May 14 01:32:25 PM PDT 24
Finished May 14 01:32:44 PM PDT 24
Peak memory 248736 kb
Host smart-58c0ad2f-aa23-4a56-9468-355fc3fbc12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28077
5719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.280775719
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1373320613
Short name T674
Test name
Test status
Simulation time 30417191669 ps
CPU time 862.54 seconds
Started May 14 01:32:28 PM PDT 24
Finished May 14 01:46:52 PM PDT 24
Peak memory 266176 kb
Host smart-5650852b-99d3-4842-8bd6-244d4531bcfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373320613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1373320613
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4189317120
Short name T553
Test name
Test status
Simulation time 41204462148 ps
CPU time 701.57 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:44:09 PM PDT 24
Peak memory 265088 kb
Host smart-676bca91-4bd2-400c-b8af-50c763e03309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189317120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4189317120
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.959960672
Short name T289
Test name
Test status
Simulation time 5617765768 ps
CPU time 235.64 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:36:22 PM PDT 24
Peak memory 248036 kb
Host smart-637f1b99-1387-4753-8f05-c892ed0e4adc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959960672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.959960672
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3965507103
Short name T622
Test name
Test status
Simulation time 1409073771 ps
CPU time 22.72 seconds
Started May 14 01:32:27 PM PDT 24
Finished May 14 01:32:51 PM PDT 24
Peak memory 254960 kb
Host smart-711f2ea9-b1fe-4bcb-833e-ff01af3ed69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39655
07103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3965507103
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4185701243
Short name T684
Test name
Test status
Simulation time 167774429 ps
CPU time 6.38 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:32:33 PM PDT 24
Peak memory 239016 kb
Host smart-af14beeb-628c-402c-be8c-7c3c4dc3ec42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41857
01243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4185701243
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1970470116
Short name T111
Test name
Test status
Simulation time 210160566 ps
CPU time 18.6 seconds
Started May 14 01:32:31 PM PDT 24
Finished May 14 01:32:50 PM PDT 24
Peak memory 248732 kb
Host smart-9a8da935-ea5a-4416-a885-2dc51455ffb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19704
70116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1970470116
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3891753095
Short name T702
Test name
Test status
Simulation time 399354304 ps
CPU time 29.56 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:32:56 PM PDT 24
Peak memory 248720 kb
Host smart-eeb410cd-0da5-49dc-9bb7-08c0dc19205c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38917
53095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3891753095
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3085310126
Short name T573
Test name
Test status
Simulation time 250011102666 ps
CPU time 3363.52 seconds
Started May 14 01:32:30 PM PDT 24
Finished May 14 02:28:35 PM PDT 24
Peak memory 304888 kb
Host smart-14614d2a-3ec0-495b-920a-bd297506d450
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085310126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3085310126
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.75010419
Short name T174
Test name
Test status
Simulation time 71016886984 ps
CPU time 8781.16 seconds
Started May 14 01:32:24 PM PDT 24
Finished May 14 03:58:47 PM PDT 24
Peak memory 395004 kb
Host smart-9865a7e6-1346-4f3a-b016-bdb50e0af695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75010419 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.75010419
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2802907089
Short name T488
Test name
Test status
Simulation time 194425386309 ps
CPU time 2882.13 seconds
Started May 14 01:32:27 PM PDT 24
Finished May 14 02:20:30 PM PDT 24
Peak memory 289316 kb
Host smart-5513e0f8-30e6-4333-825d-d1604eac43c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802907089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2802907089
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3131753704
Short name T503
Test name
Test status
Simulation time 6240047942 ps
CPU time 182.32 seconds
Started May 14 01:32:29 PM PDT 24
Finished May 14 01:35:32 PM PDT 24
Peak memory 249968 kb
Host smart-d36df865-a360-4358-907b-cf553775dee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31317
53704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3131753704
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2945852149
Short name T582
Test name
Test status
Simulation time 1660468216 ps
CPU time 35.54 seconds
Started May 14 01:32:24 PM PDT 24
Finished May 14 01:33:01 PM PDT 24
Peak memory 248908 kb
Host smart-58a990c6-722b-4ad3-9c74-ac36069c2978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
52149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2945852149
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2135862180
Short name T306
Test name
Test status
Simulation time 105064470172 ps
CPU time 1485.22 seconds
Started May 14 01:32:28 PM PDT 24
Finished May 14 01:57:14 PM PDT 24
Peak memory 265180 kb
Host smart-1f7141b5-aa7b-4a72-b85e-f8a51903e228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135862180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2135862180
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.144919727
Short name T181
Test name
Test status
Simulation time 11933276173 ps
CPU time 1111.2 seconds
Started May 14 01:32:27 PM PDT 24
Finished May 14 01:50:59 PM PDT 24
Peak memory 281568 kb
Host smart-954b80db-7ce1-4a61-aee9-c9ef7618db61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144919727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.144919727
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1240445724
Short name T299
Test name
Test status
Simulation time 2664709768 ps
CPU time 103.3 seconds
Started May 14 01:32:28 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 254092 kb
Host smart-d2ae35f2-bb58-4b1a-98bb-85ef841a273a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240445724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1240445724
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2214760613
Short name T455
Test name
Test status
Simulation time 25096902 ps
CPU time 3.44 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:32:31 PM PDT 24
Peak memory 240532 kb
Host smart-875cbe6f-4675-443a-b9b1-18d1a973d96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
60613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2214760613
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1815142017
Short name T38
Test name
Test status
Simulation time 495312617 ps
CPU time 32 seconds
Started May 14 01:32:31 PM PDT 24
Finished May 14 01:33:04 PM PDT 24
Peak memory 255108 kb
Host smart-d6b0bff0-a9b8-4ec3-9849-6f315a02e5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18151
42017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1815142017
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1438700571
Short name T393
Test name
Test status
Simulation time 123178634 ps
CPU time 16.7 seconds
Started May 14 01:32:26 PM PDT 24
Finished May 14 01:32:44 PM PDT 24
Peak memory 255880 kb
Host smart-b31ac6d8-229c-4bba-9997-4925e658a572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
00571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1438700571
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3161499129
Short name T558
Test name
Test status
Simulation time 51868735 ps
CPU time 5.19 seconds
Started May 14 01:32:28 PM PDT 24
Finished May 14 01:32:34 PM PDT 24
Peak memory 251080 kb
Host smart-cee2d236-e6f2-4bce-9b48-293d925283b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
99129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3161499129
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1082618870
Short name T67
Test name
Test status
Simulation time 9249549196 ps
CPU time 978.91 seconds
Started May 14 01:32:25 PM PDT 24
Finished May 14 01:48:45 PM PDT 24
Peak memory 272748 kb
Host smart-f2086d5e-ffe8-4896-a749-f9a4d92716fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082618870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1082618870
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.999260313
Short name T601
Test name
Test status
Simulation time 505820668305 ps
CPU time 4518.66 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 02:47:56 PM PDT 24
Peak memory 322368 kb
Host smart-192f3292-04be-420c-b833-d316f6b30f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999260313 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.999260313
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3351489164
Short name T654
Test name
Test status
Simulation time 50434617246 ps
CPU time 3035.29 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 02:23:13 PM PDT 24
Peak memory 281512 kb
Host smart-3f5a9d56-9197-47b1-9ee5-6018837cd715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351489164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3351489164
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3255682136
Short name T570
Test name
Test status
Simulation time 1876042752 ps
CPU time 129.36 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 255592 kb
Host smart-836ac869-aaed-4ace-b060-c550ebe0780c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
82136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3255682136
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1030500536
Short name T513
Test name
Test status
Simulation time 275102397 ps
CPU time 18.02 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:32:57 PM PDT 24
Peak memory 248736 kb
Host smart-d354c9b0-00b5-4b09-b5e2-b2499f555b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305
00536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1030500536
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3251862624
Short name T303
Test name
Test status
Simulation time 24367100370 ps
CPU time 1582.48 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 01:59:05 PM PDT 24
Peak memory 289532 kb
Host smart-f10b4839-adce-4259-bfe7-f9fbba1ab68f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251862624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3251862624
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3754931901
Short name T539
Test name
Test status
Simulation time 51295831214 ps
CPU time 3029.1 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 02:23:09 PM PDT 24
Peak memory 289252 kb
Host smart-0391ac29-c244-4066-b0bb-26db1085214b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754931901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3754931901
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2324725269
Short name T307
Test name
Test status
Simulation time 8527126494 ps
CPU time 364.1 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 01:38:46 PM PDT 24
Peak memory 248244 kb
Host smart-e543d830-9d1c-4fe4-a079-6350bf19e9bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324725269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2324725269
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3914418601
Short name T335
Test name
Test status
Simulation time 246759161 ps
CPU time 8.75 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:32:47 PM PDT 24
Peak memory 248708 kb
Host smart-be082c1d-0f1b-40d8-b661-c82f5becd1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144
18601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3914418601
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2225656746
Short name T334
Test name
Test status
Simulation time 245661529 ps
CPU time 9.19 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:32:48 PM PDT 24
Peak memory 253008 kb
Host smart-7834aa67-8068-4bf8-8ea5-3980e77bb82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
56746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2225656746
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3877418943
Short name T89
Test name
Test status
Simulation time 693276207 ps
CPU time 40.74 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:33:19 PM PDT 24
Peak memory 248848 kb
Host smart-b8cd90b9-fbfa-4f9c-af7f-e0e3e17b0076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38774
18943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3877418943
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1200620511
Short name T435
Test name
Test status
Simulation time 1076472270 ps
CPU time 8.29 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:32:47 PM PDT 24
Peak memory 248716 kb
Host smart-32d17359-2ad4-4df2-b8a6-9e549376433e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12006
20511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1200620511
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3914013220
Short name T508
Test name
Test status
Simulation time 85349721157 ps
CPU time 1674.67 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 02:00:37 PM PDT 24
Peak memory 289336 kb
Host smart-7ce5a230-8491-4c47-843a-6843ff5f36e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914013220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3914013220
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1408510429
Short name T177
Test name
Test status
Simulation time 36990293114 ps
CPU time 2200.26 seconds
Started May 14 01:32:39 PM PDT 24
Finished May 14 02:09:20 PM PDT 24
Peak memory 273016 kb
Host smart-2cb6a0aa-90ab-4f45-a5d6-a7a04acbc2b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408510429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1408510429
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1434021113
Short name T700
Test name
Test status
Simulation time 10312627167 ps
CPU time 172.05 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:35:31 PM PDT 24
Peak memory 256964 kb
Host smart-638f17df-6055-40e2-a7d1-8dcf5116608e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
21113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1434021113
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2260645703
Short name T524
Test name
Test status
Simulation time 2176107778 ps
CPU time 35.27 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 01:33:17 PM PDT 24
Peak memory 255608 kb
Host smart-9468f601-3a3c-4a89-891d-86632c336198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
45703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2260645703
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2038227474
Short name T614
Test name
Test status
Simulation time 27145032614 ps
CPU time 1146.49 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:51:45 PM PDT 24
Peak memory 273340 kb
Host smart-78274236-85e6-4f4c-828d-5a249f335862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038227474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2038227474
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.13412991
Short name T450
Test name
Test status
Simulation time 21145662153 ps
CPU time 1277.08 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:53:55 PM PDT 24
Peak memory 270304 kb
Host smart-b7aca661-cc0e-49f9-bff4-dc41d1786753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13412991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.13412991
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.212757805
Short name T555
Test name
Test status
Simulation time 8187248897 ps
CPU time 319.55 seconds
Started May 14 01:32:39 PM PDT 24
Finished May 14 01:38:00 PM PDT 24
Peak memory 247880 kb
Host smart-799c3189-3a43-4efd-98ed-e6bd6b80713f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212757805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.212757805
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.366756764
Short name T552
Test name
Test status
Simulation time 1765791717 ps
CPU time 34.48 seconds
Started May 14 01:32:40 PM PDT 24
Finished May 14 01:33:15 PM PDT 24
Peak memory 256912 kb
Host smart-aef1114a-c689-43c5-a818-18a5c161b967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36675
6764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.366756764
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2791985719
Short name T518
Test name
Test status
Simulation time 238205724 ps
CPU time 11.24 seconds
Started May 14 01:32:37 PM PDT 24
Finished May 14 01:32:49 PM PDT 24
Peak memory 252904 kb
Host smart-e40af19c-f2b9-463f-890e-77bac8b4b2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
85719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2791985719
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1131871291
Short name T641
Test name
Test status
Simulation time 337543476 ps
CPU time 21.23 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 01:33:03 PM PDT 24
Peak memory 248636 kb
Host smart-e9e31ace-702d-47bb-b6a8-86566d2aff2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
71291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1131871291
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1127857562
Short name T271
Test name
Test status
Simulation time 2450264838 ps
CPU time 234.53 seconds
Started May 14 01:32:31 PM PDT 24
Finished May 14 01:36:27 PM PDT 24
Peak memory 256948 kb
Host smart-a93185f8-0c7a-4fad-8135-57fa5675e8e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127857562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1127857562
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3458484638
Short name T105
Test name
Test status
Simulation time 12614103170 ps
CPU time 1337.51 seconds
Started May 14 01:32:39 PM PDT 24
Finished May 14 01:54:58 PM PDT 24
Peak memory 288844 kb
Host smart-89316240-0ed7-439c-95ba-8b8ada8ee746
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458484638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3458484638
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3155551881
Short name T361
Test name
Test status
Simulation time 4172438009 ps
CPU time 81.01 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:34:00 PM PDT 24
Peak memory 249044 kb
Host smart-adac2e1c-c45a-4801-be89-5ef4a7d14a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31555
51881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3155551881
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1848939688
Short name T81
Test name
Test status
Simulation time 1550117695 ps
CPU time 30.81 seconds
Started May 14 01:32:40 PM PDT 24
Finished May 14 01:33:12 PM PDT 24
Peak memory 248752 kb
Host smart-5815b05c-22d2-4d8a-bf1c-39080c7074ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
39688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1848939688
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3098132243
Short name T61
Test name
Test status
Simulation time 25126584575 ps
CPU time 1647.5 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 02:00:07 PM PDT 24
Peak memory 271368 kb
Host smart-ca9f8e3e-1cff-495c-845d-a333b98013a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098132243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3098132243
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.744153143
Short name T103
Test name
Test status
Simulation time 136824626841 ps
CPU time 1856.67 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 02:03:36 PM PDT 24
Peak memory 273288 kb
Host smart-9caf48e2-b9b6-499a-a396-59b910a61b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744153143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.744153143
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3014572854
Short name T357
Test name
Test status
Simulation time 326320506 ps
CPU time 32.79 seconds
Started May 14 01:32:36 PM PDT 24
Finished May 14 01:33:10 PM PDT 24
Peak memory 248732 kb
Host smart-cc500dd3-54c1-42a6-91d9-876637df5c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
72854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3014572854
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3173897370
Short name T542
Test name
Test status
Simulation time 240483875 ps
CPU time 11.01 seconds
Started May 14 01:32:41 PM PDT 24
Finished May 14 01:32:53 PM PDT 24
Peak memory 252912 kb
Host smart-e3d94d3e-563b-4cc0-a9cb-9178c150a55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31738
97370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3173897370
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3898646928
Short name T21
Test name
Test status
Simulation time 1157817213 ps
CPU time 22.08 seconds
Started May 14 01:32:39 PM PDT 24
Finished May 14 01:33:02 PM PDT 24
Peak memory 248800 kb
Host smart-e7b67733-3353-488d-867f-bb12e0a5089d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38986
46928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3898646928
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2942439066
Short name T590
Test name
Test status
Simulation time 874070055 ps
CPU time 38.69 seconds
Started May 14 01:32:38 PM PDT 24
Finished May 14 01:33:18 PM PDT 24
Peak memory 256676 kb
Host smart-a7cbb304-a592-45ac-90e2-222146a1d70e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942439066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2942439066
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1229125267
Short name T441
Test name
Test status
Simulation time 29723408686 ps
CPU time 1642.51 seconds
Started May 14 01:32:45 PM PDT 24
Finished May 14 02:00:08 PM PDT 24
Peak memory 268548 kb
Host smart-5b0faefe-e9ce-4851-8abf-60bb7ec8c465
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229125267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1229125267
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3883397609
Short name T549
Test name
Test status
Simulation time 4978174452 ps
CPU time 74.99 seconds
Started May 14 01:32:45 PM PDT 24
Finished May 14 01:34:01 PM PDT 24
Peak memory 248664 kb
Host smart-caf57cc5-9a3f-476d-a152-025053f379e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38833
97609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3883397609
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3145600018
Short name T489
Test name
Test status
Simulation time 676892665 ps
CPU time 45.91 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:33:34 PM PDT 24
Peak memory 255512 kb
Host smart-3f27ae9c-bcec-44e7-aed2-86c7bc00bd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
00018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3145600018
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.211739402
Short name T320
Test name
Test status
Simulation time 64064825590 ps
CPU time 1015.35 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:49:44 PM PDT 24
Peak memory 268232 kb
Host smart-bcc29ecd-3cb9-4572-911a-29d498af64b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211739402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.211739402
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1652340929
Short name T597
Test name
Test status
Simulation time 35983748853 ps
CPU time 725.29 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:44:53 PM PDT 24
Peak memory 266232 kb
Host smart-fdf50e6e-dda2-4a06-a6d2-e1339219cc26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652340929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1652340929
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.867210387
Short name T9
Test name
Test status
Simulation time 23202567139 ps
CPU time 333.96 seconds
Started May 14 01:32:48 PM PDT 24
Finished May 14 01:38:23 PM PDT 24
Peak memory 254736 kb
Host smart-10e9caac-5e83-4dd0-aabe-214b34cdded3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867210387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.867210387
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2611318519
Short name T341
Test name
Test status
Simulation time 5414047592 ps
CPU time 52.2 seconds
Started May 14 01:32:39 PM PDT 24
Finished May 14 01:33:33 PM PDT 24
Peak memory 248792 kb
Host smart-e1c70fbf-0459-47fa-9ec9-f5f20dd239f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
18519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2611318519
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.372444353
Short name T566
Test name
Test status
Simulation time 1148839933 ps
CPU time 25.34 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:33:13 PM PDT 24
Peak memory 248676 kb
Host smart-7d6a0fe2-4b38-4fb1-a8e0-4100d4be6df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37244
4353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.372444353
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.962652296
Short name T419
Test name
Test status
Simulation time 186774353 ps
CPU time 14.38 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:33:03 PM PDT 24
Peak memory 253148 kb
Host smart-7d1ac712-28ff-4d33-9957-3c2dfcb55798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96265
2296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.962652296
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3850247398
Short name T394
Test name
Test status
Simulation time 570128385 ps
CPU time 34 seconds
Started May 14 01:32:40 PM PDT 24
Finished May 14 01:33:15 PM PDT 24
Peak memory 248744 kb
Host smart-eff2fe72-56a6-4b85-9bfa-71cbd3d4514c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
47398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3850247398
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2262402277
Short name T425
Test name
Test status
Simulation time 2562968603 ps
CPU time 48.5 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:33:36 PM PDT 24
Peak memory 256192 kb
Host smart-3dc72df9-d1bf-4511-84e0-41031d18bfac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262402277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2262402277
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.968830392
Short name T215
Test name
Test status
Simulation time 71330098035 ps
CPU time 586.84 seconds
Started May 14 01:32:49 PM PDT 24
Finished May 14 01:42:36 PM PDT 24
Peak memory 265240 kb
Host smart-95b888c4-f31b-4f80-b942-18d5a73d55f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968830392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.968830392
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3961959139
Short name T653
Test name
Test status
Simulation time 3148861719 ps
CPU time 117.28 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 249816 kb
Host smart-5fbbffc6-f9a1-4166-87a8-2ce90bbdd78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39619
59139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3961959139
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3030007130
Short name T36
Test name
Test status
Simulation time 914133641 ps
CPU time 71.31 seconds
Started May 14 01:32:48 PM PDT 24
Finished May 14 01:34:01 PM PDT 24
Peak memory 249132 kb
Host smart-aabe29d4-6d37-4258-9c86-0505cc540509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30300
07130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3030007130
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.593341646
Short name T402
Test name
Test status
Simulation time 32822062119 ps
CPU time 1490.89 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:57:39 PM PDT 24
Peak memory 288656 kb
Host smart-9c0080a4-a899-486b-b65e-b61b8e454a6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593341646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.593341646
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3220841496
Short name T3
Test name
Test status
Simulation time 421249076 ps
CPU time 19.69 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:33:08 PM PDT 24
Peak memory 256872 kb
Host smart-96cee63d-bbed-4eda-b5cd-0f6c9509e519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
41496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3220841496
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3657541939
Short name T466
Test name
Test status
Simulation time 73032331 ps
CPU time 3.84 seconds
Started May 14 01:32:48 PM PDT 24
Finished May 14 01:32:53 PM PDT 24
Peak memory 239200 kb
Host smart-b0880966-ce0d-4c30-ba22-e5247f862238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
41939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3657541939
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2522372137
Short name T37
Test name
Test status
Simulation time 4467730351 ps
CPU time 78.31 seconds
Started May 14 01:32:49 PM PDT 24
Finished May 14 01:34:08 PM PDT 24
Peak memory 256400 kb
Host smart-84649024-456e-4162-acdb-5bd41dd6f62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
72137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2522372137
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.305270919
Short name T347
Test name
Test status
Simulation time 112034398 ps
CPU time 12.89 seconds
Started May 14 01:32:45 PM PDT 24
Finished May 14 01:32:58 PM PDT 24
Peak memory 255916 kb
Host smart-01336ebf-87e8-4e89-b16a-b23c8643a485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
0919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.305270919
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1335412150
Short name T236
Test name
Test status
Simulation time 14424053259 ps
CPU time 1277.96 seconds
Started May 14 01:32:46 PM PDT 24
Finished May 14 01:54:05 PM PDT 24
Peak memory 289204 kb
Host smart-c6d77d36-0b2e-4eea-a8bf-856aa9c3c737
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335412150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1335412150
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1169301131
Short name T514
Test name
Test status
Simulation time 8584574660 ps
CPU time 709.37 seconds
Started May 14 01:32:59 PM PDT 24
Finished May 14 01:44:49 PM PDT 24
Peak memory 273384 kb
Host smart-13d38a75-bd14-4913-8338-8116d00b17d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169301131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1169301131
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3877296335
Short name T593
Test name
Test status
Simulation time 933038714 ps
CPU time 25.03 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:33:23 PM PDT 24
Peak memory 249080 kb
Host smart-f79f9ace-bbe6-4af0-8e15-e8ee5b76e767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38772
96335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3877296335
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1980488370
Short name T383
Test name
Test status
Simulation time 787636181 ps
CPU time 45.07 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:33:43 PM PDT 24
Peak memory 255924 kb
Host smart-047a34a6-9126-4a30-b90c-112a4873c440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19804
88370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1980488370
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2187906132
Short name T310
Test name
Test status
Simulation time 40981585882 ps
CPU time 1603.75 seconds
Started May 14 01:33:00 PM PDT 24
Finished May 14 01:59:44 PM PDT 24
Peak memory 272432 kb
Host smart-e984833c-5d29-4e58-9065-7c13860d23e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187906132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2187906132
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4224888597
Short name T252
Test name
Test status
Simulation time 52999799907 ps
CPU time 2919.35 seconds
Started May 14 01:32:55 PM PDT 24
Finished May 14 02:21:36 PM PDT 24
Peak memory 288952 kb
Host smart-f5a7733d-3f82-4136-856d-576e4ce99b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224888597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4224888597
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3237830288
Short name T568
Test name
Test status
Simulation time 20307343023 ps
CPU time 217.14 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:36:35 PM PDT 24
Peak memory 254660 kb
Host smart-fa196506-84c3-4a8a-a9ac-ccfd220036d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237830288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3237830288
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.259159567
Short name T507
Test name
Test status
Simulation time 3820449973 ps
CPU time 52.81 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:33:41 PM PDT 24
Peak memory 256116 kb
Host smart-a89f65bf-6000-4894-9667-333eea274deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915
9567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.259159567
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2547642150
Short name T537
Test name
Test status
Simulation time 1611654001 ps
CPU time 25.91 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 01:33:23 PM PDT 24
Peak memory 248732 kb
Host smart-77fccb15-1eed-4b7f-a4da-9a52c57aa3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25476
42150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2547642150
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2931060603
Short name T688
Test name
Test status
Simulation time 834309701 ps
CPU time 41.13 seconds
Started May 14 01:32:59 PM PDT 24
Finished May 14 01:33:40 PM PDT 24
Peak memory 255160 kb
Host smart-c4cfafad-ac94-4588-bca5-bda213396ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
60603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2931060603
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1793031062
Short name T491
Test name
Test status
Simulation time 138701913 ps
CPU time 15.93 seconds
Started May 14 01:32:47 PM PDT 24
Finished May 14 01:33:04 PM PDT 24
Peak memory 248724 kb
Host smart-03e373ea-d9f8-4a6b-a7be-9f7ff6154526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17930
31062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1793031062
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4229053056
Short name T423
Test name
Test status
Simulation time 40947670652 ps
CPU time 2373.7 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 02:12:31 PM PDT 24
Peak memory 285648 kb
Host smart-2338803e-94e3-47f0-b963-72ae01a119e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229053056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4229053056
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.514324661
Short name T94
Test name
Test status
Simulation time 346707484920 ps
CPU time 4288.51 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 02:44:27 PM PDT 24
Peak memory 305932 kb
Host smart-bf953e98-1357-4a50-ab8c-272ad5b0b8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514324661 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.514324661
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1268104696
Short name T197
Test name
Test status
Simulation time 126049269 ps
CPU time 3.7 seconds
Started May 14 01:30:38 PM PDT 24
Finished May 14 01:30:43 PM PDT 24
Peak memory 248884 kb
Host smart-33a42d4e-a988-429e-aa2c-d4427a65619e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1268104696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1268104696
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.825716099
Short name T677
Test name
Test status
Simulation time 158020922 ps
CPU time 9.33 seconds
Started May 14 01:30:42 PM PDT 24
Finished May 14 01:30:52 PM PDT 24
Peak memory 248788 kb
Host smart-58ef0864-38d6-4e11-b5ee-002270049778
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=825716099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.825716099
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.182072937
Short name T446
Test name
Test status
Simulation time 5106851568 ps
CPU time 281.96 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:35:23 PM PDT 24
Peak memory 251252 kb
Host smart-90da601a-c3b8-4b60-99a8-429ea27ac383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207
2937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.182072937
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2824598352
Short name T596
Test name
Test status
Simulation time 39188411 ps
CPU time 3.03 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:30:45 PM PDT 24
Peak memory 240476 kb
Host smart-289fb09f-783d-4cb4-8cf0-e2f16a8404da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
98352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2824598352
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2874164857
Short name T694
Test name
Test status
Simulation time 162825415927 ps
CPU time 2300.78 seconds
Started May 14 01:30:42 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 281596 kb
Host smart-c5618e41-1d2d-474a-91e0-f4553f4af94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874164857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2874164857
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.682384663
Short name T32
Test name
Test status
Simulation time 42264670895 ps
CPU time 2690.78 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 02:15:32 PM PDT 24
Peak memory 289784 kb
Host smart-e4146b72-c445-4edf-b00a-d077dd8053f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682384663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.682384663
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4230270490
Short name T526
Test name
Test status
Simulation time 11527733873 ps
CPU time 474.1 seconds
Started May 14 01:30:44 PM PDT 24
Finished May 14 01:38:39 PM PDT 24
Peak memory 247980 kb
Host smart-cf43f4c6-f555-4a0a-93e3-1170c1854d4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230270490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4230270490
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2420859813
Short name T352
Test name
Test status
Simulation time 2312889366 ps
CPU time 36.04 seconds
Started May 14 01:30:41 PM PDT 24
Finished May 14 01:31:18 PM PDT 24
Peak memory 248788 kb
Host smart-0a8c557c-655f-4214-806a-c65d25994861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208
59813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2420859813
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1292106123
Short name T12
Test name
Test status
Simulation time 794871716 ps
CPU time 12.81 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:30:54 PM PDT 24
Peak memory 270368 kb
Host smart-e114c699-13c4-4d3b-b6ba-dbe13c025e7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1292106123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1292106123
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2400300528
Short name T65
Test name
Test status
Simulation time 257387109 ps
CPU time 15.57 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:03 PM PDT 24
Peak memory 255644 kb
Host smart-8957a28e-922c-4778-947d-863ab9926386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24003
00528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2400300528
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.537152790
Short name T606
Test name
Test status
Simulation time 3400077213 ps
CPU time 50.19 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:37 PM PDT 24
Peak memory 248784 kb
Host smart-70131164-4bda-4a96-a9d0-a74df47f3af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53715
2790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.537152790
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3961178988
Short name T70
Test name
Test status
Simulation time 9110299456 ps
CPU time 139.62 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:33:00 PM PDT 24
Peak memory 256960 kb
Host smart-ba4bf1c6-1d15-4d49-929e-cf5c0a360231
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961178988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3961178988
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.805033894
Short name T420
Test name
Test status
Simulation time 39740047809 ps
CPU time 2006.32 seconds
Started May 14 01:32:54 PM PDT 24
Finished May 14 02:06:22 PM PDT 24
Peak memory 281640 kb
Host smart-051313a0-d804-481d-a952-d36a990fc92b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805033894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.805033894
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1151885780
Short name T240
Test name
Test status
Simulation time 14597860432 ps
CPU time 251.31 seconds
Started May 14 01:32:55 PM PDT 24
Finished May 14 01:37:07 PM PDT 24
Peak memory 256960 kb
Host smart-4eaaec49-e00b-49e9-a284-60a45c2b3732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518
85780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1151885780
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2799150878
Short name T693
Test name
Test status
Simulation time 88367712404 ps
CPU time 1837.87 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 02:03:34 PM PDT 24
Peak memory 281660 kb
Host smart-1121bd5e-f54e-4fb6-8edd-476b50f54794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799150878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2799150878
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1621159721
Short name T438
Test name
Test status
Simulation time 23125818709 ps
CPU time 1521.01 seconds
Started May 14 01:32:58 PM PDT 24
Finished May 14 01:58:20 PM PDT 24
Peak memory 287524 kb
Host smart-bb6117da-fb2f-424c-9c10-2e84512f48fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621159721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1621159721
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3511469303
Short name T285
Test name
Test status
Simulation time 14293837063 ps
CPU time 269.42 seconds
Started May 14 01:32:59 PM PDT 24
Finished May 14 01:37:29 PM PDT 24
Peak memory 247132 kb
Host smart-0675f5aa-2e86-40b2-8124-a5a13b0d1226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511469303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3511469303
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2637055111
Short name T612
Test name
Test status
Simulation time 939770882 ps
CPU time 19.83 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 01:33:17 PM PDT 24
Peak memory 248720 kb
Host smart-d3bbd9b4-75df-4e7e-973f-92d97ae9327a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26370
55111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2637055111
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.443778961
Short name T509
Test name
Test status
Simulation time 1412989438 ps
CPU time 49.05 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:33:47 PM PDT 24
Peak memory 249200 kb
Host smart-d1913f40-bf5c-424b-ab98-08b55452c29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44377
8961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.443778961
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.553434443
Short name T648
Test name
Test status
Simulation time 197874307 ps
CPU time 11.83 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:33:10 PM PDT 24
Peak memory 248716 kb
Host smart-7e2833cd-f1dd-44e0-8c3c-791988462463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55343
4443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.553434443
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3588563341
Short name T463
Test name
Test status
Simulation time 1240438252 ps
CPU time 34.82 seconds
Started May 14 01:32:55 PM PDT 24
Finished May 14 01:33:31 PM PDT 24
Peak memory 248724 kb
Host smart-54d04331-94f0-4bb4-8e90-0c2d93e1ea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35885
63341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3588563341
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1866401405
Short name T623
Test name
Test status
Simulation time 11812280144 ps
CPU time 1206 seconds
Started May 14 01:33:00 PM PDT 24
Finished May 14 01:53:07 PM PDT 24
Peak memory 285576 kb
Host smart-9fc6b485-0764-4bd4-ac27-42b89055dc2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866401405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1866401405
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2950498025
Short name T658
Test name
Test status
Simulation time 17533172989 ps
CPU time 763.68 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:45:50 PM PDT 24
Peak memory 272104 kb
Host smart-b9383b34-1888-4469-96ac-d9af79771354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950498025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2950498025
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2628982534
Short name T520
Test name
Test status
Simulation time 3420155046 ps
CPU time 181.2 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:36:08 PM PDT 24
Peak memory 250224 kb
Host smart-606ea956-0518-4a39-a8a7-e5f90e1d5d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26289
82534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2628982534
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.433980850
Short name T77
Test name
Test status
Simulation time 1141862634 ps
CPU time 71.02 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:34:18 PM PDT 24
Peak memory 255940 kb
Host smart-d0974314-5ee9-4efa-8119-f2b612389b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43398
0850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.433980850
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.4122006012
Short name T624
Test name
Test status
Simulation time 29653059317 ps
CPU time 1546.21 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:58:52 PM PDT 24
Peak memory 269512 kb
Host smart-6dcb1c99-47ba-4468-a4c7-a882c264ea17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122006012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.4122006012
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2342611582
Short name T634
Test name
Test status
Simulation time 70895173117 ps
CPU time 394.68 seconds
Started May 14 01:33:07 PM PDT 24
Finished May 14 01:39:43 PM PDT 24
Peak memory 254336 kb
Host smart-ce53b440-e519-4430-8acc-3817e2c1a3cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342611582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2342611582
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1875746668
Short name T413
Test name
Test status
Simulation time 513638546 ps
CPU time 12.31 seconds
Started May 14 01:33:00 PM PDT 24
Finished May 14 01:33:13 PM PDT 24
Peak memory 256924 kb
Host smart-a5734227-7e43-4f6d-9fe3-4b3cfbf26b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18757
46668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1875746668
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2982427432
Short name T626
Test name
Test status
Simulation time 192105709 ps
CPU time 21.49 seconds
Started May 14 01:32:56 PM PDT 24
Finished May 14 01:33:18 PM PDT 24
Peak memory 254608 kb
Host smart-19188fbb-8acb-47b7-925d-890ccc9a0f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29824
27432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2982427432
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3560490144
Short name T644
Test name
Test status
Simulation time 2210572444 ps
CPU time 67.89 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:34:15 PM PDT 24
Peak memory 249224 kb
Host smart-9252d469-dd2b-460b-8645-f28f8c2982cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
90144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3560490144
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3489174154
Short name T386
Test name
Test status
Simulation time 4511613898 ps
CPU time 67.88 seconds
Started May 14 01:32:57 PM PDT 24
Finished May 14 01:34:06 PM PDT 24
Peak memory 248776 kb
Host smart-c456b7ef-b849-48c1-b41d-010c4eae251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34891
74154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3489174154
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3630089271
Short name T46
Test name
Test status
Simulation time 13744541577 ps
CPU time 1282.01 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:54:28 PM PDT 24
Peak memory 289408 kb
Host smart-eb1821ce-72c8-435a-bb1e-fcbd29a7f7ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630089271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3630089271
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2361155601
Short name T559
Test name
Test status
Simulation time 1205218522 ps
CPU time 65.06 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:34:12 PM PDT 24
Peak memory 248604 kb
Host smart-0a9f95fa-aa4f-4d19-a6e8-874d9d26c185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23611
55601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2361155601
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1446579512
Short name T448
Test name
Test status
Simulation time 1327094384 ps
CPU time 38.1 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:33:46 PM PDT 24
Peak memory 255780 kb
Host smart-e425d8ee-e529-453a-8c0b-56da3832af30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14465
79512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1446579512
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1708747046
Short name T309
Test name
Test status
Simulation time 180910031435 ps
CPU time 1692.75 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 02:01:19 PM PDT 24
Peak memory 273220 kb
Host smart-a14b1cd2-5f5e-469e-9f96-f97427496ae2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708747046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1708747046
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2957788038
Short name T69
Test name
Test status
Simulation time 59044845375 ps
CPU time 3288.35 seconds
Started May 14 01:33:10 PM PDT 24
Finished May 14 02:27:59 PM PDT 24
Peak memory 289488 kb
Host smart-3708bb12-e9cc-4237-97e4-5911b1c9e362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957788038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2957788038
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2046096717
Short name T220
Test name
Test status
Simulation time 12019965913 ps
CPU time 249.55 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 248228 kb
Host smart-2bcb8faa-e514-473a-b424-88cd553b1069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046096717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2046096717
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.781157852
Short name T246
Test name
Test status
Simulation time 3037541152 ps
CPU time 23 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:33:28 PM PDT 24
Peak memory 254992 kb
Host smart-44dbb5aa-532a-40ba-bc30-c8444a79fb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78115
7852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.781157852
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2546575561
Short name T421
Test name
Test status
Simulation time 273156829 ps
CPU time 15.25 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:33:23 PM PDT 24
Peak memory 248720 kb
Host smart-8b8287d4-b97d-47b5-984e-67c401937237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
75561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2546575561
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.286575432
Short name T182
Test name
Test status
Simulation time 303456475 ps
CPU time 7.7 seconds
Started May 14 01:33:08 PM PDT 24
Finished May 14 01:33:17 PM PDT 24
Peak memory 253912 kb
Host smart-2a301198-a395-416a-949d-bbccb28ba3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28657
5432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.286575432
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1109085201
Short name T588
Test name
Test status
Simulation time 2699802384 ps
CPU time 60.45 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:34:08 PM PDT 24
Peak memory 248772 kb
Host smart-44744fe6-92c1-481c-85c2-48972660334a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11090
85201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1109085201
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3423077874
Short name T95
Test name
Test status
Simulation time 42364564886 ps
CPU time 649.15 seconds
Started May 14 01:33:09 PM PDT 24
Finished May 14 01:43:58 PM PDT 24
Peak memory 256884 kb
Host smart-20db3a97-606f-4495-b17a-3beae038c493
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423077874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3423077874
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1617517459
Short name T175
Test name
Test status
Simulation time 89258053917 ps
CPU time 1283.24 seconds
Started May 14 01:33:05 PM PDT 24
Finished May 14 01:54:30 PM PDT 24
Peak memory 281640 kb
Host smart-3db941f8-3534-44e0-8aa3-238e5adc5107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617517459 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1617517459
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2544407057
Short name T53
Test name
Test status
Simulation time 17210873222 ps
CPU time 1095.27 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 01:51:29 PM PDT 24
Peak memory 281520 kb
Host smart-5df0d673-5c06-4522-b034-4cefa1feef9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544407057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2544407057
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3374007546
Short name T664
Test name
Test status
Simulation time 1786608047 ps
CPU time 12.39 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 01:33:26 PM PDT 24
Peak memory 254184 kb
Host smart-21c8f195-0de8-4af1-811f-c645bca4e51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
07546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3374007546
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.758404654
Short name T690
Test name
Test status
Simulation time 855248652 ps
CPU time 24.91 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 01:33:40 PM PDT 24
Peak memory 248828 kb
Host smart-36710df7-934a-4921-8487-e4d265c98f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75840
4654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.758404654
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3280728525
Short name T28
Test name
Test status
Simulation time 36580897244 ps
CPU time 1958.41 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 02:05:53 PM PDT 24
Peak memory 269376 kb
Host smart-bd9973a6-c01b-4198-adb1-3419f91b1615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280728525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3280728525
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.130656032
Short name T460
Test name
Test status
Simulation time 40019833610 ps
CPU time 1189.04 seconds
Started May 14 01:33:12 PM PDT 24
Finished May 14 01:53:03 PM PDT 24
Peak memory 286236 kb
Host smart-11080267-a882-480c-9488-d262f4388dbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130656032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.130656032
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3845999270
Short name T297
Test name
Test status
Simulation time 28328336472 ps
CPU time 296.07 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 248216 kb
Host smart-21e1b0f6-0ddd-48a4-abf3-18ce85836f93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845999270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3845999270
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.4007287605
Short name T611
Test name
Test status
Simulation time 685071785 ps
CPU time 46.69 seconds
Started May 14 01:33:03 PM PDT 24
Finished May 14 01:33:51 PM PDT 24
Peak memory 248724 kb
Host smart-f811a334-6663-4827-99bd-48f2789cb1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40072
87605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4007287605
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3562304790
Short name T511
Test name
Test status
Simulation time 81671440 ps
CPU time 12.22 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 01:33:27 PM PDT 24
Peak memory 248700 kb
Host smart-632cf0b2-d88f-4b18-b63f-dcca27132d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623
04790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3562304790
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.767220175
Short name T72
Test name
Test status
Simulation time 669681245 ps
CPU time 40.44 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 01:33:56 PM PDT 24
Peak memory 248888 kb
Host smart-acf085fa-881b-42c4-8577-275841bace72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76722
0175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.767220175
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1039918779
Short name T657
Test name
Test status
Simulation time 142921806 ps
CPU time 13.48 seconds
Started May 14 01:33:06 PM PDT 24
Finished May 14 01:33:21 PM PDT 24
Peak memory 248792 kb
Host smart-37969dee-73c3-4388-9069-13259cd9fb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
18779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1039918779
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1946904440
Short name T458
Test name
Test status
Simulation time 133439171249 ps
CPU time 1071.16 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 01:51:05 PM PDT 24
Peak memory 284892 kb
Host smart-8a27a0cd-96f8-4f37-ba8e-8373641ec7ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946904440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1946904440
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4221487017
Short name T598
Test name
Test status
Simulation time 175745345772 ps
CPU time 2837.7 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 02:20:33 PM PDT 24
Peak memory 289788 kb
Host smart-000405e2-0416-4f20-9a76-5c46f76bdce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221487017 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4221487017
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3873808382
Short name T432
Test name
Test status
Simulation time 19102922368 ps
CPU time 1663.89 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 02:00:58 PM PDT 24
Peak memory 289604 kb
Host smart-8d603e35-13f4-4818-8f57-1f5ef41f61ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873808382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3873808382
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.926507108
Short name T636
Test name
Test status
Simulation time 4604724828 ps
CPU time 280.69 seconds
Started May 14 01:33:15 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 256888 kb
Host smart-ffe38b6d-ffaf-4fc9-805e-9681becf1209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92650
7108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.926507108
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.227159458
Short name T605
Test name
Test status
Simulation time 496559239 ps
CPU time 35.04 seconds
Started May 14 01:33:18 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 255908 kb
Host smart-f4056eed-01c7-4209-ab3c-47ef3db2dfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
9458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.227159458
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.605054013
Short name T223
Test name
Test status
Simulation time 85528416952 ps
CPU time 1508.9 seconds
Started May 14 01:33:12 PM PDT 24
Finished May 14 01:58:22 PM PDT 24
Peak memory 288976 kb
Host smart-5fe910f1-b03f-4fb0-9f16-77ad0ef13d91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605054013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.605054013
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4086953622
Short name T659
Test name
Test status
Simulation time 439780531315 ps
CPU time 1914.67 seconds
Started May 14 01:33:18 PM PDT 24
Finished May 14 02:05:14 PM PDT 24
Peak memory 281548 kb
Host smart-9fec5e8f-21fe-40a7-a413-f1509cbe3621
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086953622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4086953622
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3824364686
Short name T452
Test name
Test status
Simulation time 2282859772 ps
CPU time 67.66 seconds
Started May 14 01:33:17 PM PDT 24
Finished May 14 01:34:26 PM PDT 24
Peak memory 248784 kb
Host smart-21d6947b-6ff5-4b43-9899-b747e36ec5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38243
64686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3824364686
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3786153553
Short name T525
Test name
Test status
Simulation time 535839091 ps
CPU time 33.39 seconds
Started May 14 01:33:12 PM PDT 24
Finished May 14 01:33:47 PM PDT 24
Peak memory 256120 kb
Host smart-6033525e-b495-41aa-8787-2a55a068c1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
53553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3786153553
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3475021759
Short name T471
Test name
Test status
Simulation time 305586880 ps
CPU time 10 seconds
Started May 14 01:33:18 PM PDT 24
Finished May 14 01:33:29 PM PDT 24
Peak memory 248724 kb
Host smart-9c44f039-f1c3-48f9-86b6-52b9673a11bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
21759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3475021759
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2476144375
Short name T350
Test name
Test status
Simulation time 1172506531 ps
CPU time 39.86 seconds
Started May 14 01:33:14 PM PDT 24
Finished May 14 01:33:55 PM PDT 24
Peak memory 248708 kb
Host smart-a0f099a3-8ddf-4eb8-a0e4-b2f1875bf821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24761
44375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2476144375
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3428105119
Short name T603
Test name
Test status
Simulation time 121756436660 ps
CPU time 475.32 seconds
Started May 14 01:33:13 PM PDT 24
Finished May 14 01:41:10 PM PDT 24
Peak memory 256956 kb
Host smart-77a1e16c-4cb0-49bf-894c-46fa751b5dea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428105119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3428105119
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.450293418
Short name T362
Test name
Test status
Simulation time 11032446590 ps
CPU time 1044.24 seconds
Started May 14 01:33:19 PM PDT 24
Finished May 14 01:50:44 PM PDT 24
Peak memory 273420 kb
Host smart-af4efd5e-d67a-44cb-bfde-26b622db531a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450293418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.450293418
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1750559021
Short name T424
Test name
Test status
Simulation time 1419290234 ps
CPU time 105.44 seconds
Started May 14 01:33:20 PM PDT 24
Finished May 14 01:35:06 PM PDT 24
Peak memory 256864 kb
Host smart-16d11146-dd6f-40cc-9522-0876ef3ac5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
59021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1750559021
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1334993657
Short name T535
Test name
Test status
Simulation time 214614552 ps
CPU time 32.74 seconds
Started May 14 01:33:20 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 248728 kb
Host smart-980690ef-57e6-4f92-b917-66c19ca54324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13349
93657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1334993657
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2606202560
Short name T645
Test name
Test status
Simulation time 16153028357 ps
CPU time 902.02 seconds
Started May 14 01:33:19 PM PDT 24
Finished May 14 01:48:22 PM PDT 24
Peak memory 273352 kb
Host smart-18c6cf29-db7c-4dd2-869b-86506e653c76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606202560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2606202560
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1545732290
Short name T288
Test name
Test status
Simulation time 38029262178 ps
CPU time 396.29 seconds
Started May 14 01:33:22 PM PDT 24
Finished May 14 01:39:59 PM PDT 24
Peak memory 247904 kb
Host smart-139d4f18-dcfc-40e3-aa8b-c33e2ae8c838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545732290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1545732290
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1029400104
Short name T671
Test name
Test status
Simulation time 4687804385 ps
CPU time 20.94 seconds
Started May 14 01:33:19 PM PDT 24
Finished May 14 01:33:41 PM PDT 24
Peak memory 248724 kb
Host smart-41347ed0-bdd1-4b42-86c2-9c8605608c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294
00104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1029400104
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4074158766
Short name T482
Test name
Test status
Simulation time 156386817 ps
CPU time 9.33 seconds
Started May 14 01:33:21 PM PDT 24
Finished May 14 01:33:31 PM PDT 24
Peak memory 248704 kb
Host smart-7c970739-3208-4297-9543-309bb0810808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
58766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4074158766
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.706884555
Short name T275
Test name
Test status
Simulation time 843320399 ps
CPU time 13.89 seconds
Started May 14 01:33:21 PM PDT 24
Finished May 14 01:33:36 PM PDT 24
Peak memory 248720 kb
Host smart-cb3387af-fc6f-4635-8061-8d68f92e1018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70688
4555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.706884555
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2950379011
Short name T569
Test name
Test status
Simulation time 170652088 ps
CPU time 15.3 seconds
Started May 14 01:33:21 PM PDT 24
Finished May 14 01:33:37 PM PDT 24
Peak memory 249036 kb
Host smart-d72414c2-f735-4c74-8e15-3d8a282ed478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29503
79011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2950379011
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.119641765
Short name T591
Test name
Test status
Simulation time 79068721962 ps
CPU time 2454.11 seconds
Started May 14 01:33:24 PM PDT 24
Finished May 14 02:14:19 PM PDT 24
Peak memory 289656 kb
Host smart-1a188e87-2fca-4e4d-8b31-51ac1701dc4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119641765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.119641765
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.881575774
Short name T457
Test name
Test status
Simulation time 32531346101 ps
CPU time 3878.26 seconds
Started May 14 01:33:20 PM PDT 24
Finished May 14 02:37:59 PM PDT 24
Peak memory 322096 kb
Host smart-2777b040-53cc-40f7-83b2-4adace2a5ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881575774 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.881575774
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1958714716
Short name T496
Test name
Test status
Simulation time 69166160201 ps
CPU time 3031.66 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 02:24:01 PM PDT 24
Peak memory 281552 kb
Host smart-18f2e1ec-2639-45e1-949b-9836e8cfa692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958714716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1958714716
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.782447538
Short name T619
Test name
Test status
Simulation time 1059652680 ps
CPU time 110.51 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 01:35:19 PM PDT 24
Peak memory 256924 kb
Host smart-2d45b42c-0782-4241-a68a-3b96716d1beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78244
7538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.782447538
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2916138510
Short name T66
Test name
Test status
Simulation time 583442071 ps
CPU time 34.38 seconds
Started May 14 01:33:27 PM PDT 24
Finished May 14 01:34:02 PM PDT 24
Peak memory 248880 kb
Host smart-db0e7441-3875-4a7f-b581-bb124f4685d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29161
38510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2916138510
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2739491966
Short name T224
Test name
Test status
Simulation time 115429799135 ps
CPU time 1596.15 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 02:00:05 PM PDT 24
Peak memory 273396 kb
Host smart-d598edc0-0c08-4b4a-b722-b37a6b7edf6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739491966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2739491966
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1857962989
Short name T680
Test name
Test status
Simulation time 5827850220 ps
CPU time 221.85 seconds
Started May 14 01:33:29 PM PDT 24
Finished May 14 01:37:12 PM PDT 24
Peak memory 247988 kb
Host smart-5f593ec8-3916-40e8-8e5d-404203a28915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857962989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1857962989
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1638888138
Short name T615
Test name
Test status
Simulation time 1356079991 ps
CPU time 19.93 seconds
Started May 14 01:33:24 PM PDT 24
Finished May 14 01:33:44 PM PDT 24
Peak memory 255956 kb
Host smart-83d500fc-deca-4233-8820-03a4bb8187a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
88138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1638888138
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.617785593
Short name T93
Test name
Test status
Simulation time 265305201 ps
CPU time 22.85 seconds
Started May 14 01:33:30 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 248716 kb
Host smart-bd077ff0-d909-46b4-9993-c40d85ef206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61778
5593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.617785593
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1261648493
Short name T672
Test name
Test status
Simulation time 297135547 ps
CPU time 19.92 seconds
Started May 14 01:33:27 PM PDT 24
Finished May 14 01:33:48 PM PDT 24
Peak memory 255760 kb
Host smart-265cca8c-e896-4a58-85b2-fc672d32ded8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
48493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1261648493
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2470077147
Short name T377
Test name
Test status
Simulation time 102763182 ps
CPU time 12.9 seconds
Started May 14 01:33:19 PM PDT 24
Finished May 14 01:33:33 PM PDT 24
Peak memory 248724 kb
Host smart-5bd028f7-5f11-4aca-a7be-0e401e6ea165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
77147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2470077147
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3715598026
Short name T381
Test name
Test status
Simulation time 15714877812 ps
CPU time 1430.59 seconds
Started May 14 01:33:26 PM PDT 24
Finished May 14 01:57:18 PM PDT 24
Peak memory 288932 kb
Host smart-052e36fe-50cb-4746-bd6f-8a8c5b80ea56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715598026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3715598026
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1986582699
Short name T602
Test name
Test status
Simulation time 37056346627 ps
CPU time 1741.06 seconds
Started May 14 01:33:29 PM PDT 24
Finished May 14 02:02:31 PM PDT 24
Peak memory 273360 kb
Host smart-74616c33-31f9-42b3-b4b5-6d2e21c772ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986582699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1986582699
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3832498167
Short name T608
Test name
Test status
Simulation time 746266753 ps
CPU time 45.93 seconds
Started May 14 01:33:29 PM PDT 24
Finished May 14 01:34:16 PM PDT 24
Peak memory 255804 kb
Host smart-f2efef8a-39d0-40c7-95dd-958b57b1e066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38324
98167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3832498167
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1045233078
Short name T607
Test name
Test status
Simulation time 9563193382 ps
CPU time 39.53 seconds
Started May 14 01:33:27 PM PDT 24
Finished May 14 01:34:08 PM PDT 24
Peak memory 255796 kb
Host smart-707f6405-3c81-437d-a4c4-62ddee1a275d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10452
33078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1045233078
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3439487940
Short name T31
Test name
Test status
Simulation time 195454307826 ps
CPU time 2972.93 seconds
Started May 14 01:33:26 PM PDT 24
Finished May 14 02:23:00 PM PDT 24
Peak memory 288952 kb
Host smart-a269e878-7e6d-40b2-84e4-e7d8bcc9ea07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439487940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3439487940
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.798586140
Short name T371
Test name
Test status
Simulation time 62133922327 ps
CPU time 607.61 seconds
Started May 14 01:33:27 PM PDT 24
Finished May 14 01:43:35 PM PDT 24
Peak memory 265296 kb
Host smart-e8e0e863-8a93-457c-bcc9-6de18a0305ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798586140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.798586140
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1071028529
Short name T667
Test name
Test status
Simulation time 60013061812 ps
CPU time 486.22 seconds
Started May 14 01:33:29 PM PDT 24
Finished May 14 01:41:36 PM PDT 24
Peak memory 248244 kb
Host smart-f379b46e-f4fe-4a98-a7c8-b377530132bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071028529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1071028529
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2728605797
Short name T42
Test name
Test status
Simulation time 3084391294 ps
CPU time 46.41 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 01:34:15 PM PDT 24
Peak memory 248800 kb
Host smart-290312a3-955c-4a31-b497-2f799eb56872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27286
05797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2728605797
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.4036515881
Short name T76
Test name
Test status
Simulation time 399468245 ps
CPU time 21.42 seconds
Started May 14 01:33:28 PM PDT 24
Finished May 14 01:33:50 PM PDT 24
Peak memory 255548 kb
Host smart-c3717dfd-2bc5-41b7-9caf-409d0a699c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40365
15881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4036515881
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.182500916
Short name T372
Test name
Test status
Simulation time 127296205 ps
CPU time 9.27 seconds
Started May 14 01:33:29 PM PDT 24
Finished May 14 01:33:39 PM PDT 24
Peak memory 248716 kb
Host smart-70572e34-3c47-4f35-ade0-9f88338e23c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
0916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.182500916
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2178693968
Short name T249
Test name
Test status
Simulation time 93780175279 ps
CPU time 2712.95 seconds
Started May 14 01:33:34 PM PDT 24
Finished May 14 02:18:48 PM PDT 24
Peak memory 287944 kb
Host smart-5db0f883-a8f1-4c58-b8f9-e46f2236c621
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178693968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2178693968
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1721677307
Short name T637
Test name
Test status
Simulation time 38245712359 ps
CPU time 2292.85 seconds
Started May 14 01:33:35 PM PDT 24
Finished May 14 02:11:50 PM PDT 24
Peak memory 288664 kb
Host smart-0812a486-7a9b-442d-b108-0721c1b5db95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721677307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1721677307
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2877504245
Short name T510
Test name
Test status
Simulation time 11001080796 ps
CPU time 174.22 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:36:37 PM PDT 24
Peak memory 256896 kb
Host smart-3ea01cae-464b-405f-8846-218386241772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
04245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2877504245
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.111493969
Short name T74
Test name
Test status
Simulation time 1776225815 ps
CPU time 15.09 seconds
Started May 14 01:33:33 PM PDT 24
Finished May 14 01:33:49 PM PDT 24
Peak memory 253036 kb
Host smart-52bc110c-a6c0-45ae-bd74-d80001dccd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149
3969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.111493969
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.550730060
Short name T669
Test name
Test status
Simulation time 28676794949 ps
CPU time 996.35 seconds
Started May 14 01:33:35 PM PDT 24
Finished May 14 01:50:13 PM PDT 24
Peak memory 268408 kb
Host smart-275a7362-df2e-433d-9e9e-8771cbfbbbfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550730060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.550730060
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3816027021
Short name T512
Test name
Test status
Simulation time 41041318996 ps
CPU time 408.39 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:40:31 PM PDT 24
Peak memory 255980 kb
Host smart-d86bf286-7365-4ba8-beb7-e80c20d477d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816027021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3816027021
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1444063695
Short name T58
Test name
Test status
Simulation time 1105831653 ps
CPU time 35.36 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:34:18 PM PDT 24
Peak memory 248712 kb
Host smart-052aa6de-706b-4a57-9b66-f260e865d808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
63695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1444063695
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.289843945
Short name T685
Test name
Test status
Simulation time 2769498303 ps
CPU time 43.93 seconds
Started May 14 01:33:34 PM PDT 24
Finished May 14 01:34:20 PM PDT 24
Peak memory 249204 kb
Host smart-9a3a11cf-9e00-4647-bcdc-80440d5be976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28984
3945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.289843945
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2984693125
Short name T703
Test name
Test status
Simulation time 1071173792 ps
CPU time 21.8 seconds
Started May 14 01:33:35 PM PDT 24
Finished May 14 01:33:58 PM PDT 24
Peak memory 249140 kb
Host smart-9675b2ed-bf88-40e4-a718-f28d257f5eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29846
93125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2984693125
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.223335508
Short name T617
Test name
Test status
Simulation time 283147729 ps
CPU time 24.94 seconds
Started May 14 01:33:35 PM PDT 24
Finished May 14 01:34:01 PM PDT 24
Peak memory 248720 kb
Host smart-09ca88c4-7484-4ec7-9ee6-17d9fec87a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22333
5508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.223335508
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3635392535
Short name T620
Test name
Test status
Simulation time 22020781161 ps
CPU time 2208.44 seconds
Started May 14 01:33:42 PM PDT 24
Finished May 14 02:10:32 PM PDT 24
Peak memory 298104 kb
Host smart-07414162-8e57-4d73-bb62-635c70782ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635392535 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3635392535
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2265073374
Short name T108
Test name
Test status
Simulation time 99657739340 ps
CPU time 1592.16 seconds
Started May 14 01:33:42 PM PDT 24
Finished May 14 02:00:15 PM PDT 24
Peak memory 273416 kb
Host smart-78ba377f-fa61-454e-9cf4-75d29e83bb2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265073374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2265073374
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1912635799
Short name T238
Test name
Test status
Simulation time 479800199 ps
CPU time 26.89 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:34:10 PM PDT 24
Peak memory 248952 kb
Host smart-163d29ec-7111-492a-934e-eb9cd72687bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
35799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1912635799
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3330399557
Short name T639
Test name
Test status
Simulation time 952416703 ps
CPU time 32.15 seconds
Started May 14 01:33:43 PM PDT 24
Finished May 14 01:34:16 PM PDT 24
Peak memory 255464 kb
Host smart-ac37a05f-709e-45e7-ada6-5c4733f36e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
99557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3330399557
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2597002342
Short name T8
Test name
Test status
Simulation time 237664315115 ps
CPU time 3444.41 seconds
Started May 14 01:33:42 PM PDT 24
Finished May 14 02:31:08 PM PDT 24
Peak memory 287756 kb
Host smart-014e7223-3305-4f4e-abf3-bd0a04100691
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597002342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2597002342
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.373310078
Short name T545
Test name
Test status
Simulation time 12295869144 ps
CPU time 835.7 seconds
Started May 14 01:33:42 PM PDT 24
Finished May 14 01:47:39 PM PDT 24
Peak memory 268260 kb
Host smart-50dfaf68-6f78-4335-979a-58e81eba40ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373310078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.373310078
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1092536538
Short name T291
Test name
Test status
Simulation time 11852062129 ps
CPU time 125.23 seconds
Started May 14 01:33:44 PM PDT 24
Finished May 14 01:35:50 PM PDT 24
Peak memory 248140 kb
Host smart-7d86a835-df87-435c-a6d2-89445672e00c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092536538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1092536538
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1174953960
Short name T378
Test name
Test status
Simulation time 476249838 ps
CPU time 22.41 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 256044 kb
Host smart-ca91a58b-7a06-4298-b78c-c899fb44054d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749
53960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1174953960
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3095415987
Short name T384
Test name
Test status
Simulation time 485191802 ps
CPU time 13.61 seconds
Started May 14 01:33:42 PM PDT 24
Finished May 14 01:33:57 PM PDT 24
Peak memory 247412 kb
Host smart-7cd24961-e1dc-492e-8d19-517a5a942b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
15987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3095415987
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.123814923
Short name T272
Test name
Test status
Simulation time 223421250 ps
CPU time 18.48 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 01:34:00 PM PDT 24
Peak memory 254468 kb
Host smart-bd4f1546-11e4-4513-9659-4999d84a3304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12381
4923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.123814923
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.97493119
Short name T500
Test name
Test status
Simulation time 4073877728 ps
CPU time 60.74 seconds
Started May 14 01:33:43 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 248772 kb
Host smart-c28b3986-9ea1-4ecc-8c49-31fa43720ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97493
119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.97493119
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.337312685
Short name T655
Test name
Test status
Simulation time 60276570412 ps
CPU time 1774.45 seconds
Started May 14 01:33:41 PM PDT 24
Finished May 14 02:03:16 PM PDT 24
Peak memory 298604 kb
Host smart-2b467b8c-b001-42ba-8a61-e6e9ea46fad4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337312685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.337312685
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2029652367
Short name T209
Test name
Test status
Simulation time 177158189 ps
CPU time 3.7 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:30:52 PM PDT 24
Peak memory 248912 kb
Host smart-1bbcbcf8-1856-4944-be09-c15459641066
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2029652367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2029652367
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1841310644
Short name T519
Test name
Test status
Simulation time 458486734011 ps
CPU time 1612.03 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:57:41 PM PDT 24
Peak memory 272952 kb
Host smart-a2e100c6-08d8-4af4-97eb-e9aba2e613f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841310644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1841310644
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2877577398
Short name T214
Test name
Test status
Simulation time 248050623 ps
CPU time 8.52 seconds
Started May 14 01:30:45 PM PDT 24
Finished May 14 01:30:54 PM PDT 24
Peak memory 240560 kb
Host smart-a6565d03-3604-4ff4-a5bc-426fdfa77930
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2877577398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2877577398
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4036625379
Short name T675
Test name
Test status
Simulation time 1226333593 ps
CPU time 14.62 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:31:03 PM PDT 24
Peak memory 254688 kb
Host smart-f7a0186e-e5f5-4d69-8742-1f60c5c2500c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
25379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4036625379
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3398270055
Short name T490
Test name
Test status
Simulation time 287362251 ps
CPU time 24.49 seconds
Started May 14 01:30:50 PM PDT 24
Finished May 14 01:31:16 PM PDT 24
Peak memory 248724 kb
Host smart-ec4a915c-87b0-43b3-8303-4f332a4074a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
70055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3398270055
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2797062820
Short name T663
Test name
Test status
Simulation time 50015891572 ps
CPU time 2784.08 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 02:17:12 PM PDT 24
Peak memory 285660 kb
Host smart-cf4d8cf7-bc16-4c3c-aaf6-f82936b01bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797062820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2797062820
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.394382120
Short name T304
Test name
Test status
Simulation time 8329710140 ps
CPU time 90.22 seconds
Started May 14 01:30:50 PM PDT 24
Finished May 14 01:32:22 PM PDT 24
Peak memory 248212 kb
Host smart-36ec1513-b6c6-4e87-95af-b6c596d965d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394382120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.394382120
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.307788381
Short name T392
Test name
Test status
Simulation time 753824604 ps
CPU time 25.36 seconds
Started May 14 01:30:39 PM PDT 24
Finished May 14 01:31:06 PM PDT 24
Peak memory 255072 kb
Host smart-db302ba3-0874-4128-8efc-42dbe45abb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30778
8381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.307788381
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3437635482
Short name T523
Test name
Test status
Simulation time 227821053 ps
CPU time 21.65 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:09 PM PDT 24
Peak memory 254788 kb
Host smart-bb58e9c1-d376-4fc5-8cd3-55af6ded61b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34376
35482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3437635482
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3843340817
Short name T263
Test name
Test status
Simulation time 1031948271 ps
CPU time 61.51 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:49 PM PDT 24
Peak memory 255356 kb
Host smart-34a58ff7-eb26-41c1-a450-1f0f4cac22ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38433
40817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3843340817
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4290641828
Short name T618
Test name
Test status
Simulation time 390947078 ps
CPU time 19.75 seconds
Started May 14 01:30:40 PM PDT 24
Finished May 14 01:31:01 PM PDT 24
Peak memory 248716 kb
Host smart-7259276a-aa50-40b8-8816-0c3683abaee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
41828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4290641828
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3516062945
Short name T686
Test name
Test status
Simulation time 229849324326 ps
CPU time 3997.62 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 02:37:27 PM PDT 24
Peak memory 297540 kb
Host smart-80ac0fa4-6cd1-488b-b7ea-c611970053b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516062945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3516062945
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2711197956
Short name T241
Test name
Test status
Simulation time 913401812543 ps
CPU time 5967.71 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 03:10:18 PM PDT 24
Peak memory 339092 kb
Host smart-9aede43b-0726-4a2c-ae73-af151351a3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711197956 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2711197956
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1859721047
Short name T39
Test name
Test status
Simulation time 13503280 ps
CPU time 2.42 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:30:51 PM PDT 24
Peak memory 248976 kb
Host smart-d4e5a130-d745-4bdd-8bfa-4ae6f43c7522
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1859721047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1859721047
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2603189110
Short name T395
Test name
Test status
Simulation time 38878403358 ps
CPU time 2266.6 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 02:08:36 PM PDT 24
Peak memory 289460 kb
Host smart-936d0dba-24f5-496b-bfc5-30bf9f851f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603189110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2603189110
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1045055546
Short name T572
Test name
Test status
Simulation time 3279851554 ps
CPU time 35.86 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:31:24 PM PDT 24
Peak memory 240620 kb
Host smart-71aa3eb0-adff-4bb6-b1fc-9fe148c3bf97
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1045055546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1045055546
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.464370469
Short name T687
Test name
Test status
Simulation time 3210941838 ps
CPU time 175.16 seconds
Started May 14 01:30:50 PM PDT 24
Finished May 14 01:33:46 PM PDT 24
Peak memory 256928 kb
Host smart-cc38049b-8501-48bc-ae8b-eee6c880add8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46437
0469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.464370469
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3064694910
Short name T340
Test name
Test status
Simulation time 381950042 ps
CPU time 32.51 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:19 PM PDT 24
Peak memory 248732 kb
Host smart-18d7ef39-2f07-4eb1-a2f6-e55056d1d233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30646
94910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3064694910
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3205480071
Short name T314
Test name
Test status
Simulation time 25723842325 ps
CPU time 1513.36 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:56:01 PM PDT 24
Peak memory 273312 kb
Host smart-2aa7d4d8-2546-4041-b187-b38b475a8398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205480071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3205480071
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.382236836
Short name T584
Test name
Test status
Simulation time 77869984932 ps
CPU time 2435.61 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 02:11:24 PM PDT 24
Peak memory 272652 kb
Host smart-ce66ec9c-5a96-47c7-851b-4aada5275e29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382236836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.382236836
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.963964944
Short name T633
Test name
Test status
Simulation time 5395844450 ps
CPU time 40.56 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:31:29 PM PDT 24
Peak memory 256112 kb
Host smart-38711cc4-79a1-4bbc-b8c2-8556e8b70dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96396
4944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.963964944
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1286566481
Short name T517
Test name
Test status
Simulation time 773291436 ps
CPU time 31.8 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:31:21 PM PDT 24
Peak memory 255440 kb
Host smart-ad131e03-f22e-4a23-ba29-de04da291804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12865
66481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1286566481
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1965373726
Short name T640
Test name
Test status
Simulation time 459759489 ps
CPU time 16.65 seconds
Started May 14 01:30:50 PM PDT 24
Finished May 14 01:31:08 PM PDT 24
Peak memory 254208 kb
Host smart-aabd9d38-c994-44db-aeca-1e0b33a0f232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
73726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1965373726
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2184724644
Short name T701
Test name
Test status
Simulation time 771740806 ps
CPU time 43.61 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:31:33 PM PDT 24
Peak memory 248720 kb
Host smart-6ec4ea99-6cb4-4ee1-9a06-c74531fd26b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
24644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2184724644
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.900449520
Short name T183
Test name
Test status
Simulation time 5850180218 ps
CPU time 65.76 seconds
Started May 14 01:30:46 PM PDT 24
Finished May 14 01:31:53 PM PDT 24
Peak memory 256596 kb
Host smart-8150026a-28f6-4588-a485-8fd40001aad7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900449520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.900449520
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2502167938
Short name T267
Test name
Test status
Simulation time 63250483908 ps
CPU time 1675.73 seconds
Started May 14 01:30:47 PM PDT 24
Finished May 14 01:58:44 PM PDT 24
Peak memory 289880 kb
Host smart-42d15015-8ff9-4ebb-8b94-447611966627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502167938 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2502167938
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.660512499
Short name T195
Test name
Test status
Simulation time 117830392 ps
CPU time 3.99 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:01 PM PDT 24
Peak memory 248960 kb
Host smart-327ee3ea-2f6f-4689-b2da-6d68731419fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=660512499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.660512499
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2786383127
Short name T75
Test name
Test status
Simulation time 8466490945 ps
CPU time 865.75 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:45:23 PM PDT 24
Peak memory 268288 kb
Host smart-db141685-4403-4a13-8482-be55053a71a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786383127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2786383127
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3210821056
Short name T406
Test name
Test status
Simulation time 223560059 ps
CPU time 11.89 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:31:09 PM PDT 24
Peak memory 248748 kb
Host smart-f131ad17-4917-4728-b3c4-36d8cc959ce2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210821056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3210821056
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2021315963
Short name T557
Test name
Test status
Simulation time 3675073296 ps
CPU time 61.44 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:58 PM PDT 24
Peak memory 256780 kb
Host smart-5bf8628a-df98-406b-8fc6-3ed368edd065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20213
15963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2021315963
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.4134104035
Short name T57
Test name
Test status
Simulation time 604460944 ps
CPU time 36.07 seconds
Started May 14 01:30:57 PM PDT 24
Finished May 14 01:31:35 PM PDT 24
Peak memory 255924 kb
Host smart-422a967b-f092-4e0d-adaa-b4377c7c76d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41341
04035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4134104035
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2947597883
Short name T319
Test name
Test status
Simulation time 133213904634 ps
CPU time 2201.44 seconds
Started May 14 01:30:57 PM PDT 24
Finished May 14 02:07:40 PM PDT 24
Peak memory 286988 kb
Host smart-7c0b4838-9d11-4f7c-bbc8-bde7e91987d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947597883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2947597883
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3842021965
Short name T522
Test name
Test status
Simulation time 55329395018 ps
CPU time 1287.95 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:52:25 PM PDT 24
Peak memory 281548 kb
Host smart-3c115991-7c51-4331-9c1f-d91bfa1cf04d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842021965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3842021965
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2605217370
Short name T300
Test name
Test status
Simulation time 37504400527 ps
CPU time 379.74 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 247960 kb
Host smart-470a3dde-6756-4e0b-9546-1498051ba9db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605217370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2605217370
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.953990799
Short name T635
Test name
Test status
Simulation time 1202345855 ps
CPU time 38.59 seconds
Started May 14 01:30:52 PM PDT 24
Finished May 14 01:31:32 PM PDT 24
Peak memory 248688 kb
Host smart-f93f8a74-5c03-405f-90c1-130eb523771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95399
0799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.953990799
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2887967302
Short name T527
Test name
Test status
Simulation time 2850388425 ps
CPU time 81.89 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:32:19 PM PDT 24
Peak memory 255652 kb
Host smart-f04eddc7-566f-4646-b45b-12e8ecda509f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
67302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2887967302
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.516800732
Short name T616
Test name
Test status
Simulation time 45275316 ps
CPU time 4.23 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:31:00 PM PDT 24
Peak memory 239172 kb
Host smart-97e3ce46-c18f-46b2-a742-cc84b72c80d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51680
0732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.516800732
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.826320615
Short name T530
Test name
Test status
Simulation time 219042786 ps
CPU time 13.51 seconds
Started May 14 01:30:57 PM PDT 24
Finished May 14 01:31:12 PM PDT 24
Peak memory 248724 kb
Host smart-e8f607da-bec2-421f-b5e3-584626f7e349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82632
0615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.826320615
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1729038606
Short name T269
Test name
Test status
Simulation time 187442832084 ps
CPU time 2917.69 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 02:19:35 PM PDT 24
Peak memory 281628 kb
Host smart-bd78f617-9768-4740-bc62-c8ec11bc5df4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729038606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1729038606
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2345032368
Short name T198
Test name
Test status
Simulation time 36474877 ps
CPU time 3.41 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:30:59 PM PDT 24
Peak memory 248824 kb
Host smart-3875daab-f5a4-4b64-8dee-55c864fcc126
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2345032368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2345032368
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.763561133
Short name T670
Test name
Test status
Simulation time 163467395590 ps
CPU time 2069.93 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 02:05:26 PM PDT 24
Peak memory 273344 kb
Host smart-ce01edc3-909f-4674-8381-85e3d4044179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763561133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.763561133
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1937899043
Short name T587
Test name
Test status
Simulation time 156869786 ps
CPU time 10.29 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:31:07 PM PDT 24
Peak memory 248752 kb
Host smart-df3599cf-b4e4-41fd-b2cd-c02f122c6273
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1937899043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1937899043
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2449608474
Short name T497
Test name
Test status
Simulation time 5341152382 ps
CPU time 123.58 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:33:01 PM PDT 24
Peak memory 256864 kb
Host smart-c4076d43-f8c9-4766-8e16-b87452f189e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24496
08474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2449608474
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2560762893
Short name T551
Test name
Test status
Simulation time 111584811 ps
CPU time 8.16 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:31:04 PM PDT 24
Peak memory 253036 kb
Host smart-83e84448-8798-4c5f-ab95-ef9bb6f41a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
62893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2560762893
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3402060218
Short name T312
Test name
Test status
Simulation time 125999266834 ps
CPU time 1890.89 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 02:02:28 PM PDT 24
Peak memory 267176 kb
Host smart-eef00524-f943-41a9-9184-fbcb196ef8e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402060218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3402060218
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1754092958
Short name T428
Test name
Test status
Simulation time 16073870004 ps
CPU time 1096.03 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:49:13 PM PDT 24
Peak memory 265236 kb
Host smart-09012d93-99c4-4954-8789-3e17feb60a17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754092958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1754092958
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3903907680
Short name T589
Test name
Test status
Simulation time 20359233457 ps
CPU time 224.66 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:34:40 PM PDT 24
Peak memory 248004 kb
Host smart-26d70cc4-b765-4b43-9a93-1bc4c4aff7e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903907680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3903907680
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2945599224
Short name T560
Test name
Test status
Simulation time 116160563 ps
CPU time 5.27 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:31:00 PM PDT 24
Peak memory 240536 kb
Host smart-bdff415a-f16d-4c88-8ba7-4c9de5f0c676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
99224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2945599224
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3968047753
Short name T632
Test name
Test status
Simulation time 823100848 ps
CPU time 47.45 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:44 PM PDT 24
Peak memory 248668 kb
Host smart-929ca78d-162f-43ea-b596-a2d86ebf3c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39680
47753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3968047753
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3830419569
Short name T521
Test name
Test status
Simulation time 314054200 ps
CPU time 19.71 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:31:15 PM PDT 24
Peak memory 247500 kb
Host smart-3ce220f3-220f-4b66-9d7a-981842cdf993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38304
19569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3830419569
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2285829728
Short name T367
Test name
Test status
Simulation time 947306977 ps
CPU time 22.23 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:18 PM PDT 24
Peak memory 248720 kb
Host smart-88562057-9ff8-46e0-a985-35f375dc44dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22858
29728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2285829728
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2992157885
Short name T205
Test name
Test status
Simulation time 35611382 ps
CPU time 3.36 seconds
Started May 14 01:30:57 PM PDT 24
Finished May 14 01:31:02 PM PDT 24
Peak memory 248848 kb
Host smart-b8e54bd1-a490-4fd2-a908-8b7eafd98101
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2992157885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2992157885
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2745720067
Short name T515
Test name
Test status
Simulation time 17060286450 ps
CPU time 1212.38 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:51:09 PM PDT 24
Peak memory 273388 kb
Host smart-4789dd8c-f801-4fce-be31-32eafd823bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745720067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2745720067
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1725002016
Short name T631
Test name
Test status
Simulation time 508661283 ps
CPU time 9.5 seconds
Started May 14 01:30:58 PM PDT 24
Finished May 14 01:31:09 PM PDT 24
Peak memory 248760 kb
Host smart-1d1b0dcd-26da-4aff-9040-f77627388d44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1725002016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1725002016
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1226924007
Short name T344
Test name
Test status
Simulation time 1853643855 ps
CPU time 115.98 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:32:52 PM PDT 24
Peak memory 256708 kb
Host smart-d35fca76-869c-4000-bdb5-b56521ee8f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
24007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1226924007
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.408782661
Short name T346
Test name
Test status
Simulation time 75579645 ps
CPU time 4 seconds
Started May 14 01:30:55 PM PDT 24
Finished May 14 01:31:01 PM PDT 24
Peak memory 240516 kb
Host smart-a95581f6-c9b3-47dc-8884-1fe4d1e5ed87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40878
2661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.408782661
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3217289161
Short name T250
Test name
Test status
Simulation time 27742422282 ps
CPU time 1513.47 seconds
Started May 14 01:30:57 PM PDT 24
Finished May 14 01:56:12 PM PDT 24
Peak memory 270304 kb
Host smart-4cf6946d-26a3-4039-8cbf-9e89b4658e6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217289161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3217289161
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3463111814
Short name T440
Test name
Test status
Simulation time 50458379688 ps
CPU time 1309.5 seconds
Started May 14 01:30:53 PM PDT 24
Finished May 14 01:52:44 PM PDT 24
Peak memory 289584 kb
Host smart-0dc0f9ca-e4cb-4860-84ca-9d4b8d49016e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463111814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3463111814
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4178848693
Short name T298
Test name
Test status
Simulation time 7830949008 ps
CPU time 316.79 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:36:12 PM PDT 24
Peak memory 248316 kb
Host smart-9fe4186b-21f3-4113-bf09-3d79dfede698
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178848693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4178848693
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.674788494
Short name T574
Test name
Test status
Simulation time 2672033082 ps
CPU time 46.75 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:31:44 PM PDT 24
Peak memory 255948 kb
Host smart-b4a2cb75-fcef-4e80-a955-450ad2d68532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67478
8494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.674788494
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.339523962
Short name T447
Test name
Test status
Simulation time 669543246 ps
CPU time 37.57 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:31:33 PM PDT 24
Peak memory 255516 kb
Host smart-8feca96a-be2d-426a-b95a-a8ebca855990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
3962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.339523962
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3483920701
Short name T379
Test name
Test status
Simulation time 682417052 ps
CPU time 23.6 seconds
Started May 14 01:30:56 PM PDT 24
Finished May 14 01:31:21 PM PDT 24
Peak memory 253976 kb
Host smart-f034f974-00d6-46b5-8b33-c9dba56544de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
20701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3483920701
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2656426503
Short name T625
Test name
Test status
Simulation time 707152865 ps
CPU time 47.37 seconds
Started May 14 01:31:01 PM PDT 24
Finished May 14 01:31:49 PM PDT 24
Peak memory 248740 kb
Host smart-8d752ae3-01a3-4348-8ddf-0362bffe075c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26564
26503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2656426503
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2290677669
Short name T14
Test name
Test status
Simulation time 13620323466 ps
CPU time 1262.78 seconds
Started May 14 01:30:54 PM PDT 24
Finished May 14 01:51:58 PM PDT 24
Peak memory 284312 kb
Host smart-395cc304-a734-4edd-be74-679a35ccd163
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290677669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2290677669
Directory /workspace/9.alert_handler_stress_all/latest
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