Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	101399	1			T1	22		T5	1498		T8	296
class_i[0x1]	54450	1			T5	1320		T31	9		T33	26
class_i[0x2]	59419	1			T14	1020		T20	1		T31	4
class_i[0x3]	52198	1			T6	2		T7	4995		T8	3063

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67766	1			T1	2		T14	10		T5	792
alert[0x1]	66384	1			T1	2		T14	960		T5	710
alert[0x2]	64936	1			T1	2		T6	1		T14	26
alert[0x3]	68380	1			T1	16		T6	1		T14	24

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

267191

1

T1

22

T14

1020

T5

2818

esc_ping_fail

275

1

T6

2

T17

1

T20

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	67688	1			T1	2		T14	10		T5	792
esc_integrity_fail	alert[0x1]	66311	1			T1	2		T14	960		T5	710
esc_integrity_fail	alert[0x2]	64872	1			T1	2		T14	26		T5	600
esc_integrity_fail	alert[0x3]	68320	1			T1	16		T14	24		T5	716
esc_ping_fail	alert[0x0]	78	1			T31	1		T69	1		T318	1
esc_ping_fail	alert[0x1]	73	1			T20	1		T31	1		T69	4
esc_ping_fail	alert[0x2]	64	1			T6	1		T31	1		T69	1
esc_ping_fail	alert[0x3]	60	1			T6	1		T17	1		T69	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	101343	1			T1	22		T5	1498		T8	296
esc_integrity_fail	class_i[0x1]	54400	1			T5	1320		T31	6		T33	26
esc_integrity_fail	class_i[0x2]	59336	1			T14	1020		T31	4		T33	8
esc_integrity_fail	class_i[0x3]	52112	1			T7	4995		T8	3063		T80	4985
esc_ping_fail	class_i[0x0]	56	1			T17	1		T73	1		T318	1
esc_ping_fail	class_i[0x1]	50	1			T31	3		T329	11		T324	1
esc_ping_fail	class_i[0x2]	83	1			T20	1		T69	1		T73	2
esc_ping_fail	class_i[0x3]	86	1			T6	2		T69	7		T317	2