Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	719502818	0	0	628
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	719502818	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	719502818	719342415	0	0
tb.dut.CheckAccuCntDw	0	0	628	628	0	0
tb.dut.CheckEscCntDw	0	0	628	628	0	0
tb.dut.CheckNAlerts	0	0	628	628	0	0
tb.dut.CheckNClasses	0	0	628	628	0	0
tb.dut.CheckNEscSev	0	0	628	628	0	0
tb.dut.CrashdumpKnownO_A	0	0	719502818	719342415	0	0
tb.dut.EdnKnownO_A	0	0	719502818	719342415	0	0
tb.dut.EscPKnownO_A	0	0	719502818	719342415	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	719502818	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	719502818	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	719502818	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	719502818	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	719502818	70	0	0
tb.dut.IrqAKnownO_A	0	0	719502818	719342415	0	0
tb.dut.IrqBKnownO_A	0	0	719502818	719342415	0	0
tb.dut.IrqCKnownO_A	0	0	719502818	719342415	0	0
tb.dut.IrqDKnownO_A	0	0	719502818	719342415	0	0
tb.dut.TlAReadyKnownO_A	0	0	719502818	719342415	0	0
tb.dut.TlDValidKnownO_A	0	0	719502818	719342415	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	746200617	3949487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	746200617	14792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	746200617	15897	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	746200617	15899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	746200617	15272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	746200617	14923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	746200617	15605	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	746200617	15386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	746200617	14999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	746200617	14817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	746200617	14596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	746200617	14414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	746200617	14660	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	746200617	14412	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	746200617	15762	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	746200617	16011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	746200617	14926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	746200617	16042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	746200617	14765	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	746200617	15512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	746200617	15546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	746200617	16419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	746200617	14408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	746200617	15989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	746200617	16632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	746200617	15708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	746200617	15940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	746200617	14732	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	746200617	15306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	746200617	15085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	746200617	14727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	746200617	16131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	746200617	15449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	746200617	15676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	746200617	14803	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	746200617	14698	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	746200617	15334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	746200617	14893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	746200617	15386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	746200617	15564	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	746200617	16603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	746200617	15835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	746200617	15050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	746200617	15291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	746200617	15657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	746200617	16263	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	746200617	14455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	746200617	15337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	746200617	15629	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	746200617	14874	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	746200617	16635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	746200617	15443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	746200617	15161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	746200617	14675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	746200617	14946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	746200617	14945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	746200617	15802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	746200617	16214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	746200617	14544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	746200617	16535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	746200617	14693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	746200617	14802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	746200617	14895	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	746200617	16652	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	746200617	14699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	746200617	15569	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	746200617	14663	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	746200617	14823	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	746200617	15503	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	746200617	14297	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	746200617	31664	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	746200617	14925	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	746200617	14771	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	746200617	15230	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	746200617	16563	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	746200617	15026	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	746200617	14587	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	746200617	14821	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	746200617	16410	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	719502818	5816	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	719502818	255089	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	719502818	367837345	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	719502818	254	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	719502818	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	719502818	38	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	719502818	357	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	719363146	271949284	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	719502818	900	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	719502818	881	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	719502818	865	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	719502818	847	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	719502818	957	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	719502818	125763	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	719502818	858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	719502818	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	719502818	1263	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	719502818	1053	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	719361440	719289953	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	719502818	719342415	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	719502818	2667	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	719502818	202829	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	719502818	409948132	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	719502818	240	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	719502818	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	719502818	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	719502818	259	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	719363146	320786669	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	719502818	637	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	719502818	626	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	719502818	608	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	719502818	600	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	719502818	666	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	719502818	85073	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	719502818	573	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	719502818	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	719502818	1275	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	719502818	1065	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	719361440	719289953	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	719502818	719342415	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	719502818	2062	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	719502818	159150	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	719502818	454121651	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	719502818	272	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	719502818	478	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	719502818	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	719502818	198	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	719363146	374282905	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	719502818	561	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	719502818	558	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	719502818	550	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	719502818	536	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	719502818	687	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	719502818	89056	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	719502818	596	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	719502818	70	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	719502818	1271	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	719502818	1061	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	719361440	719289953	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	719502818	719342415	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	719502818	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	719502818	2976	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	719502818	175487	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	719502818	380490250	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	719502818	223	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	719502818	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	719502818	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	719502818	207	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	719363146	313169246	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	719502818	606	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	719502818	600	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	719502818	597	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	719502818	591	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	719502818	792	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	719502818	100825	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	719502818	700	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	719502818	68	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	719502818	1219	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	719502818	1009	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	719361440	719289953	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	719502818	719342415	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	746200617	148775369	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	746200617	745514963	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	746200617	745514963	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	746200617	196401037	0	0
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tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
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tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
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tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
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tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0

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