Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	180	1			T3	1		T4	1		T5	2
index[0x1]	169	1			T1	1		T8	3		T22	1
index[0x2]	177	1			T12	1		T4	2		T8	1
index[0x3]	158	1			T1	1		T13	1		T17	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	198	1			T12	1		T4	2		T13	1
lens_less_than_1000[1]	144	1			T3	1		T4	1		T5	1
lens_less_than_1000[2]	89	1			T17	1		T19	2		T74	1
lens_less_than_1000[3]	81	1			T17	1		T33	1		T89	1
lens_less_than_1000[4]	50	1			T5	1		T8	1		T17	1
lens_less_than_1000[5]	42	1			T1	1		T8	3		T45	1
lens_less_than_1000[6]	33	1			T126	1		T30	3		T104	1
lens_less_than_1000[7]	24	1			T1	1		T70	1		T30	1
lens_less_than_1000[8]	11	1			T134	1		T144	2		T216	1
lens_less_than_1000[9]	5	1			T22	1		T110	1		T139	1
len_2	7	1			T66	1		T296	1		T98	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9] , len_2]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T4	1		T68	1		T30	1
index[0x0]	lens_less_than_1000[1]	34	1			T3	1		T5	1		T33	2
index[0x0]	lens_less_than_1000[2]	21	1			T90	1		T28	1		T58	1
index[0x0]	lens_less_than_1000[3]	21	1			T33	1		T297	1		T298	1
index[0x0]	lens_less_than_1000[4]	18	1			T5	1		T72	1		T77	1
index[0x0]	lens_less_than_1000[5]	6	1			T283	1		T138	1		T299	1
index[0x0]	lens_less_than_1000[6]	10	1			T126	1		T148	1		T124	1
index[0x0]	lens_less_than_1000[7]	7	1			T286	4		T300	1		T142	1
index[0x0]	lens_less_than_1000[8]	2	1			T134	1		T216	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T22	1		-	-		-	-
index[0x0]	len_2	1	1			T301	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	48	1			T78	1		T302	1		T79	2
index[0x1]	lens_less_than_1000[1]	36	1			T22	1		T88	1		T55	1
index[0x1]	lens_less_than_1000[2]	23	1			T74	1		T76	1		T94	1
index[0x1]	lens_less_than_1000[3]	17	1			T79	1		T28	1		T91	2
index[0x1]	lens_less_than_1000[4]	16	1			T54	1		T262	1		T62	1
index[0x1]	lens_less_than_1000[5]	13	1			T1	1		T8	3		T137	2
index[0x1]	lens_less_than_1000[6]	10	1			T54	1		T58	1		T106	1
index[0x1]	lens_less_than_1000[7]	4	1			T265	1		T303	1		T304	1
index[0x1]	lens_less_than_1000[8]	2	1			T144	1		T305	1		-	-
index[0x2]	lens_less_than_1000[0]	47	1			T12	1		T4	1		T306	1
index[0x2]	lens_less_than_1000[1]	41	1			T4	1		T306	1		T53	1
index[0x2]	lens_less_than_1000[2]	26	1			T19	2		T87	1		T79	1
index[0x2]	lens_less_than_1000[3]	24	1			T17	1		T89	1		T56	1
index[0x2]	lens_less_than_1000[4]	9	1			T8	1		T307	1		T58	1
index[0x2]	lens_less_than_1000[5]	9	1			T45	1		T30	1		T308	4
index[0x2]	lens_less_than_1000[6]	5	1			T104	1		T101	1		T309	1
index[0x2]	lens_less_than_1000[7]	10	1			T70	1		T30	1		T280	1
index[0x2]	lens_less_than_1000[8]	1	1			T310	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	3	1			T110	1		T265	1		T100	1
index[0x2]	len_2	2	1			T66	1		T296	1		-	-
index[0x3]	lens_less_than_1000[0]	44	1			T13	1		T68	1		T85	1
index[0x3]	lens_less_than_1000[1]	33	1			T32	1		T311	1		T28	1
index[0x3]	lens_less_than_1000[2]	19	1			T17	1		T77	1		T44	1
index[0x3]	lens_less_than_1000[3]	19	1			T312	1		T28	1		T59	1
index[0x3]	lens_less_than_1000[4]	7	1			T17	1		T148	1		T77	1
index[0x3]	lens_less_than_1000[5]	14	1			T308	4		T41	1		T58	1
index[0x3]	lens_less_than_1000[6]	8	1			T30	3		T259	1		T313	1
index[0x3]	lens_less_than_1000[7]	3	1			T1	1		T250	1		T265	1
index[0x3]	lens_less_than_1000[8]	6	1			T144	1		T64	1		T314	1
index[0x3]	lens_less_than_1000[9]	1	1			T139	1		-	-		-	-
index[0x3]	len_2	4	1			T98	1		T315	2		T289	1