Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T5	1		T8	1		T82	1
class_index[0x1]	69	1			T4	2		T5	1		T75	1
class_index[0x2]	70	1			T5	2		T66	1		T88	1
class_index[0x3]	68	1			T1	1		T14	1		T114	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	99	1			T1	1		T4	2		T14	1
intr_timeout_cnt[1]	57	1			T8	1		T66	1		T27	2
intr_timeout_cnt[2]	25	1			T89	1		T60	4		T123	1
intr_timeout_cnt[3]	24	1			T5	1		T87	1		T28	1
intr_timeout_cnt[4]	21	1			T89	1		T28	1		T91	1
intr_timeout_cnt[5]	7	1			T38	1		T94	1		T276	1
intr_timeout_cnt[6]	9	1			T75	1		T88	1		T114	1
intr_timeout_cnt[7]	9	1			T5	1		T38	1		T277	1
intr_timeout_cnt[8]	9	1			T62	3		T110	1		T278	1
intr_timeout_cnt[9]	8	1			T88	1		T62	1		T29	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T5	1		T82	1		T95	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T8	1		T27	1		T28	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T123	1		T279	1		T120	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T280	1		T118	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T122	1		T281	1		T282	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T94	1		T283	2		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T38	1		T280	1		T284	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T285	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T88	1		T29	1		T138	1
class_index[0x1]	intr_timeout_cnt[0]	28	1			T4	2		T82	1		T90	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T92	1		T113	1		T286	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T89	1		T118	3		T287	1
class_index[0x1]	intr_timeout_cnt[3]	10	1			T5	1		T87	1		T28	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T288	1		T284	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T38	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T75	1		T138	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T277	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T278	1		T284	1		T289	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T290	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T5	1		T91	1		T108	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T66	1		T37	1		T92	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T60	4		T291	1		T118	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T93	1		T112	1		T110	1
class_index[0x2]	intr_timeout_cnt[4]	9	1			T29	1		T138	2		T287	2
class_index[0x2]	intr_timeout_cnt[5]	1	1			T292	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T88	1		T284	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	4	1			T5	1		T98	1		T293	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T110	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T62	1		T264	1		T285	1
class_index[0x3]	intr_timeout_cnt[0]	21	1			T1	1		T14	1		T60	2
class_index[0x3]	intr_timeout_cnt[1]	16	1			T27	1		T90	1		T38	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T29	1		T116	1		T280	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T95	1		T116	1		T294	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T89	1		T28	1		T91	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T276	1		T62	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T114	1		T144	1		T64	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T295	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T62	3		T284	1		-	-