Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	372117	1			T1	2172		T3	33		T12	63
all_values[1]	372117	1			T1	2172		T3	33		T12	63
all_values[2]	372117	1			T1	2172		T3	33		T12	63
all_values[3]	372117	1			T1	2172		T3	33		T12	63

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

740758

1

T1

4367

T3

62

T12

125

auto[1]

747710

1

T1

4321

T3

70

T12

127

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

892503

1

T1

7319

T3

116

T12

133

auto[1]

595965

1

T1

1369

T3

16

T12

119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	105644	1			T1	547		T3	6		T12	21
all_values[0]	auto[0]	auto[1]	80473	1			T1	530		T3	6		T12	19
all_values[0]	auto[1]	auto[0]	105964	1			T1	555		T3	11		T12	12
all_values[0]	auto[1]	auto[1]	80036	1			T1	540		T3	10		T12	11
all_values[1]	auto[0]	auto[0]	111311	1			T1	1042		T3	12		T12	18
all_values[1]	auto[0]	auto[1]	73562	1			T1	57		T12	17		T4	285
all_values[1]	auto[1]	auto[0]	113364	1			T1	1014		T3	21		T12	14
all_values[1]	auto[1]	auto[1]	73880	1			T1	59		T12	14		T4	291
all_values[2]	auto[0]	auto[0]	112750	1			T1	1085		T3	21		T12	11
all_values[2]	auto[0]	auto[1]	71982	1			T1	16		T12	11		T4	62
all_values[2]	auto[1]	auto[0]	114778	1			T1	1045		T3	12		T12	21
all_values[2]	auto[1]	auto[1]	72607	1			T1	26		T12	20		T4	63
all_values[3]	auto[0]	auto[0]	113617	1			T1	1022		T3	17		T12	15
all_values[3]	auto[0]	auto[1]	71419	1			T1	68		T12	13		T4	61
all_values[3]	auto[1]	auto[0]	115075	1			T1	1009		T3	16		T12	21
all_values[3]	auto[1]	auto[1]	72006	1			T1	73		T12	14		T6	12