Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	372117	1			T1	2172		T3	33		T12	63
all_pins[1]	372117	1			T1	2172		T3	33		T12	63
all_pins[2]	372117	1			T1	2172		T3	33		T12	63
all_pins[3]	372117	1			T1	2172		T3	33		T12	63

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1189939	1			T1	7990		T3	122		T12	193
values[0x1]	298529	1			T1	698		T3	10		T12	59
transitions[0x0=>0x1]	199164	1			T1	651		T3	10		T12	37
transitions[0x1=>0x0]	199432	1			T1	651		T3	10		T12	37

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	292081	1			T1	1632		T3	23		T12	52
all_pins[0]	values[0x1]	80036	1			T1	540		T3	10		T12	11
all_pins[0]	transitions[0x0=>0x1]	79297	1			T1	540		T3	10		T12	11
all_pins[0]	transitions[0x1=>0x0]	71535	1			T1	73		T12	14		T6	12
all_pins[1]	values[0x0]	298237	1			T1	2113		T3	33		T12	49
all_pins[1]	values[0x1]	73880	1			T1	59		T12	14		T4	291
all_pins[1]	transitions[0x0=>0x1]	40642	1			T1	35		T12	10		T4	141
all_pins[1]	transitions[0x1=>0x0]	46798	1			T1	516		T3	10		T12	7
all_pins[2]	values[0x0]	299510	1			T1	2146		T3	33		T12	43
all_pins[2]	values[0x1]	72607	1			T1	26		T12	20		T4	63
all_pins[2]	transitions[0x0=>0x1]	39892	1			T1	13		T12	10		T4	30
all_pins[2]	transitions[0x1=>0x0]	41165	1			T1	46		T12	4		T4	258
all_pins[3]	values[0x0]	300111	1			T1	2099		T3	33		T12	49
all_pins[3]	values[0x1]	72006	1			T1	73		T12	14		T6	12
all_pins[3]	transitions[0x0=>0x1]	39333	1			T1	63		T12	6		T6	12
all_pins[3]	transitions[0x1=>0x0]	39934	1			T1	16		T12	12		T4	36