Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89262	1			T4	210		T5	47		T7	1199
accum_cnt_1000	247903	1			T1	85		T4	239		T14	22
accum_cnt_100	28968	1			T1	24		T3	7		T12	17
accum_cnt_50	64516	1			T1	80		T3	14		T12	35
accum_cnt_10	200021	1			T1	71		T3	1		T12	39
accum_cnt_0	427102	1			T1	5840		T3	66		T12	33

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	274823	1			T1	1525		T3	22		T12	31
class_index[0x1]	274823	1			T1	1525		T3	22		T12	31
class_index[0x2]	274823	1			T1	1525		T3	22		T12	31
class_index[0x3]	274823	1			T1	1525		T3	22		T12	31

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26929	1			T4	210		T5	47		T17	272
class_index[0x0]	accum_cnt_1000	67205	1			T1	85		T4	211		T13	52
class_index[0x0]	accum_cnt_100	7826	1			T1	24		T3	7		T12	5
class_index[0x0]	accum_cnt_50	16179	1			T1	22		T3	14		T12	21
class_index[0x0]	accum_cnt_10	53433	1			T1	17		T3	1		T12	5
class_index[0x0]	accum_cnt_0	87687	1			T1	1377		T6	18		T4	31
class_index[0x1]	accum_cnt_2000	20125	1			T7	600		T8	284		T47	464
class_index[0x1]	accum_cnt_1000	63411	1			T13	51		T5	3		T7	557
class_index[0x1]	accum_cnt_100	7030	1			T4	7		T13	15		T5	16
class_index[0x1]	accum_cnt_50	17252	1			T4	36		T13	14		T5	27
class_index[0x1]	accum_cnt_10	49877	1			T4	38		T13	7		T5	592
class_index[0x1]	accum_cnt_0	105081	1			T1	1525		T3	22		T12	31
class_index[0x2]	accum_cnt_2000	19757	1			T7	599		T23	608		T80	573
class_index[0x2]	accum_cnt_1000	54331	1			T4	28		T14	22		T13	50
class_index[0x2]	accum_cnt_100	5763	1			T12	12		T4	30		T13	19
class_index[0x2]	accum_cnt_50	18197	1			T1	5		T12	14		T4	45
class_index[0x2]	accum_cnt_10	48874	1			T1	12		T12	5		T4	30
class_index[0x2]	accum_cnt_0	122097	1			T1	1508		T3	22		T6	18
class_index[0x3]	accum_cnt_2000	22451	1			T19	98		T23	640		T80	228
class_index[0x3]	accum_cnt_1000	62956	1			T13	33		T5	55		T46	1
class_index[0x3]	accum_cnt_100	8349	1			T13	23		T5	17		T46	16
class_index[0x3]	accum_cnt_50	12888	1			T1	53		T4	18		T14	15
class_index[0x3]	accum_cnt_10	47837	1			T1	42		T12	29		T6	18
class_index[0x3]	accum_cnt_0	112237	1			T1	1430		T3	22		T12	2