Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2041	1			T4	355		T7	170		T8	3
alert[0x1]	14747	1			T4	412		T69	1		T88	60
alert[0x2]	2864	1			T4	624		T7	15		T8	194
alert[0x3]	5497	1			T7	90		T16	174		T317	1
alert[0x4]	10375	1			T6	1		T8	117		T33	31
alert[0x5]	4929	1			T16	7		T146	1		T317	1
alert[0x6]	8800	1			T4	53		T7	16		T72	13
alert[0x7]	5213	1			T7	45		T33	37		T72	151
alert[0x8]	4858	1			T5	5		T7	189		T114	8
alert[0x9]	8964	1			T4	154		T5	4		T8	6
alert[0xa]	4186	1			T16	44		T52	16		T121	10
alert[0xb]	6468	1			T6	2		T7	51		T72	54
alert[0xc]	3004	1			T5	4		T7	65		T121	44
alert[0xd]	10633	1			T4	23		T5	9		T7	756
alert[0xe]	5321	1			T4	97		T86	2503		T226	1
alert[0xf]	8334	1			T1	10		T4	37		T7	615
alert[0x10]	8476	1			T4	51		T7	41		T33	2142
alert[0x11]	12439	1			T7	90		T31	1		T33	7
alert[0x12]	8799	1			T7	2690		T33	969		T53	302
alert[0x13]	4959	1			T8	52		T80	1		T69	1
alert[0x14]	5545	1			T6	1		T7	38		T33	65
alert[0x15]	4080	1			T7	623		T8	36		T73	1
alert[0x16]	5792	1			T8	11		T16	561		T88	6
alert[0x17]	6158	1			T4	24		T80	7		T16	25
alert[0x18]	6675	1			T7	387		T69	1		T72	266
alert[0x19]	7060	1			T8	20		T20	1		T16	2969
alert[0x1a]	6078	1			T4	226		T5	3		T7	19
alert[0x1b]	3357	1			T1	2		T5	1		T7	531
alert[0x1c]	10980	1			T21	1		T72	8		T87	2
alert[0x1d]	6228	1			T69	1		T30	2		T88	18
alert[0x1e]	6362	1			T5	4		T33	20		T72	8
alert[0x1f]	5017	1			T6	1		T16	3121		T111	3
alert[0x20]	10017	1			T4	1302		T33	57		T87	1
alert[0x21]	8397	1			T33	3		T73	1		T114	5
alert[0x22]	9816	1			T6	1		T31	1		T30	1
alert[0x23]	5758	1			T5	5		T7	2988		T33	24
alert[0x24]	3186	1			T5	1		T69	1		T88	2
alert[0x25]	2941	1			T7	43		T20	1		T33	26
alert[0x26]	4846	1			T4	30		T16	64		T87	1
alert[0x27]	8886	1			T8	1		T31	1		T33	46
alert[0x28]	5667	1			T4	106		T69	2		T73	1
alert[0x29]	2468	1			T20	1		T31	1		T33	3
alert[0x2a]	4693	1			T7	152		T33	161		T72	2
alert[0x2b]	2454	1			T72	4		T146	1		T52	23
alert[0x2c]	8168	1			T6	1		T4	2		T72	225
alert[0x2d]	6480	1			T4	15		T31	1		T33	132
alert[0x2e]	3443	1			T4	169		T69	1		T72	402
alert[0x2f]	9920	1			T72	65		T114	3		T318	1
alert[0x30]	7063	1			T7	41		T33	1426		T16	46
alert[0x31]	9582	1			T7	120		T33	138		T16	440
alert[0x32]	4400	1			T7	323		T8	100		T33	241
alert[0x33]	8379	1			T72	15		T16	555		T87	4
alert[0x34]	4950	1			T7	157		T33	12		T69	1
alert[0x35]	6067	1			T6	1		T7	237		T52	79
alert[0x36]	5094	1			T4	8		T7	33		T8	1
alert[0x37]	2606	1			T4	263		T7	76		T33	50
alert[0x38]	3093	1			T4	168		T7	15		T33	75
alert[0x39]	9026	1			T6	1		T7	261		T80	1
alert[0x3a]	9727	1			T4	338		T7	2010		T121	1176
alert[0x3b]	5664	1			T6	1		T69	1		T16	3327
alert[0x3c]	2895	1			T8	7		T69	1		T52	5
alert[0x3d]	6543	1			T114	4		T52	224		T121	5
alert[0x3e]	3377	1			T4	719		T69	1		T72	14
alert[0x3f]	12478	1			T4	916		T80	2		T73	1
alert[0x40]	12536	1			T8	3		T20	1		T33	145

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	160881	1			T1	12		T4	6092		T5	10
class_i[0x1]	91402	1			T5	6		T20	4		T80	9
class_i[0x2]	70473	1			T5	20		T8	478		T31	2
class_i[0x3]	102103	1			T6	10		T80	5		T69	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

424201

1

T1

12

T4

6092

T5

36

alert_ping_fail

658

1

T6

10

T20

4

T21

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2033	1			T4	355		T7	170		T8	3
alert_integrity_fail	alert[0x1]	14738	1			T4	412		T88	60		T86	245
alert_integrity_fail	alert[0x2]	2851	1			T4	624		T7	15		T8	194
alert_integrity_fail	alert[0x3]	5486	1			T7	90		T16	174		T52	170
alert_integrity_fail	alert[0x4]	10366	1			T8	117		T33	31		T72	7
alert_integrity_fail	alert[0x5]	4914	1			T16	7		T88	3		T86	11
alert_integrity_fail	alert[0x6]	8786	1			T4	53		T7	16		T72	13
alert_integrity_fail	alert[0x7]	5203	1			T7	45		T33	37		T72	151
alert_integrity_fail	alert[0x8]	4844	1			T5	5		T7	189		T114	8
alert_integrity_fail	alert[0x9]	8952	1			T4	154		T5	4		T8	6
alert_integrity_fail	alert[0xa]	4180	1			T16	44		T52	16		T121	10
alert_integrity_fail	alert[0xb]	6462	1			T7	51		T72	54		T16	16
alert_integrity_fail	alert[0xc]	2995	1			T5	4		T7	65		T121	44
alert_integrity_fail	alert[0xd]	10626	1			T4	23		T5	9		T7	756
alert_integrity_fail	alert[0xe]	5316	1			T4	97		T86	2503		T115	725
alert_integrity_fail	alert[0xf]	8325	1			T1	10		T4	37		T7	615
alert_integrity_fail	alert[0x10]	8466	1			T4	51		T7	41		T33	2142
alert_integrity_fail	alert[0x11]	12427	1			T7	90		T33	7		T52	13
alert_integrity_fail	alert[0x12]	8792	1			T7	2690		T33	969		T53	302
alert_integrity_fail	alert[0x13]	4946	1			T8	52		T80	1		T52	56
alert_integrity_fail	alert[0x14]	5533	1			T7	38		T33	65		T16	14
alert_integrity_fail	alert[0x15]	4066	1			T7	623		T8	36		T88	27
alert_integrity_fail	alert[0x16]	5777	1			T8	11		T16	561		T88	6
alert_integrity_fail	alert[0x17]	6141	1			T4	24		T80	7		T16	25
alert_integrity_fail	alert[0x18]	6665	1			T7	387		T72	266		T16	33
alert_integrity_fail	alert[0x19]	7048	1			T8	20		T16	2969		T52	308
alert_integrity_fail	alert[0x1a]	6072	1			T4	226		T5	3		T7	19
alert_integrity_fail	alert[0x1b]	3348	1			T1	2		T5	1		T7	531
alert_integrity_fail	alert[0x1c]	10968	1			T72	8		T87	2		T52	1158
alert_integrity_fail	alert[0x1d]	6212	1			T30	2		T88	18		T121	1
alert_integrity_fail	alert[0x1e]	6347	1			T5	4		T33	20		T72	8
alert_integrity_fail	alert[0x1f]	5005	1			T16	3121		T121	14		T56	82
alert_integrity_fail	alert[0x20]	10005	1			T4	1302		T33	57		T87	1
alert_integrity_fail	alert[0x21]	8391	1			T33	3		T114	5		T53	63
alert_integrity_fail	alert[0x22]	9806	1			T30	1		T16	410		T114	1
alert_integrity_fail	alert[0x23]	5752	1			T5	5		T7	2988		T33	24
alert_integrity_fail	alert[0x24]	3173	1			T5	1		T88	2		T121	453
alert_integrity_fail	alert[0x25]	2936	1			T7	43		T33	26		T52	181
alert_integrity_fail	alert[0x26]	4840	1			T4	30		T16	64		T87	1
alert_integrity_fail	alert[0x27]	8872	1			T8	1		T33	46		T72	189
alert_integrity_fail	alert[0x28]	5655	1			T4	106		T54	9		T56	664
alert_integrity_fail	alert[0x29]	2456	1			T33	3		T16	20		T52	21
alert_integrity_fail	alert[0x2a]	4679	1			T7	152		T33	161		T72	2
alert_integrity_fail	alert[0x2b]	2438	1			T72	4		T52	23		T86	180
alert_integrity_fail	alert[0x2c]	8150	1			T4	2		T72	225		T16	549
alert_integrity_fail	alert[0x2d]	6472	1			T4	15		T33	132		T72	1
alert_integrity_fail	alert[0x2e]	3433	1			T4	169		T72	402		T52	35
alert_integrity_fail	alert[0x2f]	9910	1			T72	65		T114	3		T52	19
alert_integrity_fail	alert[0x30]	7058	1			T7	41		T33	1426		T16	46
alert_integrity_fail	alert[0x31]	9577	1			T7	120		T33	138		T16	440
alert_integrity_fail	alert[0x32]	4391	1			T7	323		T8	100		T33	241
alert_integrity_fail	alert[0x33]	8369	1			T72	15		T16	555		T87	4
alert_integrity_fail	alert[0x34]	4938	1			T7	157		T33	12		T16	663
alert_integrity_fail	alert[0x35]	6057	1			T7	237		T52	79		T56	3
alert_integrity_fail	alert[0x36]	5081	1			T4	8		T7	33		T8	1
alert_integrity_fail	alert[0x37]	2603	1			T4	263		T7	76		T33	50
alert_integrity_fail	alert[0x38]	3084	1			T4	168		T7	15		T33	75
alert_integrity_fail	alert[0x39]	9018	1			T7	261		T80	1		T121	46
alert_integrity_fail	alert[0x3a]	9721	1			T4	338		T7	2010		T121	1176
alert_integrity_fail	alert[0x3b]	5654	1			T16	3327		T86	249		T55	1
alert_integrity_fail	alert[0x3c]	2883	1			T8	7		T52	5		T121	30
alert_integrity_fail	alert[0x3d]	6535	1			T114	4		T52	224		T121	5
alert_integrity_fail	alert[0x3e]	3368	1			T4	719		T72	14		T114	47
alert_integrity_fail	alert[0x3f]	12475	1			T4	916		T80	2		T52	2104
alert_integrity_fail	alert[0x40]	12531	1			T8	3		T33	145		T114	17
alert_ping_fail	alert[0x0]	8	1			T69	1		T319	1		T320	1
alert_ping_fail	alert[0x1]	9	1			T69	1		T321	1		T320	1
alert_ping_fail	alert[0x2]	13	1			T31	1		T322	1		T321	1
alert_ping_fail	alert[0x3]	11	1			T317	1		T323	1		T324	1
alert_ping_fail	alert[0x4]	9	1			T6	1		T317	1		T226	1
alert_ping_fail	alert[0x5]	15	1			T146	1		T317	1		T226	1
alert_ping_fail	alert[0x6]	14	1			T105	1		T323	1		T298	1
alert_ping_fail	alert[0x7]	10	1			T325	1		T324	1		T320	1
alert_ping_fail	alert[0x8]	14	1			T36	5		T298	1		T324	1
alert_ping_fail	alert[0x9]	12	1			T325	2		T319	1		T261	1
alert_ping_fail	alert[0xa]	6	1			T316	1		T226	1		T326	1
alert_ping_fail	alert[0xb]	6	1			T6	2		T327	1		T328	1
alert_ping_fail	alert[0xc]	9	1			T319	1		T105	1		T323	1
alert_ping_fail	alert[0xd]	7	1			T226	1		T329	1		T330	1
alert_ping_fail	alert[0xe]	5	1			T226	1		T105	1		T323	1
alert_ping_fail	alert[0xf]	9	1			T317	1		T325	1		T326	1
alert_ping_fail	alert[0x10]	10	1			T324	1		T320	1		T327	2
alert_ping_fail	alert[0x11]	12	1			T31	1		T105	1		T323	1
alert_ping_fail	alert[0x12]	7	1			T319	1		T105	1		T261	1
alert_ping_fail	alert[0x13]	13	1			T69	1		T104	2		T321	1
alert_ping_fail	alert[0x14]	12	1			T6	1		T105	1		T329	1
alert_ping_fail	alert[0x15]	14	1			T73	1		T226	1		T325	1
alert_ping_fail	alert[0x16]	15	1			T316	1		T321	2		T105	1
alert_ping_fail	alert[0x17]	17	1			T321	1		T325	1		T261	1
alert_ping_fail	alert[0x18]	10	1			T69	1		T321	1		T226	1
alert_ping_fail	alert[0x19]	12	1			T20	1		T329	1		T261	1
alert_ping_fail	alert[0x1a]	6	1			T105	1		T331	1		T332	1
alert_ping_fail	alert[0x1b]	9	1			T323	1		T324	2		T320	1
alert_ping_fail	alert[0x1c]	12	1			T21	1		T318	1		T211	1
alert_ping_fail	alert[0x1d]	16	1			T69	1		T318	1		T321	2
alert_ping_fail	alert[0x1e]	15	1			T321	2		T329	1		T269	2
alert_ping_fail	alert[0x1f]	12	1			T6	1		T111	3		T261	1
alert_ping_fail	alert[0x20]	12	1			T329	2		T269	1		T326	1
alert_ping_fail	alert[0x21]	6	1			T73	1		T320	1		T331	1
alert_ping_fail	alert[0x22]	10	1			T6	1		T31	1		T329	1
alert_ping_fail	alert[0x23]	6	1			T261	1		T269	1		T332	1
alert_ping_fail	alert[0x24]	13	1			T69	1		T323	1		T269	2
alert_ping_fail	alert[0x25]	5	1			T20	1		T69	1		T329	1
alert_ping_fail	alert[0x26]	6	1			T324	1		T333	2		T334	1
alert_ping_fail	alert[0x27]	14	1			T31	1		T330	1		T324	1
alert_ping_fail	alert[0x28]	12	1			T69	2		T73	1		T320	1
alert_ping_fail	alert[0x29]	12	1			T20	1		T31	1		T69	1
alert_ping_fail	alert[0x2a]	14	1			T146	1		T325	1		T319	1
alert_ping_fail	alert[0x2b]	16	1			T146	1		T321	3		T326	1
alert_ping_fail	alert[0x2c]	18	1			T6	1		T73	1		T226	1
alert_ping_fail	alert[0x2d]	8	1			T31	1		T104	1		T321	1
alert_ping_fail	alert[0x2e]	10	1			T69	1		T335	1		T336	1
alert_ping_fail	alert[0x2f]	10	1			T318	1		T322	1		T226	1
alert_ping_fail	alert[0x30]	5	1			T330	1		T324	2		T269	1
alert_ping_fail	alert[0x31]	5	1			T330	1		T269	1		T333	1
alert_ping_fail	alert[0x32]	9	1			T323	1		T324	2		T327	1
alert_ping_fail	alert[0x33]	10	1			T322	1		T226	1		T105	1
alert_ping_fail	alert[0x34]	12	1			T69	1		T321	1		T324	3
alert_ping_fail	alert[0x35]	10	1			T6	1		T321	1		T331	1
alert_ping_fail	alert[0x36]	13	1			T319	1		T105	1		T323	1
alert_ping_fail	alert[0x37]	3	1			T226	1		T320	1		T337	1
alert_ping_fail	alert[0x38]	9	1			T211	1		T327	1		T338	1
alert_ping_fail	alert[0x39]	8	1			T6	1		T31	1		T326	1
alert_ping_fail	alert[0x3a]	6	1			T320	1		T332	1		T334	1
alert_ping_fail	alert[0x3b]	10	1			T6	1		T69	1		T323	2
alert_ping_fail	alert[0x3c]	12	1			T69	1		T321	1		T105	2
alert_ping_fail	alert[0x3d]	8	1			T226	1		T330	1		T336	1
alert_ping_fail	alert[0x3e]	9	1			T69	1		T226	1		T105	1
alert_ping_fail	alert[0x3f]	3	1			T73	1		T326	1		T339	1
alert_ping_fail	alert[0x40]	5	1			T20	1		T325	1		T340	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	160690	1			T1	12		T4	6092		T5	10
alert_integrity_fail	class_i[0x1]	91248	1			T5	6		T80	9		T33	7712
alert_integrity_fail	class_i[0x2]	70316	1			T5	20		T8	478		T16	14974
alert_integrity_fail	class_i[0x3]	101947	1			T80	5		T72	657		T341	10
alert_ping_fail	class_i[0x0]	191	1			T69	13		T322	1		T321	18
alert_ping_fail	class_i[0x1]	154	1			T20	4		T21	1		T31	5
alert_ping_fail	class_i[0x2]	157	1			T31	2		T69	1		T73	5
alert_ping_fail	class_i[0x3]	156	1			T6	10		T69	1		T317	4