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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.63 99.99 98.74 92.70 100.00 100.00 99.38 99.64


Total test records in report: 833
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T775 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1883767538 May 16 02:40:17 PM PDT 24 May 16 02:40:27 PM PDT 24 68276726 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1451749509 May 16 02:39:55 PM PDT 24 May 16 02:40:25 PM PDT 24 1383190338 ps
T777 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.187087032 May 16 02:40:31 PM PDT 24 May 16 02:40:38 PM PDT 24 11157302 ps
T167 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3678418275 May 16 02:40:18 PM PDT 24 May 16 02:42:07 PM PDT 24 904952142 ps
T778 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2020152564 May 16 02:40:24 PM PDT 24 May 16 02:40:38 PM PDT 24 204897323 ps
T179 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1209077832 May 16 02:40:27 PM PDT 24 May 16 02:48:57 PM PDT 24 7302170173 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4185043221 May 16 02:40:06 PM PDT 24 May 16 02:44:04 PM PDT 24 15492076692 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3679544943 May 16 02:40:23 PM PDT 24 May 16 02:40:36 PM PDT 24 186338623 ps
T781 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1529201250 May 16 02:39:56 PM PDT 24 May 16 02:40:12 PM PDT 24 130481253 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1339462346 May 16 02:40:04 PM PDT 24 May 16 02:40:10 PM PDT 24 11276794 ps
T202 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3693587348 May 16 02:40:25 PM PDT 24 May 16 02:40:32 PM PDT 24 50645338 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.836984643 May 16 02:40:16 PM PDT 24 May 16 02:40:40 PM PDT 24 192388112 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.226991136 May 16 02:40:04 PM PDT 24 May 16 02:40:16 PM PDT 24 1086968672 ps
T174 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3052227816 May 16 02:40:03 PM PDT 24 May 16 02:46:35 PM PDT 24 4382242276 ps
T176 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4236655865 May 16 02:40:05 PM PDT 24 May 16 02:43:56 PM PDT 24 2055287531 ps
T178 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1387014846 May 16 02:40:05 PM PDT 24 May 16 03:00:01 PM PDT 24 60285781419 ps
T785 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1153077466 May 16 02:40:34 PM PDT 24 May 16 02:40:40 PM PDT 24 74800889 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1212854043 May 16 02:39:55 PM PDT 24 May 16 02:40:10 PM PDT 24 61361428 ps
T181 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.41517602 May 16 02:40:24 PM PDT 24 May 16 02:49:15 PM PDT 24 26251592917 ps
T177 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3779466666 May 16 02:40:05 PM PDT 24 May 16 02:48:49 PM PDT 24 24661262521 ps
T173 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1870260782 May 16 02:40:15 PM PDT 24 May 16 02:43:45 PM PDT 24 5270109664 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.676704453 May 16 02:40:23 PM PDT 24 May 16 02:40:37 PM PDT 24 197564258 ps
T788 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1233220017 May 16 02:40:32 PM PDT 24 May 16 02:40:58 PM PDT 24 941768561 ps
T789 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2839342477 May 16 02:40:33 PM PDT 24 May 16 02:40:39 PM PDT 24 6860352 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3094925384 May 16 02:40:24 PM PDT 24 May 16 02:40:39 PM PDT 24 121941464 ps
T184 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.993236800 May 16 02:40:24 PM PDT 24 May 16 02:43:56 PM PDT 24 6173809506 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4140913506 May 16 02:40:10 PM PDT 24 May 16 02:40:35 PM PDT 24 298047051 ps
T183 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3152609327 May 16 02:40:04 PM PDT 24 May 16 02:57:31 PM PDT 24 12833901846 ps
T169 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1209614295 May 16 02:39:55 PM PDT 24 May 16 02:48:47 PM PDT 24 32938317685 ps
T792 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3033532932 May 16 02:40:33 PM PDT 24 May 16 02:40:43 PM PDT 24 66110111 ps
T194 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.429830883 May 16 02:40:05 PM PDT 24 May 16 02:41:02 PM PDT 24 408701324 ps
T793 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2511441958 May 16 02:40:33 PM PDT 24 May 16 02:40:46 PM PDT 24 67692626 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.924109807 May 16 02:40:18 PM PDT 24 May 16 02:40:23 PM PDT 24 19485206 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4230560808 May 16 02:40:23 PM PDT 24 May 16 02:40:33 PM PDT 24 147531516 ps
T796 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3762926796 May 16 02:40:32 PM PDT 24 May 16 02:40:38 PM PDT 24 24551344 ps
T196 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3158558284 May 16 02:40:14 PM PDT 24 May 16 02:40:22 PM PDT 24 155908949 ps
T797 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.87814188 May 16 02:40:15 PM PDT 24 May 16 02:40:28 PM PDT 24 178666455 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2380305714 May 16 02:39:56 PM PDT 24 May 16 02:40:08 PM PDT 24 287831167 ps
T799 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1540284088 May 16 02:40:37 PM PDT 24 May 16 02:40:42 PM PDT 24 66248057 ps
T800 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1143547952 May 16 02:39:53 PM PDT 24 May 16 02:40:03 PM PDT 24 45428431 ps
T801 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1346436093 May 16 02:40:36 PM PDT 24 May 16 02:40:51 PM PDT 24 277240847 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3295813591 May 16 02:40:24 PM PDT 24 May 16 02:40:44 PM PDT 24 799838666 ps
T803 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2177729124 May 16 02:40:25 PM PDT 24 May 16 02:40:31 PM PDT 24 7189020 ps
T804 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.912894818 May 16 02:40:33 PM PDT 24 May 16 02:40:39 PM PDT 24 10010045 ps
T805 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3658861465 May 16 02:40:10 PM PDT 24 May 16 02:40:24 PM PDT 24 167109809 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.529713506 May 16 02:40:15 PM PDT 24 May 16 02:40:40 PM PDT 24 1170483577 ps
T807 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.704114651 May 16 02:40:31 PM PDT 24 May 16 02:40:38 PM PDT 24 9714822 ps
T808 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.614271090 May 16 02:40:31 PM PDT 24 May 16 02:41:24 PM PDT 24 1368834381 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3390491008 May 16 02:39:53 PM PDT 24 May 16 02:40:03 PM PDT 24 63165667 ps
T195 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1714273964 May 16 02:39:56 PM PDT 24 May 16 02:41:10 PM PDT 24 3674782319 ps
T810 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3086326416 May 16 02:40:37 PM PDT 24 May 16 02:40:42 PM PDT 24 20468966 ps
T170 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3906590890 May 16 02:40:24 PM PDT 24 May 16 02:46:08 PM PDT 24 28777260753 ps
T171 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.727532077 May 16 02:40:22 PM PDT 24 May 16 02:43:00 PM PDT 24 1675884185 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1286620774 May 16 02:40:40 PM PDT 24 May 16 02:40:44 PM PDT 24 12969135 ps
T182 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3254111746 May 16 02:40:32 PM PDT 24 May 16 02:46:09 PM PDT 24 3879690605 ps
T812 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1408150538 May 16 02:40:14 PM PDT 24 May 16 02:40:20 PM PDT 24 17194714 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.885443842 May 16 02:39:57 PM PDT 24 May 16 02:40:08 PM PDT 24 54889479 ps
T201 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2260930798 May 16 02:39:57 PM PDT 24 May 16 02:40:50 PM PDT 24 365007324 ps
T814 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3467972053 May 16 02:40:31 PM PDT 24 May 16 02:40:38 PM PDT 24 8470289 ps
T205 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1876653220 May 16 02:40:25 PM PDT 24 May 16 02:40:33 PM PDT 24 43952679 ps
T815 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1911719978 May 16 02:40:32 PM PDT 24 May 16 02:40:38 PM PDT 24 19639514 ps
T816 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2906554281 May 16 02:40:15 PM PDT 24 May 16 02:40:44 PM PDT 24 1124220250 ps
T817 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2159639740 May 16 02:40:14 PM PDT 24 May 16 02:40:39 PM PDT 24 731938555 ps
T818 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2372188540 May 16 02:40:33 PM PDT 24 May 16 02:40:39 PM PDT 24 6854525 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.214716397 May 16 02:40:15 PM PDT 24 May 16 02:40:25 PM PDT 24 82630792 ps
T820 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.992478269 May 16 02:39:59 PM PDT 24 May 16 02:40:11 PM PDT 24 59822138 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.838420724 May 16 02:40:13 PM PDT 24 May 16 02:56:20 PM PDT 24 66042092664 ps
T180 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2170822874 May 16 02:39:55 PM PDT 24 May 16 02:45:23 PM PDT 24 4871364707 ps
T822 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2800023941 May 16 02:40:12 PM PDT 24 May 16 02:40:21 PM PDT 24 224000414 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1753283765 May 16 02:40:16 PM PDT 24 May 16 02:51:22 PM PDT 24 4832354313 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.781242189 May 16 02:40:23 PM PDT 24 May 16 02:40:37 PM PDT 24 95529158 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2319919402 May 16 02:40:35 PM PDT 24 May 16 02:42:03 PM PDT 24 8893583738 ps
T825 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4046278260 May 16 02:40:31 PM PDT 24 May 16 02:40:37 PM PDT 24 6125193 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.316069052 May 16 02:39:57 PM PDT 24 May 16 02:40:05 PM PDT 24 19131728 ps
T185 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2884621904 May 16 02:40:14 PM PDT 24 May 16 02:46:20 PM PDT 24 5644968761 ps
T827 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1737877001 May 16 02:40:34 PM PDT 24 May 16 02:40:40 PM PDT 24 8699165 ps
T186 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2242392782 May 16 02:39:57 PM PDT 24 May 16 02:41:41 PM PDT 24 828867307 ps
T828 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3959431197 May 16 02:40:19 PM PDT 24 May 16 02:40:25 PM PDT 24 9418817 ps
T829 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.626818305 May 16 02:39:55 PM PDT 24 May 16 02:41:50 PM PDT 24 3405995002 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2093890206 May 16 02:40:06 PM PDT 24 May 16 02:40:20 PM PDT 24 2107431569 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3115653122 May 16 02:40:07 PM PDT 24 May 16 02:40:25 PM PDT 24 357456472 ps
T832 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3470850845 May 16 02:40:32 PM PDT 24 May 16 02:40:46 PM PDT 24 63048930 ps
T833 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2927586877 May 16 02:40:23 PM PDT 24 May 16 02:40:32 PM PDT 24 149843106 ps

Test location /workspace/coverage/default/31.alert_handler_stress_all.53563522
Short name T4
Test name
Test status
Simulation time 68847722085 ps
CPU time 3880.93 seconds
Started May 16 02:18:42 PM PDT 24
Finished May 16 03:23:25 PM PDT 24
Peak memory 305584 kb
Host smart-022ed05f-67fb-4677-97ae-605451874bba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53563522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_hand
ler_stress_all.53563522
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.4260341230
Short name T8
Test name
Test status
Simulation time 107944745047 ps
CPU time 4356.27 seconds
Started May 16 02:14:37 PM PDT 24
Finished May 16 03:27:15 PM PDT 24
Peak memory 305608 kb
Host smart-198f8cad-c291-4cae-b534-965228f476e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260341230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.4260341230
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.555124513
Short name T188
Test name
Test status
Simulation time 3612802550 ps
CPU time 34.33 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:41:10 PM PDT 24
Peak memory 240116 kb
Host smart-d62f2477-4535-4779-a1c9-b63421de315b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=555124513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.555124513
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4284761918
Short name T10
Test name
Test status
Simulation time 434021179 ps
CPU time 22.42 seconds
Started May 16 02:14:59 PM PDT 24
Finished May 16 02:15:23 PM PDT 24
Peak memory 277600 kb
Host smart-931d39b4-d55f-420e-8463-b0f5dca360d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4284761918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4284761918
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2014859776
Short name T120
Test name
Test status
Simulation time 266915860111 ps
CPU time 9631.44 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 04:57:40 PM PDT 24
Peak memory 394232 kb
Host smart-4dc8001c-06bd-48cf-a2c9-854f12747551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014859776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2014859776
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1660022041
Short name T16
Test name
Test status
Simulation time 180063624399 ps
CPU time 2676.87 seconds
Started May 16 02:15:09 PM PDT 24
Finished May 16 02:59:48 PM PDT 24
Peak memory 289440 kb
Host smart-2a760a6a-f20c-4be2-88c4-0855e127a6c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660022041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1660022041
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3642633603
Short name T104
Test name
Test status
Simulation time 39669660624 ps
CPU time 2164.75 seconds
Started May 16 02:15:26 PM PDT 24
Finished May 16 02:51:33 PM PDT 24
Peak memory 273416 kb
Host smart-243c472c-6789-41d9-b432-30bb75987072
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642633603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3642633603
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1017389931
Short name T33
Test name
Test status
Simulation time 11113292167 ps
CPU time 978.88 seconds
Started May 16 02:16:20 PM PDT 24
Finished May 16 02:32:43 PM PDT 24
Peak memory 273392 kb
Host smart-f097ef00-65c1-4d46-8ceb-3cf2a021f019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017389931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1017389931
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1099665982
Short name T149
Test name
Test status
Simulation time 6416281319 ps
CPU time 226.08 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:44:07 PM PDT 24
Peak memory 272852 kb
Host smart-bda63710-8ca3-403a-aa48-00add6d732cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1099665982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1099665982
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1754317912
Short name T30
Test name
Test status
Simulation time 33361951901 ps
CPU time 1936.25 seconds
Started May 16 02:18:40 PM PDT 24
Finished May 16 02:50:58 PM PDT 24
Peak memory 273328 kb
Host smart-55fa8ffa-e16f-449f-adbc-523df639d82d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754317912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1754317912
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3191334972
Short name T100
Test name
Test status
Simulation time 109863124808 ps
CPU time 3217.44 seconds
Started May 16 02:16:43 PM PDT 24
Finished May 16 03:10:22 PM PDT 24
Peak memory 297948 kb
Host smart-a6391202-072c-4d6e-ad68-f125471307bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191334972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3191334972
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1586683755
Short name T161
Test name
Test status
Simulation time 5519656417 ps
CPU time 681.37 seconds
Started May 16 02:40:21 PM PDT 24
Finished May 16 02:51:47 PM PDT 24
Peak memory 265028 kb
Host smart-52f14c3b-fff2-45aa-9ab6-b9d7d1d0fe10
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586683755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1586683755
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1010027775
Short name T18
Test name
Test status
Simulation time 4823632954 ps
CPU time 51.56 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 248796 kb
Host smart-d9cb0fa0-14d2-46d0-89cd-f00627c6c2a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1010027775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1010027775
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3541213801
Short name T126
Test name
Test status
Simulation time 8579352054 ps
CPU time 638.5 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:26:15 PM PDT 24
Peak memory 273380 kb
Host smart-fe6bf7cc-68e7-47c7-a7dd-f87e5ec00355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541213801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3541213801
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3685394038
Short name T153
Test name
Test status
Simulation time 17841193015 ps
CPU time 1292.25 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 03:02:00 PM PDT 24
Peak memory 265044 kb
Host smart-6f1e1406-fd30-465d-96c1-976c8a209f11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685394038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3685394038
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1146492032
Short name T133
Test name
Test status
Simulation time 110546650832 ps
CPU time 1861.34 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:50:32 PM PDT 24
Peak memory 273388 kb
Host smart-0da99882-60ec-4dc6-95f3-01fb1a6afb1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146492032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1146492032
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2928928794
Short name T159
Test name
Test status
Simulation time 70605566786 ps
CPU time 1248.71 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 03:01:26 PM PDT 24
Peak memory 264960 kb
Host smart-ce3e4da0-c778-4d71-9eee-1a4f5e8868d5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928928794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2928928794
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2884621904
Short name T185
Test name
Test status
Simulation time 5644968761 ps
CPU time 362.57 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:46:20 PM PDT 24
Peak memory 265044 kb
Host smart-d029eb61-0154-4f93-99fa-bd2fe974d0a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2884621904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2884621904
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.615705035
Short name T69
Test name
Test status
Simulation time 39808378181 ps
CPU time 400.72 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 02:24:07 PM PDT 24
Peak memory 247688 kb
Host smart-c14b7f5f-81d2-417e-afa6-588c25bd649c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615705035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.615705035
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3436710751
Short name T43
Test name
Test status
Simulation time 494654997796 ps
CPU time 3072.84 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 03:08:40 PM PDT 24
Peak memory 289160 kb
Host smart-97e591dd-33ad-4959-8048-ebbe0d5164db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436710751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3436710751
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3612904678
Short name T263
Test name
Test status
Simulation time 8116169 ps
CPU time 1.54 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236488 kb
Host smart-c9368fc9-dda2-4066-be66-28d9545d8e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612904678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3612904678
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3318683351
Short name T91
Test name
Test status
Simulation time 42431547603 ps
CPU time 2555.19 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 03:02:04 PM PDT 24
Peak memory 289160 kb
Host smart-b85c4159-63ba-4736-87ac-63dbd3e759b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318683351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3318683351
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1387014846
Short name T178
Test name
Test status
Simulation time 60285781419 ps
CPU time 1190.96 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 03:00:01 PM PDT 24
Peak memory 265012 kb
Host smart-daf9fdc0-a01b-4682-928d-9a31db077ad9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387014846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1387014846
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1904931453
Short name T5
Test name
Test status
Simulation time 54779933431 ps
CPU time 2720.52 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 03:04:26 PM PDT 24
Peak memory 306020 kb
Host smart-c80bc49d-8b0e-405c-9cf3-b0e0dd5f284a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904931453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1904931453
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1651956217
Short name T226
Test name
Test status
Simulation time 8810559204 ps
CPU time 349.23 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:24:33 PM PDT 24
Peak memory 248104 kb
Host smart-432f5506-c33d-40d9-a7f1-8f582e5e3f2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651956217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1651956217
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.570469069
Short name T165
Test name
Test status
Simulation time 19307722793 ps
CPU time 670.11 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:51:48 PM PDT 24
Peak memory 272920 kb
Host smart-b269e815-967e-4ca7-ba76-f06c675ba0e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570469069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.570469069
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1525418649
Short name T343
Test name
Test status
Simulation time 37212891934 ps
CPU time 2088.22 seconds
Started May 16 02:20:53 PM PDT 24
Finished May 16 02:55:43 PM PDT 24
Peak memory 288556 kb
Host smart-597da5ac-16a5-4d53-a1c5-20986fdf278c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525418649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1525418649
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2030354825
Short name T326
Test name
Test status
Simulation time 51279891223 ps
CPU time 427.3 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:26:12 PM PDT 24
Peak memory 248172 kb
Host smart-f56ecb3d-bbe9-4866-82b8-041e844f6ce2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030354825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2030354825
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3101136362
Short name T80
Test name
Test status
Simulation time 206699805778 ps
CPU time 2156.43 seconds
Started May 16 02:18:34 PM PDT 24
Finished May 16 02:54:33 PM PDT 24
Peak memory 289140 kb
Host smart-913e6fd9-071c-4399-9798-27f80dcf07b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101136362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3101136362
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.833132401
Short name T559
Test name
Test status
Simulation time 23954464145 ps
CPU time 484.36 seconds
Started May 16 02:15:23 PM PDT 24
Finished May 16 02:23:29 PM PDT 24
Peak memory 247192 kb
Host smart-d7664287-8daa-4767-9677-b8bac7e139c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833132401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.833132401
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.991144571
Short name T284
Test name
Test status
Simulation time 111374123776 ps
CPU time 3239.81 seconds
Started May 16 02:15:22 PM PDT 24
Finished May 16 03:09:24 PM PDT 24
Peak memory 289772 kb
Host smart-d5fbde66-2b6c-45dc-bf1b-c7c99eeb6667
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991144571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.991144571
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3678418275
Short name T167
Test name
Test status
Simulation time 904952142 ps
CPU time 105.2 seconds
Started May 16 02:40:18 PM PDT 24
Finished May 16 02:42:07 PM PDT 24
Peak memory 264956 kb
Host smart-940480d9-a06a-403c-966a-c6f1f61e904c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3678418275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3678418275
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3477539808
Short name T616
Test name
Test status
Simulation time 46443932666 ps
CPU time 2765.68 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 03:06:36 PM PDT 24
Peak memory 288508 kb
Host smart-2a8a8803-02c6-4955-9624-d6e13eea1502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477539808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3477539808
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2924504282
Short name T204
Test name
Test status
Simulation time 1765299013 ps
CPU time 75.82 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:41:51 PM PDT 24
Peak memory 245452 kb
Host smart-f28f8175-87fe-4b8d-bb5e-14a38724f83d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2924504282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2924504282
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1067195301
Short name T751
Test name
Test status
Simulation time 37803134 ps
CPU time 1.49 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236552 kb
Host smart-53dffa9d-87fe-48e4-82ae-d3859c05f529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1067195301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1067195301
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4243358410
Short name T94
Test name
Test status
Simulation time 167976696230 ps
CPU time 4287.82 seconds
Started May 16 02:19:36 PM PDT 24
Finished May 16 03:31:06 PM PDT 24
Peak memory 339028 kb
Host smart-3141b4fc-b464-427f-ac73-0ce6fc340a4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243358410 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4243358410
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2318266978
Short name T166
Test name
Test status
Simulation time 8465274519 ps
CPU time 318.85 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:45:39 PM PDT 24
Peak memory 272108 kb
Host smart-8844c5fa-03ba-472c-b582-5a25935ed4bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2318266978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2318266978
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1042206615
Short name T269
Test name
Test status
Simulation time 61901628850 ps
CPU time 626.52 seconds
Started May 16 02:16:07 PM PDT 24
Finished May 16 02:26:35 PM PDT 24
Peak memory 248220 kb
Host smart-c05225ff-08c6-46a4-9750-9d986b845d66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042206615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1042206615
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.727532077
Short name T171
Test name
Test status
Simulation time 1675884185 ps
CPU time 153.29 seconds
Started May 16 02:40:22 PM PDT 24
Finished May 16 02:43:00 PM PDT 24
Peak memory 255400 kb
Host smart-e5fec742-5adf-4134-bad0-068c7b5cd8da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=727532077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.727532077
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4214550326
Short name T138
Test name
Test status
Simulation time 206612831031 ps
CPU time 3214.79 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 03:12:31 PM PDT 24
Peak memory 302864 kb
Host smart-0e6566d2-f053-4a09-9cab-fcaf5e920536
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214550326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4214550326
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.71430266
Short name T355
Test name
Test status
Simulation time 90004052968 ps
CPU time 1362.36 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 02:41:48 PM PDT 24
Peak memory 266144 kb
Host smart-00df8dec-bbce-4575-8d29-6066d301ba1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71430266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.71430266
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2616336714
Short name T154
Test name
Test status
Simulation time 6585657735 ps
CPU time 252.22 seconds
Started May 16 02:39:54 PM PDT 24
Finished May 16 02:44:10 PM PDT 24
Peak memory 265148 kb
Host smart-4c9bae87-420f-42ad-b439-891f4c0d54b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2616336714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2616336714
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2813995163
Short name T281
Test name
Test status
Simulation time 204497140552 ps
CPU time 5221.02 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 03:47:32 PM PDT 24
Peak memory 305844 kb
Host smart-9e889477-cef1-458e-83c2-ea28fb8e4dd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813995163 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2813995163
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.4124019230
Short name T142
Test name
Test status
Simulation time 38314322169 ps
CPU time 3425.75 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 03:12:41 PM PDT 24
Peak memory 321768 kb
Host smart-923916e7-48dc-45d3-811a-dbd42af7eb8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124019230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4124019230
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2330147514
Short name T324
Test name
Test status
Simulation time 56526171686 ps
CPU time 638.05 seconds
Started May 16 02:16:33 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 247956 kb
Host smart-33f99f8d-ad5a-413b-b95c-aef284f73d24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330147514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2330147514
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1186932245
Short name T58
Test name
Test status
Simulation time 37123911125 ps
CPU time 2322.18 seconds
Started May 16 02:19:26 PM PDT 24
Finished May 16 02:58:09 PM PDT 24
Peak memory 281572 kb
Host smart-3fde76dd-978b-4430-9644-6fe6ce534ec2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186932245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1186932245
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2847863772
Short name T361
Test name
Test status
Simulation time 7835858 ps
CPU time 1.52 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:21 PM PDT 24
Peak memory 234604 kb
Host smart-0cd89efc-b791-425a-a1a9-b193e07b8fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847863772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2847863772
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1704883870
Short name T280
Test name
Test status
Simulation time 970552129 ps
CPU time 25.94 seconds
Started May 16 02:20:06 PM PDT 24
Finished May 16 02:20:34 PM PDT 24
Peak memory 248700 kb
Host smart-db70eae4-8c05-4dc4-817d-e2dbc23f9c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
83870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1704883870
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3250027087
Short name T19
Test name
Test status
Simulation time 25800772168 ps
CPU time 708.53 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 02:32:32 PM PDT 24
Peak memory 266260 kb
Host smart-ca187f0d-4d3f-4ca8-ae9f-86c7313e0a44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250027087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3250027087
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2700135075
Short name T62
Test name
Test status
Simulation time 67561675941 ps
CPU time 1895.93 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:46:01 PM PDT 24
Peak memory 297860 kb
Host smart-823ebc43-d32f-4936-a479-7fe276f00fd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700135075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2700135075
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1503068861
Short name T329
Test name
Test status
Simulation time 9123632963 ps
CPU time 372.94 seconds
Started May 16 02:16:19 PM PDT 24
Finished May 16 02:22:36 PM PDT 24
Peak memory 254192 kb
Host smart-101e5a9d-0ea1-48aa-a30c-dd125a323b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503068861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1503068861
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1515923608
Short name T265
Test name
Test status
Simulation time 151687109548 ps
CPU time 4266.77 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 03:29:31 PM PDT 24
Peak memory 317576 kb
Host smart-7b5850d8-1a4c-4a66-aa4d-9f54007d0893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515923608 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1515923608
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3254111746
Short name T182
Test name
Test status
Simulation time 3879690605 ps
CPU time 332.34 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:46:09 PM PDT 24
Peak memory 265012 kb
Host smart-73d0b9f7-7c66-4270-af2b-6c07f39bf309
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3254111746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3254111746
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3158558284
Short name T196
Test name
Test status
Simulation time 155908949 ps
CPU time 4.35 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:22 PM PDT 24
Peak memory 236520 kb
Host smart-3624b60a-04ff-4549-8956-91a17a14e84b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3158558284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3158558284
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2592054719
Short name T238
Test name
Test status
Simulation time 45423032 ps
CPU time 2.26 seconds
Started May 16 02:14:13 PM PDT 24
Finished May 16 02:14:16 PM PDT 24
Peak memory 248916 kb
Host smart-45aba93b-3576-44ee-b855-fcc145cbc0f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2592054719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2592054719
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2688266324
Short name T248
Test name
Test status
Simulation time 34266659 ps
CPU time 3.41 seconds
Started May 16 02:15:59 PM PDT 24
Finished May 16 02:16:04 PM PDT 24
Peak memory 248872 kb
Host smart-f547a0a9-7763-4f55-8642-c1e6e9097d62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2688266324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2688266324
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3225353886
Short name T231
Test name
Test status
Simulation time 36413050 ps
CPU time 2.27 seconds
Started May 16 02:16:09 PM PDT 24
Finished May 16 02:16:13 PM PDT 24
Peak memory 248896 kb
Host smart-558d93ce-915e-4d3f-b53c-57e703cec25c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3225353886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3225353886
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2431847579
Short name T2
Test name
Test status
Simulation time 123338938 ps
CPU time 3.37 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:17:23 PM PDT 24
Peak memory 248920 kb
Host smart-0345d1a7-0b8a-4902-882a-410f84cddfd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2431847579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2431847579
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.846306689
Short name T151
Test name
Test status
Simulation time 7775402754 ps
CPU time 617.47 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:50:21 PM PDT 24
Peak memory 268976 kb
Host smart-ca6c6659-2d26-4551-bc59-c071183670e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846306689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.846306689
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4289523261
Short name T331
Test name
Test status
Simulation time 21048487145 ps
CPU time 446.24 seconds
Started May 16 02:15:56 PM PDT 24
Finished May 16 02:23:24 PM PDT 24
Peak memory 247044 kb
Host smart-3e55a1f6-cc99-46ec-87e6-3fa90b64368c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289523261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4289523261
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3904879099
Short name T98
Test name
Test status
Simulation time 131555388352 ps
CPU time 1460.07 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:40:54 PM PDT 24
Peak memory 288964 kb
Host smart-52d98889-0bc3-4abc-93c2-0a935939552a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904879099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3904879099
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1243332192
Short name T327
Test name
Test status
Simulation time 24682075377 ps
CPU time 526.72 seconds
Started May 16 02:16:54 PM PDT 24
Finished May 16 02:25:43 PM PDT 24
Peak memory 248216 kb
Host smart-0ed7ab18-57e2-41c9-8f75-87ba518e7912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243332192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1243332192
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2937088964
Short name T346
Test name
Test status
Simulation time 11441895094 ps
CPU time 962.68 seconds
Started May 16 02:18:05 PM PDT 24
Finished May 16 02:34:10 PM PDT 24
Peak memory 272780 kb
Host smart-c35a3ccb-1899-47b8-a7b8-cf337e6e016c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937088964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2937088964
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1555002947
Short name T36
Test name
Test status
Simulation time 281521930316 ps
CPU time 3205.2 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 03:12:56 PM PDT 24
Peak memory 281528 kb
Host smart-9f7125da-aa45-4bb3-9100-b43725eeecc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555002947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1555002947
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3980539605
Short name T38
Test name
Test status
Simulation time 1297590372 ps
CPU time 37.94 seconds
Started May 16 02:15:08 PM PDT 24
Finished May 16 02:15:48 PM PDT 24
Peak memory 249180 kb
Host smart-e23e2c19-fae5-4c69-9f0a-9f621c44d3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
39605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3980539605
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2391257597
Short name T15
Test name
Test status
Simulation time 54104497505 ps
CPU time 1145.51 seconds
Started May 16 02:17:36 PM PDT 24
Finished May 16 02:36:43 PM PDT 24
Peak memory 288836 kb
Host smart-835235f2-cac8-4358-826f-f0d470983d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391257597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2391257597
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.838420724
Short name T821
Test name
Test status
Simulation time 66042092664 ps
CPU time 963.68 seconds
Started May 16 02:40:13 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 264988 kb
Host smart-b4d5bcf5-7f26-45fb-b5a7-f89d2ba61ee6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838420724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.838420724
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1680400829
Short name T22
Test name
Test status
Simulation time 260087229418 ps
CPU time 1390.42 seconds
Started May 16 02:14:23 PM PDT 24
Finished May 16 02:37:34 PM PDT 24
Peak memory 273376 kb
Host smart-7f232755-bb41-4191-8fd3-847f76dcb67a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680400829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1680400829
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3579074183
Short name T214
Test name
Test status
Simulation time 8100692630 ps
CPU time 44.98 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:16:57 PM PDT 24
Peak memory 247872 kb
Host smart-1596a838-7893-48b8-ae88-3358d075bd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
74183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3579074183
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2649985372
Short name T253
Test name
Test status
Simulation time 69227827636 ps
CPU time 2306.32 seconds
Started May 16 02:16:36 PM PDT 24
Finished May 16 02:55:04 PM PDT 24
Peak memory 286564 kb
Host smart-0def36f4-b0dc-4564-bbdd-b290539a5e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649985372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2649985372
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.466795527
Short name T64
Test name
Test status
Simulation time 816570228 ps
CPU time 30.77 seconds
Started May 16 02:16:35 PM PDT 24
Finished May 16 02:17:07 PM PDT 24
Peak memory 248744 kb
Host smart-551fceea-0609-49a9-99d3-4f50147eb0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46679
5527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.466795527
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3442809937
Short name T310
Test name
Test status
Simulation time 66161907439 ps
CPU time 4333.63 seconds
Started May 16 02:16:35 PM PDT 24
Finished May 16 03:28:51 PM PDT 24
Peak memory 338480 kb
Host smart-9e6ab5dd-b258-4b11-818a-118fea441b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442809937 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3442809937
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1128140493
Short name T139
Test name
Test status
Simulation time 17842204321 ps
CPU time 1161.73 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:36:50 PM PDT 24
Peak memory 273076 kb
Host smart-2c98af7b-0ae5-412e-b61e-f35f3b80f9a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128140493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1128140493
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.150256039
Short name T325
Test name
Test status
Simulation time 13755438713 ps
CPU time 200.7 seconds
Started May 16 02:17:37 PM PDT 24
Finished May 16 02:21:00 PM PDT 24
Peak memory 248048 kb
Host smart-e68e4688-6968-4675-a326-7ca498e5c133
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150256039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.150256039
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.4139953064
Short name T290
Test name
Test status
Simulation time 210927535 ps
CPU time 8.8 seconds
Started May 16 02:17:55 PM PDT 24
Finished May 16 02:18:05 PM PDT 24
Peak memory 248736 kb
Host smart-fbb16bae-eaaa-4bf1-8427-4786191b827d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41399
53064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.4139953064
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3273807513
Short name T134
Test name
Test status
Simulation time 155089633509 ps
CPU time 7886.76 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 04:29:33 PM PDT 24
Peak memory 371424 kb
Host smart-beaef931-275b-4461-a93f-6ea72b00fd79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273807513 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3273807513
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.98307715
Short name T301
Test name
Test status
Simulation time 369027048 ps
CPU time 17.69 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 02:18:23 PM PDT 24
Peak memory 255256 kb
Host smart-33d39278-c814-4a5c-80de-d6d7041c278a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98307
715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.98307715
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.13174573
Short name T285
Test name
Test status
Simulation time 360436622092 ps
CPU time 2042.86 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:48:51 PM PDT 24
Peak memory 286276 kb
Host smart-80248ccc-719e-4b46-952c-c84ba830cc36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handl
er_stress_all.13174573
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1783912121
Short name T144
Test name
Test status
Simulation time 24663572465 ps
CPU time 407.83 seconds
Started May 16 02:19:16 PM PDT 24
Finished May 16 02:26:06 PM PDT 24
Peak memory 256952 kb
Host smart-9bda816f-cee7-47f7-b0e1-065fa9978df9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783912121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1783912121
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3996469006
Short name T277
Test name
Test status
Simulation time 651340340 ps
CPU time 41.24 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:20:11 PM PDT 24
Peak memory 255956 kb
Host smart-3ef4ffa1-5d84-4cae-841f-a0f9e1344a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39964
69006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3996469006
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2162915877
Short name T295
Test name
Test status
Simulation time 104045350 ps
CPU time 12.69 seconds
Started May 16 02:19:36 PM PDT 24
Finished May 16 02:19:51 PM PDT 24
Peak memory 248704 kb
Host smart-46bb2505-675f-47b7-833a-e1a590912cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21629
15877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2162915877
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2075130415
Short name T296
Test name
Test status
Simulation time 2620454903 ps
CPU time 39.75 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:28 PM PDT 24
Peak memory 248916 kb
Host smart-a3b7c759-14d9-4454-9813-d0335eef95d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
30415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2075130415
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3743567437
Short name T110
Test name
Test status
Simulation time 203394653480 ps
CPU time 3547.75 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 03:19:38 PM PDT 24
Peak memory 304452 kb
Host smart-19d5169a-34bf-485e-b145-39337cd89afc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743567437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3743567437
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1977255886
Short name T292
Test name
Test status
Simulation time 2712802668 ps
CPU time 49.43 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:16:26 PM PDT 24
Peak memory 256288 kb
Host smart-907f24b7-5fd0-4849-9ac8-603bbf83e06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
55886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1977255886
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.429830883
Short name T194
Test name
Test status
Simulation time 408701324 ps
CPU time 52.57 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:41:02 PM PDT 24
Peak memory 240008 kb
Host smart-02a5d845-d7af-45f6-a892-013e292d42c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=429830883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.429830883
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3052227816
Short name T174
Test name
Test status
Simulation time 4382242276 ps
CPU time 386.1 seconds
Started May 16 02:40:03 PM PDT 24
Finished May 16 02:46:35 PM PDT 24
Peak memory 265032 kb
Host smart-733b2b99-6906-45d1-8eae-8d5afd5aaed6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3052227816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3052227816
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2170822874
Short name T180
Test name
Test status
Simulation time 4871364707 ps
CPU time 323.17 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:45:23 PM PDT 24
Peak memory 265080 kb
Host smart-1df3fd7c-f946-4856-8cb0-5bf5c5a98c6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2170822874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2170822874
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3906590890
Short name T170
Test name
Test status
Simulation time 28777260753 ps
CPU time 338.89 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:46:08 PM PDT 24
Peak memory 265076 kb
Host smart-8dea1605-747d-45ef-8570-87e9bb80a932
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906590890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3906590890
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1714273964
Short name T195
Test name
Test status
Simulation time 3674782319 ps
CPU time 67.51 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:41:10 PM PDT 24
Peak memory 240040 kb
Host smart-ffde0385-7567-4b73-8af6-f92c80ac7373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1714273964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1714273964
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3657945858
Short name T189
Test name
Test status
Simulation time 600109767 ps
CPU time 40.03 seconds
Started May 16 02:40:21 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 240056 kb
Host smart-db66a83b-9b7a-4920-8e57-e5511d061b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3657945858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3657945858
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1488393778
Short name T197
Test name
Test status
Simulation time 184874632 ps
CPU time 3.45 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:40 PM PDT 24
Peak memory 236508 kb
Host smart-bac5e8cc-5b02-4b5e-84c4-63a6835afa24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1488393778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1488393778
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1323692170
Short name T200
Test name
Test status
Simulation time 23425066 ps
CPU time 2.47 seconds
Started May 16 02:40:07 PM PDT 24
Finished May 16 02:40:14 PM PDT 24
Peak memory 235584 kb
Host smart-951c1314-3256-485b-a35c-fa3e67b82ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1323692170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1323692170
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3485961552
Short name T198
Test name
Test status
Simulation time 311645616 ps
CPU time 40.89 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:41:00 PM PDT 24
Peak memory 240008 kb
Host smart-6d79f724-a8e1-43a9-ae26-0d2b9d3170c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3485961552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3485961552
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.748743092
Short name T199
Test name
Test status
Simulation time 334652104 ps
CPU time 3.1 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:40:06 PM PDT 24
Peak memory 236732 kb
Host smart-5f39cb54-0e81-4ca6-af5d-feee16dcb71e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=748743092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.748743092
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3308898767
Short name T203
Test name
Test status
Simulation time 35841015 ps
CPU time 2.81 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:23 PM PDT 24
Peak memory 236564 kb
Host smart-ecd5364c-7826-4427-840a-8fda7784f575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3308898767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3308898767
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1876653220
Short name T205
Test name
Test status
Simulation time 43952679 ps
CPU time 3.53 seconds
Started May 16 02:40:25 PM PDT 24
Finished May 16 02:40:33 PM PDT 24
Peak memory 236848 kb
Host smart-00eb50d7-b6f8-4b94-9f54-a68723433a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1876653220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1876653220
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3693587348
Short name T202
Test name
Test status
Simulation time 50645338 ps
CPU time 2.77 seconds
Started May 16 02:40:25 PM PDT 24
Finished May 16 02:40:32 PM PDT 24
Peak memory 236524 kb
Host smart-2d065b0b-400b-4945-9d7e-e5e5a0b44e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3693587348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3693587348
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2260930798
Short name T201
Test name
Test status
Simulation time 365007324 ps
CPU time 47.05 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:50 PM PDT 24
Peak memory 239340 kb
Host smart-829bed77-09a6-4c46-b653-30554f22b750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2260930798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2260930798
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3638944159
Short name T206
Test name
Test status
Simulation time 83743167 ps
CPU time 4.98 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:15 PM PDT 24
Peak memory 235536 kb
Host smart-2163a9bc-1ce9-42dc-b7dc-6fa422928e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3638944159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3638944159
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2208881342
Short name T187
Test name
Test status
Simulation time 152771772 ps
CPU time 3.01 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 236324 kb
Host smart-bf5537db-1e72-4ebf-b77d-ddf15910b91b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2208881342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2208881342
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2163908297
Short name T193
Test name
Test status
Simulation time 783865222 ps
CPU time 43.17 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:41:01 PM PDT 24
Peak memory 239352 kb
Host smart-87903f87-28fd-4b3c-970c-a2aefd887c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2163908297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2163908297
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3531070267
Short name T28
Test name
Test status
Simulation time 144497068279 ps
CPU time 2519.41 seconds
Started May 16 02:19:35 PM PDT 24
Finished May 16 03:01:37 PM PDT 24
Peak memory 289540 kb
Host smart-6421d51b-3438-4580-8618-55fde96edcab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531070267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3531070267
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1178070536
Short name T27
Test name
Test status
Simulation time 1478309161 ps
CPU time 62.62 seconds
Started May 16 02:20:27 PM PDT 24
Finished May 16 02:21:31 PM PDT 24
Peak memory 255648 kb
Host smart-d959da7e-d1bc-4831-a8a9-528b759f2c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780
70536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1178070536
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3119607394
Short name T756
Test name
Test status
Simulation time 2104455508 ps
CPU time 132.91 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:42:16 PM PDT 24
Peak memory 236472 kb
Host smart-fb190024-8e27-4127-afae-433f9dc9332d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3119607394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3119607394
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4117292730
Short name T734
Test name
Test status
Simulation time 6047525722 ps
CPU time 236.36 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:43:57 PM PDT 24
Peak memory 236580 kb
Host smart-481a3421-8e45-4914-a8e9-8ce14a343e4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4117292730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4117292730
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1434013286
Short name T724
Test name
Test status
Simulation time 102387625 ps
CPU time 9.97 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:10 PM PDT 24
Peak memory 240044 kb
Host smart-d06cfb7e-8c1a-4fcc-b5fb-a93ff80192ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1434013286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1434013286
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1212854043
Short name T786
Test name
Test status
Simulation time 61361428 ps
CPU time 9.8 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:10 PM PDT 24
Peak memory 256208 kb
Host smart-5a7d2040-b74c-47bd-8784-73018ac0efaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212854043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1212854043
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3390491008
Short name T809
Test name
Test status
Simulation time 63165667 ps
CPU time 5.88 seconds
Started May 16 02:39:53 PM PDT 24
Finished May 16 02:40:03 PM PDT 24
Peak memory 236516 kb
Host smart-a8641d68-ca04-425b-a90f-a99932ed6de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3390491008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3390491008
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.316069052
Short name T826
Test name
Test status
Simulation time 19131728 ps
CPU time 1.37 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:05 PM PDT 24
Peak memory 235480 kb
Host smart-c9fdef5f-bf10-4120-8bd5-0196adc4dc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316069052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.316069052
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1741676392
Short name T224
Test name
Test status
Simulation time 1217419619 ps
CPU time 20.58 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:22 PM PDT 24
Peak memory 244712 kb
Host smart-f874457c-7129-4676-894c-b46f22b0a119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1741676392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1741676392
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3046184609
Short name T152
Test name
Test status
Simulation time 4781262327 ps
CPU time 166.39 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:42:50 PM PDT 24
Peak memory 267132 kb
Host smart-b79ae331-be89-4ad9-a870-a27811f80b20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3046184609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3046184609
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3546105804
Short name T719
Test name
Test status
Simulation time 1410247289 ps
CPU time 21.15 seconds
Started May 16 02:39:58 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 248336 kb
Host smart-a7ae975b-c98c-4a99-9e49-7268abd8f956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3546105804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3546105804
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.595068600
Short name T733
Test name
Test status
Simulation time 4424263215 ps
CPU time 154.43 seconds
Started May 16 02:39:53 PM PDT 24
Finished May 16 02:42:31 PM PDT 24
Peak memory 240056 kb
Host smart-0e89f61a-5a19-4aff-8987-da08e3a1e715
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=595068600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.595068600
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.626818305
Short name T829
Test name
Test status
Simulation time 3405995002 ps
CPU time 110.49 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:41:50 PM PDT 24
Peak memory 236476 kb
Host smart-09e74554-b2ea-4876-bca1-01648f86d643
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=626818305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.626818305
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.992478269
Short name T820
Test name
Test status
Simulation time 59822138 ps
CPU time 5.69 seconds
Started May 16 02:39:59 PM PDT 24
Finished May 16 02:40:11 PM PDT 24
Peak memory 239964 kb
Host smart-80611981-07c4-4fcc-9f9a-c743820d83fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=992478269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.992478269
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1735757132
Short name T372
Test name
Test status
Simulation time 79135453 ps
CPU time 9.28 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:13 PM PDT 24
Peak memory 251364 kb
Host smart-749fdf02-8342-4fba-9e0b-06a7e1afeb0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735757132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1735757132
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1529201250
Short name T781
Test name
Test status
Simulation time 130481253 ps
CPU time 9.87 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:40:12 PM PDT 24
Peak memory 236516 kb
Host smart-a626904c-602c-427f-962e-19db7d570176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1529201250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1529201250
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2834326156
Short name T767
Test name
Test status
Simulation time 6842042 ps
CPU time 1.57 seconds
Started May 16 02:39:54 PM PDT 24
Finished May 16 02:40:00 PM PDT 24
Peak memory 236508 kb
Host smart-420b0c82-2c4f-4d88-9e1f-5c89e2175606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834326156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2834326156
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3115653122
Short name T831
Test name
Test status
Simulation time 357456472 ps
CPU time 12.61 seconds
Started May 16 02:40:07 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 244716 kb
Host smart-b9678332-0e80-4d84-a7d9-8d3101714cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3115653122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3115653122
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1528863860
Short name T175
Test name
Test status
Simulation time 15307469899 ps
CPU time 565.72 seconds
Started May 16 02:39:58 PM PDT 24
Finished May 16 02:49:30 PM PDT 24
Peak memory 265104 kb
Host smart-a0fd8761-3b67-42eb-9647-83f56df5cd69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528863860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1528863860
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2237707074
Short name T718
Test name
Test status
Simulation time 2412971393 ps
CPU time 13.95 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:40:16 PM PDT 24
Peak memory 252620 kb
Host smart-3ad14139-7890-48c2-8463-f15e51a29ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2237707074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2237707074
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4235609427
Short name T748
Test name
Test status
Simulation time 85177728 ps
CPU time 9.02 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 251792 kb
Host smart-76425ab0-8b31-4e2b-b30a-853ee55a1008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235609427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.4235609427
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3325197763
Short name T735
Test name
Test status
Simulation time 96252852 ps
CPU time 4.79 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:26 PM PDT 24
Peak memory 239272 kb
Host smart-1c02decb-21e7-40b0-8fe7-8219e0522fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3325197763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3325197763
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4020949751
Short name T753
Test name
Test status
Simulation time 56536024 ps
CPU time 1.32 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:20 PM PDT 24
Peak memory 236540 kb
Host smart-4635914f-8b91-4235-ab60-cacd463f8042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4020949751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4020949751
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2159639740
Short name T817
Test name
Test status
Simulation time 731938555 ps
CPU time 20.73 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 244684 kb
Host smart-ea87dcef-9202-4308-894b-2c083326bc77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2159639740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2159639740
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3296093556
Short name T732
Test name
Test status
Simulation time 100879894 ps
CPU time 7.56 seconds
Started May 16 02:40:18 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 248212 kb
Host smart-b4ac929e-4d8d-4840-b621-5ca03aeafb57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3296093556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3296093556
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.229260565
Short name T721
Test name
Test status
Simulation time 70854511 ps
CPU time 4.19 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:22 PM PDT 24
Peak memory 240072 kb
Host smart-61dfb361-8074-47b8-acc8-e417d3a45296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229260565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.229260565
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1608023017
Short name T743
Test name
Test status
Simulation time 248020521 ps
CPU time 9.08 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 236500 kb
Host smart-846bf0bc-9b04-4327-a3b2-1080f37b676d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1608023017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1608023017
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.924109807
Short name T794
Test name
Test status
Simulation time 19485206 ps
CPU time 1.4 seconds
Started May 16 02:40:18 PM PDT 24
Finished May 16 02:40:23 PM PDT 24
Peak memory 234560 kb
Host smart-6aa28f78-e749-4308-b669-d909b769cfd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=924109807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.924109807
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2191758683
Short name T742
Test name
Test status
Simulation time 2696001654 ps
CPU time 39.86 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:41:01 PM PDT 24
Peak memory 248312 kb
Host smart-aa3a8f83-48b3-44e2-babb-855873753292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2191758683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2191758683
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.506930299
Short name T157
Test name
Test status
Simulation time 8264734043 ps
CPU time 298.53 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:45:18 PM PDT 24
Peak memory 272620 kb
Host smart-1d2f8782-fcc2-474a-abab-0cdeb6f3d3ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=506930299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.506930299
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3665766328
Short name T150
Test name
Test status
Simulation time 32303391360 ps
CPU time 1100.02 seconds
Started May 16 02:40:19 PM PDT 24
Finished May 16 02:58:43 PM PDT 24
Peak memory 264996 kb
Host smart-069294f3-3e9e-44ac-bd5a-2a87b4731e96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665766328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3665766328
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2136227578
Short name T274
Test name
Test status
Simulation time 642188175 ps
CPU time 17.6 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 248360 kb
Host smart-a1874db3-3481-4206-928c-134e62aa6257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2136227578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2136227578
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.676704453
Short name T787
Test name
Test status
Simulation time 197564258 ps
CPU time 8.59 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 239356 kb
Host smart-a3aa02d4-b3b3-4458-ac93-346f63e4f3f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676704453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.676704453
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1388010045
Short name T373
Test name
Test status
Simulation time 363013101 ps
CPU time 8.76 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:29 PM PDT 24
Peak memory 236480 kb
Host smart-bc599457-8486-4fc3-8b19-fc8e0035517f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1388010045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1388010045
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1408150538
Short name T812
Test name
Test status
Simulation time 17194714 ps
CPU time 1.82 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:20 PM PDT 24
Peak memory 235604 kb
Host smart-8a7c8716-6b71-4dd2-b017-644519b07679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1408150538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1408150538
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.529713506
Short name T806
Test name
Test status
Simulation time 1170483577 ps
CPU time 20.31 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:40 PM PDT 24
Peak memory 248252 kb
Host smart-5f6b4dc5-60d9-4194-a3f6-5569d72213fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=529713506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.529713506
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1753283765
Short name T168
Test name
Test status
Simulation time 4832354313 ps
CPU time 661.71 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:51:22 PM PDT 24
Peak memory 265076 kb
Host smart-9e471c45-ae36-44ca-9715-b8e361a33309
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753283765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1753283765
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3381159297
Short name T717
Test name
Test status
Simulation time 499330577 ps
CPU time 4.58 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 247960 kb
Host smart-5cad7858-b823-4749-baa7-8b7dda621e54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3381159297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3381159297
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.836984643
Short name T783
Test name
Test status
Simulation time 192388112 ps
CPU time 20.19 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:40 PM PDT 24
Peak memory 239296 kb
Host smart-0d0ba613-ec85-4867-87a3-e3b8d288932f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=836984643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.836984643
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1871868360
Short name T370
Test name
Test status
Simulation time 516838113 ps
CPU time 5.42 seconds
Started May 16 02:40:25 PM PDT 24
Finished May 16 02:40:35 PM PDT 24
Peak memory 238424 kb
Host smart-e1b1a554-55d0-44d1-a7bb-b983cfc1ee7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871868360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1871868360
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3679544943
Short name T780
Test name
Test status
Simulation time 186338623 ps
CPU time 8.52 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:36 PM PDT 24
Peak memory 235548 kb
Host smart-30ce7586-de8a-4d21-8f59-a40cf30acc4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3679544943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3679544943
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1467305174
Short name T764
Test name
Test status
Simulation time 11205992 ps
CPU time 1.74 seconds
Started May 16 02:40:22 PM PDT 24
Finished May 16 02:40:28 PM PDT 24
Peak memory 235576 kb
Host smart-4ecbfec1-39b5-41bd-8e1d-218915c1f5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1467305174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1467305174
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4173838101
Short name T222
Test name
Test status
Simulation time 316012769 ps
CPU time 21.18 seconds
Started May 16 02:40:25 PM PDT 24
Finished May 16 02:40:51 PM PDT 24
Peak memory 243776 kb
Host smart-f6c91fdf-f491-4f7f-8ca8-f89f74a06cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4173838101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4173838101
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3595820879
Short name T172
Test name
Test status
Simulation time 24615885452 ps
CPU time 954.74 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:56:23 PM PDT 24
Peak memory 273092 kb
Host smart-9ec68d90-3661-4603-8fb3-f09d2361ee0d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595820879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3595820879
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3633382947
Short name T723
Test name
Test status
Simulation time 804254247 ps
CPU time 17.34 seconds
Started May 16 02:40:21 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 251776 kb
Host smart-7143293e-89db-45e2-98e9-ee173201c72c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3633382947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3633382947
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2683484436
Short name T230
Test name
Test status
Simulation time 29870755 ps
CPU time 4.05 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:40:33 PM PDT 24
Peak memory 252800 kb
Host smart-d856ae32-3b8c-40b1-a047-8fc31c015195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683484436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2683484436
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4230560808
Short name T795
Test name
Test status
Simulation time 147531516 ps
CPU time 4.56 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:33 PM PDT 24
Peak memory 235556 kb
Host smart-d2f79f48-049f-4419-94bb-ff06bb1e1297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4230560808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4230560808
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2177729124
Short name T803
Test name
Test status
Simulation time 7189020 ps
CPU time 1.32 seconds
Started May 16 02:40:25 PM PDT 24
Finished May 16 02:40:31 PM PDT 24
Peak memory 235604 kb
Host smart-455465e3-3ae9-4cf4-a7c5-70d475eb3306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2177729124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2177729124
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2621788308
Short name T220
Test name
Test status
Simulation time 4216868012 ps
CPU time 44.25 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:41:12 PM PDT 24
Peak memory 243832 kb
Host smart-5df9293c-c252-4527-a9e7-b90c93370410
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2621788308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2621788308
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.993236800
Short name T184
Test name
Test status
Simulation time 6173809506 ps
CPU time 207.87 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:43:56 PM PDT 24
Peak memory 265160 kb
Host smart-1a587d5d-4649-4ff6-95eb-3bbdc40b9afd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=993236800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.993236800
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1974688734
Short name T740
Test name
Test status
Simulation time 1372869348 ps
CPU time 26.19 seconds
Started May 16 02:40:26 PM PDT 24
Finished May 16 02:40:56 PM PDT 24
Peak memory 251532 kb
Host smart-49fcf835-84d7-4855-8e25-98f43bf9ef22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1974688734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1974688734
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3094925384
Short name T790
Test name
Test status
Simulation time 121941464 ps
CPU time 9.64 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 239364 kb
Host smart-1ab70976-1a69-430e-b263-a7473788d4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094925384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3094925384
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2927586877
Short name T833
Test name
Test status
Simulation time 149843106 ps
CPU time 4.88 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:32 PM PDT 24
Peak memory 239320 kb
Host smart-07a51637-41d1-4a23-8711-6d0f770fe6a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2927586877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2927586877
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.281214542
Short name T752
Test name
Test status
Simulation time 24692748 ps
CPU time 1.47 seconds
Started May 16 02:40:22 PM PDT 24
Finished May 16 02:40:29 PM PDT 24
Peak memory 235584 kb
Host smart-151d2609-d373-47c2-9898-4f2fd271215f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=281214542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.281214542
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1636908294
Short name T223
Test name
Test status
Simulation time 358551912 ps
CPU time 26.69 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:54 PM PDT 24
Peak memory 244712 kb
Host smart-b5e9722a-cd21-4f99-8382-a21b4233988e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1636908294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1636908294
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1302370518
Short name T162
Test name
Test status
Simulation time 3851108212 ps
CPU time 143.84 seconds
Started May 16 02:40:22 PM PDT 24
Finished May 16 02:42:50 PM PDT 24
Peak memory 265144 kb
Host smart-643a2b5c-93fb-4d1f-a54c-72d73815aff2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1302370518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1302370518
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.952388797
Short name T716
Test name
Test status
Simulation time 87598104 ps
CPU time 2.65 seconds
Started May 16 02:40:26 PM PDT 24
Finished May 16 02:40:32 PM PDT 24
Peak memory 247976 kb
Host smart-34397df5-5f71-42a0-8909-90db68a25401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=952388797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.952388797
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2020152564
Short name T778
Test name
Test status
Simulation time 204897323 ps
CPU time 9.16 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 250532 kb
Host smart-1e86415d-4c2d-4b96-bbda-3dc8ff5f4b06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020152564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2020152564
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.781242189
Short name T823
Test name
Test status
Simulation time 95529158 ps
CPU time 9.3 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 236484 kb
Host smart-79acdfa6-3509-404f-b5a7-b5f8990995fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=781242189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.781242189
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3427163884
Short name T366
Test name
Test status
Simulation time 9525820 ps
CPU time 1.39 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 234596 kb
Host smart-6053be9f-5d4a-41b0-bbdf-1a5fca863342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3427163884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3427163884
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2091849315
Short name T728
Test name
Test status
Simulation time 337832498 ps
CPU time 11.2 seconds
Started May 16 02:40:22 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 243688 kb
Host smart-199adea2-5aff-4b10-9346-bcf520835223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2091849315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2091849315
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1209077832
Short name T179
Test name
Test status
Simulation time 7302170173 ps
CPU time 506.81 seconds
Started May 16 02:40:27 PM PDT 24
Finished May 16 02:48:57 PM PDT 24
Peak memory 265048 kb
Host smart-8ee6427a-d9a0-42a9-b87f-45a715846c14
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209077832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1209077832
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3295813591
Short name T802
Test name
Test status
Simulation time 799838666 ps
CPU time 15.1 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:40:44 PM PDT 24
Peak memory 248380 kb
Host smart-6acd8bdf-a8dd-466b-a32d-facc5de7478e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3295813591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3295813591
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3933272570
Short name T229
Test name
Test status
Simulation time 126762786 ps
CPU time 2.9 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:40:31 PM PDT 24
Peak memory 236512 kb
Host smart-de5fcc0d-d428-468f-9789-ac369fc61af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3933272570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3933272570
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2831294231
Short name T729
Test name
Test status
Simulation time 54307482 ps
CPU time 5.11 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 240068 kb
Host smart-71c3b455-d560-4508-83d9-32c50077d605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831294231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2831294231
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3033532932
Short name T792
Test name
Test status
Simulation time 66110111 ps
CPU time 5.54 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:40:43 PM PDT 24
Peak memory 240024 kb
Host smart-c3a217f3-1392-4a83-be41-f262197b239a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3033532932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3033532932
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4016725525
Short name T191
Test name
Test status
Simulation time 6953328 ps
CPU time 1.48 seconds
Started May 16 02:40:37 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 236464 kb
Host smart-bd7a105c-e757-4ee5-90b4-a66d9bdaa958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016725525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4016725525
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.614271090
Short name T808
Test name
Test status
Simulation time 1368834381 ps
CPU time 48.27 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:41:24 PM PDT 24
Peak memory 244628 kb
Host smart-f367f9b4-4ce0-429f-851d-34768f656d91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=614271090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.614271090
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2461654248
Short name T155
Test name
Test status
Simulation time 8005182927 ps
CPU time 157.34 seconds
Started May 16 02:40:23 PM PDT 24
Finished May 16 02:43:05 PM PDT 24
Peak memory 266652 kb
Host smart-0758539d-c8ad-417c-bc37-d98f1ba375f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2461654248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2461654248
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.41517602
Short name T181
Test name
Test status
Simulation time 26251592917 ps
CPU time 525.77 seconds
Started May 16 02:40:24 PM PDT 24
Finished May 16 02:49:15 PM PDT 24
Peak memory 265000 kb
Host smart-2a96c2a4-69c2-432a-802c-f0a13f451672
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.41517602
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3843473420
Short name T763
Test name
Test status
Simulation time 671042366 ps
CPU time 15.09 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:52 PM PDT 24
Peak memory 248064 kb
Host smart-b98ed786-61a8-4c0c-8e30-f1866a48c248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3843473420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3843473420
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1346436093
Short name T801
Test name
Test status
Simulation time 277240847 ps
CPU time 10.77 seconds
Started May 16 02:40:36 PM PDT 24
Finished May 16 02:40:51 PM PDT 24
Peak memory 240116 kb
Host smart-bf4db5b2-9b55-4af6-b51b-85545b9c6c19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346436093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1346436093
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2065032417
Short name T219
Test name
Test status
Simulation time 548383947 ps
CPU time 4.54 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:41 PM PDT 24
Peak memory 238368 kb
Host smart-2e60d635-3bc7-46b7-8e5a-68b36a95f1a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2065032417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2065032417
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3762926796
Short name T796
Test name
Test status
Simulation time 24551344 ps
CPU time 1.46 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 235596 kb
Host smart-cba3cdc6-8a4e-4907-b28a-908191757028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762926796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3762926796
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1233220017
Short name T788
Test name
Test status
Simulation time 941768561 ps
CPU time 21.56 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 245844 kb
Host smart-50fb14c1-051a-4ded-b2f6-ca9751e8b401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1233220017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1233220017
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2319919402
Short name T824
Test name
Test status
Simulation time 8893583738 ps
CPU time 83.96 seconds
Started May 16 02:40:35 PM PDT 24
Finished May 16 02:42:03 PM PDT 24
Peak memory 255736 kb
Host smart-117b9bac-8bdc-4448-b252-d352e3fa259c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2319919402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2319919402
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2511441958
Short name T793
Test name
Test status
Simulation time 67692626 ps
CPU time 8.28 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:40:46 PM PDT 24
Peak memory 248104 kb
Host smart-54230459-bc92-4da0-9a91-4d4bf2d4bb27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2511441958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2511441958
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1075949219
Short name T746
Test name
Test status
Simulation time 63757936 ps
CPU time 5.5 seconds
Started May 16 02:40:34 PM PDT 24
Finished May 16 02:40:45 PM PDT 24
Peak memory 241816 kb
Host smart-b98c50e5-ac83-43cd-a42d-9f6ef65dfa09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075949219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1075949219
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3418500957
Short name T221
Test name
Test status
Simulation time 378201870 ps
CPU time 10.97 seconds
Started May 16 02:40:38 PM PDT 24
Finished May 16 02:40:52 PM PDT 24
Peak memory 240032 kb
Host smart-63bef916-806e-452c-b16c-aa224c82eaf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3418500957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3418500957
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1286620774
Short name T811
Test name
Test status
Simulation time 12969135 ps
CPU time 1.46 seconds
Started May 16 02:40:40 PM PDT 24
Finished May 16 02:40:44 PM PDT 24
Peak memory 234604 kb
Host smart-858ee8f3-3853-435b-9f1b-6b46b84d1166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286620774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1286620774
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3189167978
Short name T744
Test name
Test status
Simulation time 686739188 ps
CPU time 21.8 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 243736 kb
Host smart-f8ad0970-3eb0-4d86-876f-3c1456a50d68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3189167978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3189167978
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3470850845
Short name T832
Test name
Test status
Simulation time 63048930 ps
CPU time 9.47 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:46 PM PDT 24
Peak memory 251908 kb
Host smart-515473d5-6662-4b18-b1bc-5c0d0ed17394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3470850845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3470850845
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1829335243
Short name T747
Test name
Test status
Simulation time 1103712282 ps
CPU time 137.27 seconds
Started May 16 02:39:58 PM PDT 24
Finished May 16 02:42:22 PM PDT 24
Peak memory 240048 kb
Host smart-19d77fe6-4c1e-4115-9e0f-ade8e4a01772
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1829335243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1829335243
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.238749651
Short name T769
Test name
Test status
Simulation time 5631506192 ps
CPU time 253.36 seconds
Started May 16 02:39:58 PM PDT 24
Finished May 16 02:44:17 PM PDT 24
Peak memory 236508 kb
Host smart-01ab17bd-802e-468b-a141-8d0dc4da5102
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=238749651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.238749651
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.885443842
Short name T813
Test name
Test status
Simulation time 54889479 ps
CPU time 5.13 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:08 PM PDT 24
Peak memory 239912 kb
Host smart-264f179e-b30a-4f55-b44c-d38aadb7cd69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=885443842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.885443842
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1143547952
Short name T800
Test name
Test status
Simulation time 45428431 ps
CPU time 5.64 seconds
Started May 16 02:39:53 PM PDT 24
Finished May 16 02:40:03 PM PDT 24
Peak memory 240924 kb
Host smart-b92b1bd2-b402-4625-a870-7d329523822b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143547952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1143547952
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2380305714
Short name T798
Test name
Test status
Simulation time 287831167 ps
CPU time 5.53 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:40:08 PM PDT 24
Peak memory 236508 kb
Host smart-fe2fb4ad-da46-43dd-8b78-dbfb138c2cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2380305714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2380305714
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2529010523
Short name T765
Test name
Test status
Simulation time 9766599 ps
CPU time 1.55 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:05 PM PDT 24
Peak memory 235496 kb
Host smart-9184060e-aded-43bb-9b85-a4a5c80b002b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529010523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2529010523
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1451749509
Short name T776
Test name
Test status
Simulation time 1383190338 ps
CPU time 24.17 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 244632 kb
Host smart-e9375bd7-f169-45cf-af2c-568c3d3c81fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1451749509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1451749509
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3807174355
Short name T158
Test name
Test status
Simulation time 7839151444 ps
CPU time 553.15 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:49:17 PM PDT 24
Peak memory 265012 kb
Host smart-3d186b05-6b33-4c28-a603-ed9e57488547
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807174355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3807174355
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1113308070
Short name T722
Test name
Test status
Simulation time 97239402 ps
CPU time 10.09 seconds
Started May 16 02:39:59 PM PDT 24
Finished May 16 02:40:15 PM PDT 24
Peak memory 253204 kb
Host smart-ab7683aa-ed0e-40d4-a120-455114162d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1113308070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1113308070
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.187087032
Short name T777
Test name
Test status
Simulation time 11157302 ps
CPU time 1.6 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 235596 kb
Host smart-c1aeff24-7fec-4ff3-bea5-631bdd2de167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=187087032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.187087032
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.460541956
Short name T365
Test name
Test status
Simulation time 11300208 ps
CPU time 1.48 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 236500 kb
Host smart-0d78989a-56a9-44af-9c4f-1118ec406e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=460541956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.460541956
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.444963967
Short name T725
Test name
Test status
Simulation time 7722699 ps
CPU time 1.29 seconds
Started May 16 02:40:36 PM PDT 24
Finished May 16 02:40:41 PM PDT 24
Peak memory 236548 kb
Host smart-bb254cc6-de48-482a-9120-710f772976e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=444963967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.444963967
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2840870260
Short name T369
Test name
Test status
Simulation time 19091109 ps
CPU time 1.35 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236516 kb
Host smart-710bfe4a-727b-44ad-a923-f93017cfa8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840870260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2840870260
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1423221913
Short name T754
Test name
Test status
Simulation time 10858907 ps
CPU time 1.55 seconds
Started May 16 02:40:34 PM PDT 24
Finished May 16 02:40:41 PM PDT 24
Peak memory 235572 kb
Host smart-c2ce64df-aebd-488c-9a4b-2a54af698729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423221913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1423221913
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3499724246
Short name T726
Test name
Test status
Simulation time 8998574 ps
CPU time 1.68 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236520 kb
Host smart-2a702389-186e-4ebe-a18c-c3b3c4dc8543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3499724246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3499724246
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3995394213
Short name T774
Test name
Test status
Simulation time 10881954 ps
CPU time 1.6 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 236532 kb
Host smart-b519bfe6-aa48-4e48-8497-f006268ef7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3995394213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3995394213
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3467972053
Short name T814
Test name
Test status
Simulation time 8470289 ps
CPU time 1.54 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236548 kb
Host smart-656905f0-4044-4e6a-a18d-d6f71db44fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3467972053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3467972053
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.745542349
Short name T363
Test name
Test status
Simulation time 37080980 ps
CPU time 1.32 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 234636 kb
Host smart-10be502d-254b-4a5c-bba5-8377531468ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=745542349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.745542349
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1737877001
Short name T827
Test name
Test status
Simulation time 8699165 ps
CPU time 1.4 seconds
Started May 16 02:40:34 PM PDT 24
Finished May 16 02:40:40 PM PDT 24
Peak memory 235592 kb
Host smart-9e327f74-fc0c-4d3d-8dc5-77f50c55fc84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1737877001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1737877001
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1873769997
Short name T225
Test name
Test status
Simulation time 10105450216 ps
CPU time 131.55 seconds
Started May 16 02:40:03 PM PDT 24
Finished May 16 02:42:20 PM PDT 24
Peak memory 240096 kb
Host smart-8c240c67-0bf7-4a36-a6fe-525661bf1e45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1873769997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1873769997
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4185043221
Short name T779
Test name
Test status
Simulation time 15492076692 ps
CPU time 232.07 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:44:04 PM PDT 24
Peak memory 240124 kb
Host smart-e3da7f9d-3f2f-422d-9091-b211b411625a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4185043221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4185043221
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2248247352
Short name T192
Test name
Test status
Simulation time 73687632 ps
CPU time 4.42 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:15 PM PDT 24
Peak memory 240052 kb
Host smart-4a34d78c-c951-4eda-b1af-6b93b62ab242
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2248247352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2248247352
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.226991136
Short name T784
Test name
Test status
Simulation time 1086968672 ps
CPU time 7.28 seconds
Started May 16 02:40:04 PM PDT 24
Finished May 16 02:40:16 PM PDT 24
Peak memory 239920 kb
Host smart-8b1c5960-0bb5-4b3d-9ccf-3a27a6854d65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226991136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.226991136
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.371129828
Short name T766
Test name
Test status
Simulation time 248008658 ps
CPU time 11.08 seconds
Started May 16 02:40:03 PM PDT 24
Finished May 16 02:40:20 PM PDT 24
Peak memory 236476 kb
Host smart-a3de9221-2693-4810-8bec-6981cd1ef831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=371129828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.371129828
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.569539311
Short name T364
Test name
Test status
Simulation time 9789268 ps
CPU time 1.5 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:13 PM PDT 24
Peak memory 236460 kb
Host smart-f89d311e-bea3-469e-a679-4677e39dd985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=569539311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.569539311
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1390639374
Short name T758
Test name
Test status
Simulation time 2391920351 ps
CPU time 42.74 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:53 PM PDT 24
Peak memory 248268 kb
Host smart-c82e8eae-e4d3-4f37-8783-bd52a9358885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1390639374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1390639374
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2242392782
Short name T186
Test name
Test status
Simulation time 828867307 ps
CPU time 97.4 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:41:41 PM PDT 24
Peak memory 265012 kb
Host smart-276afc3b-17a6-486a-9b26-8cf748b1b4a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2242392782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2242392782
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1209614295
Short name T169
Test name
Test status
Simulation time 32938317685 ps
CPU time 527.45 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:48:47 PM PDT 24
Peak memory 268172 kb
Host smart-66ff60fc-c528-4a00-a2f3-6792b1d451af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209614295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1209614295
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4140913506
Short name T791
Test name
Test status
Simulation time 298047051 ps
CPU time 21.04 seconds
Started May 16 02:40:10 PM PDT 24
Finished May 16 02:40:35 PM PDT 24
Peak memory 251368 kb
Host smart-fa665636-943e-41ae-802f-f18e79bd55bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4140913506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4140913506
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1911719978
Short name T815
Test name
Test status
Simulation time 19639514 ps
CPU time 1.41 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 234616 kb
Host smart-1b6d3fa0-a5b8-4201-9e5b-3bfde3028cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1911719978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1911719978
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.541180613
Short name T773
Test name
Test status
Simulation time 37941899 ps
CPU time 1.34 seconds
Started May 16 02:40:38 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 236408 kb
Host smart-813ef4b4-9d5f-4720-9178-7edc0a469533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=541180613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.541180613
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4004272766
Short name T190
Test name
Test status
Simulation time 10793253 ps
CPU time 1.31 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 234548 kb
Host smart-c5b4292e-313d-49e8-a3b5-5ad409b98bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4004272766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4004272766
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2839342477
Short name T789
Test name
Test status
Simulation time 6860352 ps
CPU time 1.54 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 235604 kb
Host smart-c4ca0cfe-816a-4d34-b871-734aa78b8b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2839342477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2839342477
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4046278260
Short name T825
Test name
Test status
Simulation time 6125193 ps
CPU time 1.42 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 234508 kb
Host smart-94939bf2-cb2a-48a1-b861-c19ec7275fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4046278260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4046278260
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3086326416
Short name T810
Test name
Test status
Simulation time 20468966 ps
CPU time 1.51 seconds
Started May 16 02:40:37 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 235548 kb
Host smart-60e54ac7-c4c7-49d8-a26d-cdf127df1086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3086326416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3086326416
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.704114651
Short name T807
Test name
Test status
Simulation time 9714822 ps
CPU time 1.27 seconds
Started May 16 02:40:31 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 236496 kb
Host smart-9f78bfa0-28d2-4c9f-9c5f-aef86f1b191c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=704114651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.704114651
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2372188540
Short name T818
Test name
Test status
Simulation time 6854525 ps
CPU time 1.55 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 236552 kb
Host smart-ab1dbe46-3956-432b-8250-3e16757626c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2372188540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2372188540
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2431865294
Short name T727
Test name
Test status
Simulation time 1131374706 ps
CPU time 75.59 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 236524 kb
Host smart-5b51af45-cfa1-499b-83ad-2536adb9fa53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2431865294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2431865294
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2023257706
Short name T762
Test name
Test status
Simulation time 3404951973 ps
CPU time 210.88 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:43:41 PM PDT 24
Peak memory 235600 kb
Host smart-863c2b7a-6a49-418d-9424-3ed940042658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2023257706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2023257706
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2923835988
Short name T736
Test name
Test status
Simulation time 393003155 ps
CPU time 9.14 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:19 PM PDT 24
Peak memory 240024 kb
Host smart-a34a86a3-dcd6-4124-8ad6-ced9a85d26ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2923835988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2923835988
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2237664811
Short name T208
Test name
Test status
Simulation time 205371418 ps
CPU time 14.58 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:26 PM PDT 24
Peak memory 250524 kb
Host smart-96826921-7628-49f4-ac8f-c0064f6e07fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237664811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2237664811
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2093890206
Short name T830
Test name
Test status
Simulation time 2107431569 ps
CPU time 8.89 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:20 PM PDT 24
Peak memory 235556 kb
Host smart-c3ba3fcb-cf99-4283-afce-d62e8a5fa8d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2093890206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2093890206
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.549826514
Short name T750
Test name
Test status
Simulation time 8032832 ps
CPU time 1.36 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:12 PM PDT 24
Peak memory 236544 kb
Host smart-27a53e25-8f95-4d16-8bcc-3e64393f5413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=549826514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.549826514
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3669787939
Short name T770
Test name
Test status
Simulation time 1614959132 ps
CPU time 19.24 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:31 PM PDT 24
Peak memory 243784 kb
Host smart-840c7fe8-39cd-4edf-853b-504795cfd29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3669787939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3669787939
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1981664968
Short name T163
Test name
Test status
Simulation time 1741133027 ps
CPU time 123.9 seconds
Started May 16 02:40:07 PM PDT 24
Finished May 16 02:42:16 PM PDT 24
Peak memory 256808 kb
Host smart-4c0c1270-9fc6-4841-a4ae-b98a0994f06c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981664968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1981664968
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3779466666
Short name T177
Test name
Test status
Simulation time 24661262521 ps
CPU time 519.29 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:48:49 PM PDT 24
Peak memory 265088 kb
Host smart-b23274b2-a101-45e5-b351-f5f93ef8247c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779466666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3779466666
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1563564021
Short name T720
Test name
Test status
Simulation time 152515337 ps
CPU time 9.55 seconds
Started May 16 02:40:04 PM PDT 24
Finished May 16 02:40:19 PM PDT 24
Peak memory 248060 kb
Host smart-10b7e2d9-d9b4-471a-9b89-3cea2269403e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1563564021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1563564021
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2613548751
Short name T761
Test name
Test status
Simulation time 7813649 ps
CPU time 1.43 seconds
Started May 16 02:40:30 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 235588 kb
Host smart-085ea309-de97-4a8a-b719-08bddb090617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2613548751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2613548751
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1206835516
Short name T362
Test name
Test status
Simulation time 8289145 ps
CPU time 1.36 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 234592 kb
Host smart-0f1a36df-21ef-4abd-a82a-db66c2ca62ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206835516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1206835516
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3064358585
Short name T738
Test name
Test status
Simulation time 8442188 ps
CPU time 1.44 seconds
Started May 16 02:40:34 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 236536 kb
Host smart-be070237-5e85-42a0-b4bd-2e8ab646ff7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3064358585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3064358585
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1540284088
Short name T799
Test name
Test status
Simulation time 66248057 ps
CPU time 1.64 seconds
Started May 16 02:40:37 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 236348 kb
Host smart-a05a0fcf-890d-43e3-a3e0-7e529bd54a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1540284088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1540284088
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3072625415
Short name T367
Test name
Test status
Simulation time 7414426 ps
CPU time 1.41 seconds
Started May 16 02:40:36 PM PDT 24
Finished May 16 02:40:41 PM PDT 24
Peak memory 235592 kb
Host smart-c6f03074-55bf-44f5-bec9-39094035b438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3072625415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3072625415
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2957656055
Short name T368
Test name
Test status
Simulation time 13421366 ps
CPU time 1.4 seconds
Started May 16 02:40:37 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 236484 kb
Host smart-623ddd5a-b7a6-4859-abbe-b8df822efc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2957656055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2957656055
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2876123350
Short name T760
Test name
Test status
Simulation time 11388784 ps
CPU time 1.56 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 234608 kb
Host smart-a35fbf71-632a-4ad2-8d60-d602936749b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2876123350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2876123350
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1153077466
Short name T785
Test name
Test status
Simulation time 74800889 ps
CPU time 1.44 seconds
Started May 16 02:40:34 PM PDT 24
Finished May 16 02:40:40 PM PDT 24
Peak memory 236368 kb
Host smart-6cb0dc39-9fcd-448f-9c31-1d8406b645a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153077466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1153077466
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3492655170
Short name T759
Test name
Test status
Simulation time 9855509 ps
CPU time 1.58 seconds
Started May 16 02:40:32 PM PDT 24
Finished May 16 02:40:38 PM PDT 24
Peak memory 235612 kb
Host smart-f89cc31c-e129-4f31-9f46-4e055e03dc55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3492655170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3492655170
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.912894818
Short name T804
Test name
Test status
Simulation time 10010045 ps
CPU time 1.52 seconds
Started May 16 02:40:33 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 235568 kb
Host smart-08d729d7-9426-4170-9fc9-48edf6efdefc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=912894818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.912894818
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.204328047
Short name T371
Test name
Test status
Simulation time 1813141872 ps
CPU time 8.95 seconds
Started May 16 02:40:09 PM PDT 24
Finished May 16 02:40:22 PM PDT 24
Peak memory 238124 kb
Host smart-8459d236-d6f9-4948-ac1e-f50b93fbb1ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204328047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.204328047
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3920235822
Short name T768
Test name
Test status
Simulation time 59621677 ps
CPU time 3.77 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:14 PM PDT 24
Peak memory 236468 kb
Host smart-03876197-fd00-4d36-99ef-3ca2573414d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3920235822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3920235822
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1240508382
Short name T772
Test name
Test status
Simulation time 8607200 ps
CPU time 1.51 seconds
Started May 16 02:40:03 PM PDT 24
Finished May 16 02:40:10 PM PDT 24
Peak memory 235616 kb
Host smart-40d1bddf-e671-4c58-925c-e61032de6584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1240508382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1240508382
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3658861465
Short name T805
Test name
Test status
Simulation time 167109809 ps
CPU time 10.34 seconds
Started May 16 02:40:10 PM PDT 24
Finished May 16 02:40:24 PM PDT 24
Peak memory 240028 kb
Host smart-23c89e3c-c50d-4ad7-8845-56becff59c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3658861465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3658861465
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1966594712
Short name T757
Test name
Test status
Simulation time 124027068 ps
CPU time 8 seconds
Started May 16 02:40:06 PM PDT 24
Finished May 16 02:40:19 PM PDT 24
Peak memory 248300 kb
Host smart-65c8204b-59c5-4e15-9849-af8f25aa2da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1966594712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1966594712
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1672295014
Short name T275
Test name
Test status
Simulation time 34210972 ps
CPU time 2.27 seconds
Started May 16 02:40:04 PM PDT 24
Finished May 16 02:40:11 PM PDT 24
Peak memory 236904 kb
Host smart-72cdfd13-c84f-4d92-a832-091a362e8477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1672295014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1672295014
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2800023941
Short name T822
Test name
Test status
Simulation time 224000414 ps
CPU time 5.65 seconds
Started May 16 02:40:12 PM PDT 24
Finished May 16 02:40:21 PM PDT 24
Peak memory 239296 kb
Host smart-532ce1b0-fe7e-46d9-b2c6-59513fd798ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800023941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2800023941
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1344918452
Short name T737
Test name
Test status
Simulation time 64928035 ps
CPU time 5.76 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:16 PM PDT 24
Peak memory 236508 kb
Host smart-678cc542-0fd2-4a15-bec0-1c68049bad8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1344918452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1344918452
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1339462346
Short name T782
Test name
Test status
Simulation time 11276794 ps
CPU time 1.39 seconds
Started May 16 02:40:04 PM PDT 24
Finished May 16 02:40:10 PM PDT 24
Peak memory 235632 kb
Host smart-70018b9b-0f50-4883-9518-39321e9f8987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1339462346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1339462346
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2667839562
Short name T755
Test name
Test status
Simulation time 173511229 ps
CPU time 24.68 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:35 PM PDT 24
Peak memory 244676 kb
Host smart-ed9d1caf-0f2b-45e0-95c2-a34c3dfd3eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2667839562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2667839562
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4236655865
Short name T176
Test name
Test status
Simulation time 2055287531 ps
CPU time 225.77 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:43:56 PM PDT 24
Peak memory 265164 kb
Host smart-10cd86c2-0819-46c9-855a-9cefca53e2d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236655865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4236655865
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2239832646
Short name T160
Test name
Test status
Simulation time 21395383368 ps
CPU time 567.24 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:49:38 PM PDT 24
Peak memory 265136 kb
Host smart-2af2d737-4909-43b0-9788-a0f740b342a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239832646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2239832646
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.702174492
Short name T771
Test name
Test status
Simulation time 88184498 ps
CPU time 10.02 seconds
Started May 16 02:40:05 PM PDT 24
Finished May 16 02:40:20 PM PDT 24
Peak memory 248320 kb
Host smart-ee4a84d9-7981-4b6c-9641-a660cb03a4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702174492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.702174492
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1063613992
Short name T266
Test name
Test status
Simulation time 169374076 ps
CPU time 15.41 seconds
Started May 16 02:40:13 PM PDT 24
Finished May 16 02:40:32 PM PDT 24
Peak memory 250696 kb
Host smart-7d32109c-57af-41a3-b1bd-8b65b31f3698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063613992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1063613992
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1674670095
Short name T730
Test name
Test status
Simulation time 762011296 ps
CPU time 10.23 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:32 PM PDT 24
Peak memory 239980 kb
Host smart-18017ae2-1a84-40b4-be8a-7df874c721bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1674670095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1674670095
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3192022954
Short name T741
Test name
Test status
Simulation time 9857515 ps
CPU time 1.37 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:21 PM PDT 24
Peak memory 236520 kb
Host smart-a52d40c2-fcd0-4e44-8888-1d8d02c1a4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192022954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3192022954
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2906554281
Short name T816
Test name
Test status
Simulation time 1124220250 ps
CPU time 25.27 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:44 PM PDT 24
Peak memory 244692 kb
Host smart-d349d6e1-3af3-4ec6-97c5-94120854330b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2906554281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2906554281
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3152609327
Short name T183
Test name
Test status
Simulation time 12833901846 ps
CPU time 1040.73 seconds
Started May 16 02:40:04 PM PDT 24
Finished May 16 02:57:31 PM PDT 24
Peak memory 265304 kb
Host smart-a825ef01-be85-4ac0-866c-1cd101ac92a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152609327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3152609327
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.214716397
Short name T819
Test name
Test status
Simulation time 82630792 ps
CPU time 6.73 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 252660 kb
Host smart-dc163213-336d-4485-b51c-8fd91abb8e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=214716397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.214716397
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2266673380
Short name T209
Test name
Test status
Simulation time 633306102 ps
CPU time 7.08 seconds
Started May 16 02:40:19 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 248324 kb
Host smart-9b93ec38-52a3-4251-b02d-d375d87519cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266673380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2266673380
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.87814188
Short name T797
Test name
Test status
Simulation time 178666455 ps
CPU time 8.4 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:28 PM PDT 24
Peak memory 236496 kb
Host smart-7ccbb135-f6a0-44cb-b87f-2d7c0ce16e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=87814188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.87814188
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1333543116
Short name T207
Test name
Test status
Simulation time 1905656964 ps
CPU time 39.06 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 248260 kb
Host smart-9246cfd4-3244-4e41-8cf1-9443361f113a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1333543116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1333543116
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1870260782
Short name T173
Test name
Test status
Simulation time 5270109664 ps
CPU time 205.78 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:43:45 PM PDT 24
Peak memory 265056 kb
Host smart-f8ddc832-12f1-4b7a-ba51-b0523cd7908f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1870260782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1870260782
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3098508661
Short name T156
Test name
Test status
Simulation time 6422911779 ps
CPU time 587.2 seconds
Started May 16 02:40:15 PM PDT 24
Finished May 16 02:50:06 PM PDT 24
Peak memory 265072 kb
Host smart-cf1acccc-afd7-47b7-b5d5-98cc8235b019
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098508661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3098508661
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.54446549
Short name T745
Test name
Test status
Simulation time 222770532 ps
CPU time 15.82 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:37 PM PDT 24
Peak memory 248284 kb
Host smart-fe2169b8-0c2a-43bd-aa03-af6721884675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=54446549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.54446549
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.567842455
Short name T739
Test name
Test status
Simulation time 134717154 ps
CPU time 10.13 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:30 PM PDT 24
Peak memory 238868 kb
Host smart-856bdab9-37c8-4c04-acfd-81e8053de99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567842455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.567842455
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1883767538
Short name T775
Test name
Test status
Simulation time 68276726 ps
CPU time 5.93 seconds
Started May 16 02:40:17 PM PDT 24
Finished May 16 02:40:27 PM PDT 24
Peak memory 236508 kb
Host smart-ad3faa4e-06b7-435b-8cda-6402016f6ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1883767538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1883767538
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3959431197
Short name T828
Test name
Test status
Simulation time 9418817 ps
CPU time 1.57 seconds
Started May 16 02:40:19 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 236548 kb
Host smart-9eca07c9-bad0-4d6f-ae7d-b2f634f08156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3959431197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3959431197
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1049045736
Short name T731
Test name
Test status
Simulation time 253980673 ps
CPU time 24.47 seconds
Started May 16 02:40:14 PM PDT 24
Finished May 16 02:40:42 PM PDT 24
Peak memory 244688 kb
Host smart-a93c9028-3f36-4368-9bc8-3ca6039c22d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1049045736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1049045736
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4104616487
Short name T164
Test name
Test status
Simulation time 12591975511 ps
CPU time 928.86 seconds
Started May 16 02:40:19 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 264948 kb
Host smart-0c707c6d-1903-4dd0-bddd-9d081e8e4b9b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104616487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4104616487
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1543878796
Short name T749
Test name
Test status
Simulation time 125856988 ps
CPU time 8.83 seconds
Started May 16 02:40:16 PM PDT 24
Finished May 16 02:40:29 PM PDT 24
Peak memory 248248 kb
Host smart-b7084ddc-207f-4b50-8c13-c92308931448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1543878796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1543878796
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3468273
Short name T521
Test name
Test status
Simulation time 30262789986 ps
CPU time 1288.4 seconds
Started May 16 02:14:12 PM PDT 24
Finished May 16 02:35:42 PM PDT 24
Peak memory 289548 kb
Host smart-5ad1a0a2-8719-421b-8d2a-9f207ba1903f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3468273
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1530835331
Short name T632
Test name
Test status
Simulation time 176563487 ps
CPU time 9.9 seconds
Started May 16 02:14:12 PM PDT 24
Finished May 16 02:14:23 PM PDT 24
Peak memory 248764 kb
Host smart-e8ed84cb-9562-473a-b27e-946994b6c35a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1530835331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1530835331
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1002460947
Short name T424
Test name
Test status
Simulation time 9172060095 ps
CPU time 159.01 seconds
Started May 16 02:14:17 PM PDT 24
Finished May 16 02:16:57 PM PDT 24
Peak memory 256884 kb
Host smart-3d407ac3-c38a-4515-9e9d-1ef941376cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10024
60947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1002460947
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1055154743
Short name T551
Test name
Test status
Simulation time 2901760892 ps
CPU time 39.53 seconds
Started May 16 02:14:11 PM PDT 24
Finished May 16 02:14:52 PM PDT 24
Peak memory 256048 kb
Host smart-c14c164b-4028-4872-8879-c6e5c0bab253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10551
54743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1055154743
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.912401512
Short name T649
Test name
Test status
Simulation time 40471240592 ps
CPU time 1182.49 seconds
Started May 16 02:14:13 PM PDT 24
Finished May 16 02:33:57 PM PDT 24
Peak memory 270996 kb
Host smart-5d6ee4f5-753e-491b-a31e-cb95744d9761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912401512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.912401512
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.189099701
Short name T532
Test name
Test status
Simulation time 74377461831 ps
CPU time 2507.92 seconds
Started May 16 02:14:17 PM PDT 24
Finished May 16 02:56:06 PM PDT 24
Peak memory 289268 kb
Host smart-8d49dbc5-4f9e-42cc-805f-b9b994745d9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189099701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.189099701
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1676122693
Short name T319
Test name
Test status
Simulation time 4437723335 ps
CPU time 165.79 seconds
Started May 16 02:14:13 PM PDT 24
Finished May 16 02:17:00 PM PDT 24
Peak memory 248176 kb
Host smart-76b1565b-94bd-44f1-8837-bde66a19be87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676122693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1676122693
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2131239292
Short name T674
Test name
Test status
Simulation time 813452610 ps
CPU time 44.02 seconds
Started May 16 02:14:03 PM PDT 24
Finished May 16 02:14:48 PM PDT 24
Peak memory 248700 kb
Host smart-884d72c7-acd5-41aa-bead-c0849a024721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
39292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2131239292
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2938715663
Short name T83
Test name
Test status
Simulation time 1130800422 ps
CPU time 27.62 seconds
Started May 16 02:14:04 PM PDT 24
Finished May 16 02:14:33 PM PDT 24
Peak memory 247408 kb
Host smart-e997eafa-d2f8-4435-adc3-05b041288d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29387
15663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2938715663
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3079929400
Short name T11
Test name
Test status
Simulation time 213582149 ps
CPU time 12.46 seconds
Started May 16 02:14:12 PM PDT 24
Finished May 16 02:14:26 PM PDT 24
Peak memory 270220 kb
Host smart-ea0f1591-1c6a-48ce-8cb6-e7ab7944f83a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3079929400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3079929400
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.735117424
Short name T420
Test name
Test status
Simulation time 7253865700 ps
CPU time 42.2 seconds
Started May 16 02:14:18 PM PDT 24
Finished May 16 02:15:01 PM PDT 24
Peak memory 255368 kb
Host smart-abf655ad-e9fd-494f-9060-41206bf0ec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73511
7424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.735117424
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2967441086
Short name T688
Test name
Test status
Simulation time 350368773 ps
CPU time 9.49 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:14:13 PM PDT 24
Peak memory 248752 kb
Host smart-3c6ab6b6-21e2-4921-90c2-c87049790799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
41086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2967441086
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3315131626
Short name T44
Test name
Test status
Simulation time 19523820148 ps
CPU time 860.1 seconds
Started May 16 02:14:18 PM PDT 24
Finished May 16 02:28:39 PM PDT 24
Peak memory 265168 kb
Host smart-2530162a-1ee7-4be9-84b1-05d2717d3f98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315131626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3315131626
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2754141287
Short name T304
Test name
Test status
Simulation time 46505085091 ps
CPU time 752.94 seconds
Started May 16 02:14:12 PM PDT 24
Finished May 16 02:26:46 PM PDT 24
Peak memory 273476 kb
Host smart-c765836f-dd2c-4212-9b93-b003eb8b62e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754141287 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2754141287
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1236575918
Short name T242
Test name
Test status
Simulation time 17514142 ps
CPU time 2.41 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:28 PM PDT 24
Peak memory 248876 kb
Host smart-1ab84ab4-4158-4e6f-bd1a-586abb3b2f81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1236575918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1236575918
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1605579827
Short name T430
Test name
Test status
Simulation time 99272534563 ps
CPU time 2718.11 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:59:43 PM PDT 24
Peak memory 289672 kb
Host smart-d0cd9317-dea7-4a32-be67-d7d7c7adb5b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605579827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1605579827
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2170999084
Short name T691
Test name
Test status
Simulation time 1559697367 ps
CPU time 19.04 seconds
Started May 16 02:14:23 PM PDT 24
Finished May 16 02:14:43 PM PDT 24
Peak memory 248732 kb
Host smart-6b2dc1b1-43dc-46d0-98ae-abb3c61d1ed1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2170999084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2170999084
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3974414202
Short name T580
Test name
Test status
Simulation time 16507240688 ps
CPU time 219.42 seconds
Started May 16 02:14:27 PM PDT 24
Finished May 16 02:18:07 PM PDT 24
Peak memory 256912 kb
Host smart-450535d8-b062-401b-81e8-a383247ea981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39744
14202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3974414202
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2515341793
Short name T665
Test name
Test status
Simulation time 1405126963 ps
CPU time 12.96 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:38 PM PDT 24
Peak memory 248736 kb
Host smart-c9555a5f-4e9c-48fe-b9f3-ba3ec097228d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
41793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2515341793
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3464197294
Short name T352
Test name
Test status
Simulation time 23711814677 ps
CPU time 1398.51 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:37:44 PM PDT 24
Peak memory 273108 kb
Host smart-0c27e810-a73b-4f66-b7c6-092cd049a934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464197294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3464197294
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3704058068
Short name T322
Test name
Test status
Simulation time 2051495437 ps
CPU time 84.73 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:15:49 PM PDT 24
Peak memory 247816 kb
Host smart-ee626add-d4aa-441e-a993-0917215b665d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704058068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3704058068
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1869215468
Short name T505
Test name
Test status
Simulation time 644748288 ps
CPU time 11.12 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:37 PM PDT 24
Peak memory 248796 kb
Host smart-5ffc4ae1-9ae2-424a-a121-8c3c08c58a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18692
15468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1869215468
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2806963778
Short name T61
Test name
Test status
Simulation time 169930712 ps
CPU time 11.82 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:37 PM PDT 24
Peak memory 248704 kb
Host smart-bdd6330f-d54d-4bec-8e00-8a7cfc1aa3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
63778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2806963778
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.520494733
Short name T34
Test name
Test status
Simulation time 1371052517 ps
CPU time 19.95 seconds
Started May 16 02:14:25 PM PDT 24
Finished May 16 02:14:46 PM PDT 24
Peak memory 273288 kb
Host smart-bbb440d8-86e4-4bea-82e8-6a8581986eba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=520494733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.520494733
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1068484676
Short name T89
Test name
Test status
Simulation time 355154527 ps
CPU time 20.38 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:46 PM PDT 24
Peak memory 256404 kb
Host smart-52e9d352-5294-40da-bf99-2ea0ae148bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10684
84676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1068484676
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3440959759
Short name T74
Test name
Test status
Simulation time 37647457 ps
CPU time 3.41 seconds
Started May 16 02:14:13 PM PDT 24
Finished May 16 02:14:17 PM PDT 24
Peak memory 240560 kb
Host smart-8b6527fb-7ee8-47d4-a74b-2e37a88b224a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34409
59759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3440959759
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3936028714
Short name T55
Test name
Test status
Simulation time 324253304985 ps
CPU time 3894.46 seconds
Started May 16 02:14:26 PM PDT 24
Finished May 16 03:19:21 PM PDT 24
Peak memory 322476 kb
Host smart-089191d4-85e4-4398-8613-8bce875a1113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936028714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3936028714
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1933699230
Short name T39
Test name
Test status
Simulation time 90562468137 ps
CPU time 1548.06 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:41:35 PM PDT 24
Peak memory 273388 kb
Host smart-c2fbd000-3567-4a44-899a-d8db50c8cf88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933699230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1933699230
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2401708000
Short name T147
Test name
Test status
Simulation time 3257212900 ps
CPU time 39.22 seconds
Started May 16 02:15:46 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 248800 kb
Host smart-cc24857c-70e0-4e94-8988-f8963b079466
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2401708000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2401708000
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1444085959
Short name T523
Test name
Test status
Simulation time 15449915297 ps
CPU time 221.84 seconds
Started May 16 02:15:44 PM PDT 24
Finished May 16 02:19:27 PM PDT 24
Peak memory 256924 kb
Host smart-093f1ea2-0403-43b2-8ab9-8da85ffe24a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
85959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1444085959
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1212476311
Short name T626
Test name
Test status
Simulation time 3020094770 ps
CPU time 43.3 seconds
Started May 16 02:15:50 PM PDT 24
Finished May 16 02:16:35 PM PDT 24
Peak memory 248828 kb
Host smart-55195e27-f823-4f5c-be28-96c466bc299e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
76311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1212476311
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.454371260
Short name T672
Test name
Test status
Simulation time 70376605594 ps
CPU time 2440.35 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:56:28 PM PDT 24
Peak memory 286028 kb
Host smart-9bb53c19-b4ae-4323-8d51-058ee674e47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454371260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.454371260
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1169651622
Short name T563
Test name
Test status
Simulation time 10687461783 ps
CPU time 540.24 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:24:47 PM PDT 24
Peak memory 265180 kb
Host smart-8ebe3fc6-96f3-47f5-9bbc-5867d19d53ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169651622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1169651622
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3381658497
Short name T320
Test name
Test status
Simulation time 41962528685 ps
CPU time 417.55 seconds
Started May 16 02:15:48 PM PDT 24
Finished May 16 02:22:47 PM PDT 24
Peak memory 248076 kb
Host smart-1d96346f-e723-4d05-8aab-a3684aff52a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381658497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3381658497
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.738225725
Short name T670
Test name
Test status
Simulation time 1425885669 ps
CPU time 21.66 seconds
Started May 16 02:15:44 PM PDT 24
Finished May 16 02:16:07 PM PDT 24
Peak memory 256828 kb
Host smart-dfb30ff4-db3b-4457-8b65-b16a0b4e7fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73822
5725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.738225725
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2325852974
Short name T592
Test name
Test status
Simulation time 668146326 ps
CPU time 34.47 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:16:22 PM PDT 24
Peak memory 255608 kb
Host smart-f1e3c60c-fa54-47dc-8837-613f1024ec86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
52974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2325852974
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3383794198
Short name T297
Test name
Test status
Simulation time 475038885 ps
CPU time 13.25 seconds
Started May 16 02:15:44 PM PDT 24
Finished May 16 02:15:58 PM PDT 24
Peak memory 254432 kb
Host smart-29ededb2-72c5-455b-bfe4-8445af6a8160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837
94198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3383794198
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4195356835
Short name T605
Test name
Test status
Simulation time 2360564784 ps
CPU time 12.83 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:16:00 PM PDT 24
Peak memory 248796 kb
Host smart-106be3e6-0d92-4d48-9926-108f82db9548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
56835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4195356835
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2766002589
Short name T589
Test name
Test status
Simulation time 16407325408 ps
CPU time 785.96 seconds
Started May 16 02:15:48 PM PDT 24
Finished May 16 02:28:56 PM PDT 24
Peak memory 266128 kb
Host smart-3a7811a6-e0a3-42e4-ba04-a48fca9eb433
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766002589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2766002589
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2696062492
Short name T234
Test name
Test status
Simulation time 67895789 ps
CPU time 2.42 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:16:01 PM PDT 24
Peak memory 248892 kb
Host smart-7b6c4456-d265-4f7b-af95-fc599be2b708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2696062492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2696062492
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3529486596
Short name T300
Test name
Test status
Simulation time 40705040549 ps
CPU time 2679.95 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 03:00:39 PM PDT 24
Peak memory 286108 kb
Host smart-f70feadc-9332-468a-be02-793a29848728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529486596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3529486596
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2457376576
Short name T512
Test name
Test status
Simulation time 2596326545 ps
CPU time 29.85 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:16:29 PM PDT 24
Peak memory 240592 kb
Host smart-aeae2831-c3c1-4947-86a0-51c610cb740f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2457376576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2457376576
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2296506517
Short name T417
Test name
Test status
Simulation time 5836092554 ps
CPU time 313.57 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:21:13 PM PDT 24
Peak memory 250944 kb
Host smart-532f8eec-5a4c-4e20-ac09-155af49b5ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
06517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2296506517
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3497684444
Short name T421
Test name
Test status
Simulation time 717003205 ps
CPU time 38.48 seconds
Started May 16 02:15:59 PM PDT 24
Finished May 16 02:16:39 PM PDT 24
Peak memory 248708 kb
Host smart-56b90624-5803-4161-9495-9553e6185b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
84444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3497684444
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3725035145
Short name T653
Test name
Test status
Simulation time 97056792990 ps
CPU time 1491.25 seconds
Started May 16 02:15:56 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 265284 kb
Host smart-d9b8f031-5a86-4671-94c4-e247dd280b34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725035145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3725035145
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3782669271
Short name T657
Test name
Test status
Simulation time 29311342142 ps
CPU time 1612.13 seconds
Started May 16 02:15:58 PM PDT 24
Finished May 16 02:42:52 PM PDT 24
Peak memory 266236 kb
Host smart-495e777c-9bd4-4d4c-8403-eeae6d46c4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782669271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3782669271
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1184045131
Short name T684
Test name
Test status
Simulation time 6239472886 ps
CPU time 60.27 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:16:59 PM PDT 24
Peak memory 256068 kb
Host smart-4b3bdde1-8061-4f16-b944-10c89a21baab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11840
45131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1184045131
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.498824559
Short name T541
Test name
Test status
Simulation time 875668126 ps
CPU time 56.05 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:16:55 PM PDT 24
Peak memory 248844 kb
Host smart-3d3350f1-92b6-414c-bff1-ceeb99673aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49882
4559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.498824559
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1208549204
Short name T620
Test name
Test status
Simulation time 691346664 ps
CPU time 23.07 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 02:16:21 PM PDT 24
Peak memory 247456 kb
Host smart-a8454e87-c7f4-401f-9cb9-23064504b292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
49204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1208549204
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4103900317
Short name T416
Test name
Test status
Simulation time 262448060 ps
CPU time 8.44 seconds
Started May 16 02:15:56 PM PDT 24
Finished May 16 02:16:06 PM PDT 24
Peak memory 248728 kb
Host smart-fdff6bdc-33a8-47da-8684-9fa391fd15d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41039
00317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4103900317
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3560002459
Short name T483
Test name
Test status
Simulation time 132414169242 ps
CPU time 1304.99 seconds
Started May 16 02:15:56 PM PDT 24
Finished May 16 02:37:42 PM PDT 24
Peak memory 289436 kb
Host smart-073c4326-aa37-44ca-b6a1-11576ddc0fc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560002459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3560002459
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4124449947
Short name T116
Test name
Test status
Simulation time 288259638480 ps
CPU time 8904 seconds
Started May 16 02:15:57 PM PDT 24
Finished May 16 04:44:23 PM PDT 24
Peak memory 403908 kb
Host smart-b1c3689f-0247-4d76-8abd-7d67c04bc5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124449947 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4124449947
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.130424178
Short name T86
Test name
Test status
Simulation time 53228242537 ps
CPU time 1153.63 seconds
Started May 16 02:16:08 PM PDT 24
Finished May 16 02:35:24 PM PDT 24
Peak memory 281520 kb
Host smart-e50e352d-fea2-4e02-ac14-3051a9ecfeb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130424178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.130424178
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1689276549
Short name T604
Test name
Test status
Simulation time 3728586227 ps
CPU time 23.74 seconds
Started May 16 02:16:09 PM PDT 24
Finished May 16 02:16:34 PM PDT 24
Peak memory 248772 kb
Host smart-80ac4a5e-7f59-4aa6-ab20-a61aa78add3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1689276549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1689276549
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.643134399
Short name T555
Test name
Test status
Simulation time 1840597677 ps
CPU time 59.65 seconds
Started May 16 02:16:09 PM PDT 24
Finished May 16 02:17:11 PM PDT 24
Peak memory 256708 kb
Host smart-d6a05de1-5c65-4419-9625-f7d79aac18c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64313
4399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.643134399
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4051845574
Short name T576
Test name
Test status
Simulation time 945443681 ps
CPU time 58.19 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:17:10 PM PDT 24
Peak memory 255272 kb
Host smart-bff982cd-1501-4444-af22-e7c9a752094a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
45574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4051845574
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2914828130
Short name T354
Test name
Test status
Simulation time 125654181377 ps
CPU time 1984.64 seconds
Started May 16 02:16:08 PM PDT 24
Finished May 16 02:49:14 PM PDT 24
Peak memory 270276 kb
Host smart-6c80885e-fdec-4cb1-a900-8e55d29800bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914828130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2914828130
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1102201749
Short name T638
Test name
Test status
Simulation time 16481672717 ps
CPU time 1116.1 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:34:48 PM PDT 24
Peak memory 289344 kb
Host smart-212ea1ec-8f0e-4fe1-b129-ff316e057bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102201749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1102201749
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2979665905
Short name T228
Test name
Test status
Simulation time 270316705 ps
CPU time 7.29 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:16:18 PM PDT 24
Peak memory 256924 kb
Host smart-6dc443c9-1155-459d-8ec7-6e18fbac73a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
65905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2979665905
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1364454987
Short name T708
Test name
Test status
Simulation time 665946362 ps
CPU time 21.8 seconds
Started May 16 02:16:08 PM PDT 24
Finished May 16 02:16:31 PM PDT 24
Peak memory 247732 kb
Host smart-a0d032f0-1721-4f17-aff0-23d1f3dbec50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
54987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1364454987
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2435891517
Short name T449
Test name
Test status
Simulation time 736612691 ps
CPU time 29.62 seconds
Started May 16 02:16:12 PM PDT 24
Finished May 16 02:16:43 PM PDT 24
Peak memory 248752 kb
Host smart-910b7de1-0e41-482d-84cb-95e4a2639b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24358
91517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2435891517
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1430508762
Short name T137
Test name
Test status
Simulation time 46809624620 ps
CPU time 2661.14 seconds
Started May 16 02:16:09 PM PDT 24
Finished May 16 03:00:32 PM PDT 24
Peak memory 289092 kb
Host smart-52224492-87bf-4975-b6a3-09d2ab1daaa4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430508762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1430508762
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.45133287
Short name T241
Test name
Test status
Simulation time 39404813 ps
CPU time 2.41 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 248788 kb
Host smart-2a137d12-430d-4a28-afab-3fc46a9d5c44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=45133287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.45133287
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3351667023
Short name T115
Test name
Test status
Simulation time 87075913156 ps
CPU time 603.61 seconds
Started May 16 02:16:20 PM PDT 24
Finished May 16 02:26:28 PM PDT 24
Peak memory 265220 kb
Host smart-6c7dbd0b-97b4-45de-bba6-f8a533cb4004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351667023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3351667023
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2042517730
Short name T630
Test name
Test status
Simulation time 1568915800 ps
CPU time 11.47 seconds
Started May 16 02:16:22 PM PDT 24
Finished May 16 02:16:37 PM PDT 24
Peak memory 240540 kb
Host smart-f65ddac7-0a2b-4d33-a3cc-60cf69f8f48c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2042517730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2042517730
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2635182498
Short name T457
Test name
Test status
Simulation time 538306356 ps
CPU time 68.01 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:17:34 PM PDT 24
Peak memory 256744 kb
Host smart-d4805bbd-ec4c-4a78-aa25-afbe8642545a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
82498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2635182498
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3843365602
Short name T429
Test name
Test status
Simulation time 1307783431 ps
CPU time 26.58 seconds
Started May 16 02:16:08 PM PDT 24
Finished May 16 02:16:36 PM PDT 24
Peak memory 248884 kb
Host smart-a429f4fa-31bb-464c-a4a1-404e419ee552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38433
65602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3843365602
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2063149992
Short name T497
Test name
Test status
Simulation time 42232926808 ps
CPU time 990.72 seconds
Started May 16 02:16:23 PM PDT 24
Finished May 16 02:32:57 PM PDT 24
Peak memory 272552 kb
Host smart-38dfd019-e692-45b3-9d30-2968accf44da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063149992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2063149992
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2386888442
Short name T558
Test name
Test status
Simulation time 49886107396 ps
CPU time 2981.24 seconds
Started May 16 02:16:19 PM PDT 24
Finished May 16 03:06:05 PM PDT 24
Peak memory 289268 kb
Host smart-bf49353f-3cb3-44bc-b19b-8cffdbac2cc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386888442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2386888442
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3242110775
Short name T594
Test name
Test status
Simulation time 227584560 ps
CPU time 15.07 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 248648 kb
Host smart-44ce08b6-ab80-47a6-8089-82943d53f03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
10775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3242110775
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2420245744
Short name T554
Test name
Test status
Simulation time 391732644 ps
CPU time 18.89 seconds
Started May 16 02:16:10 PM PDT 24
Finished May 16 02:16:31 PM PDT 24
Peak memory 248724 kb
Host smart-a2fbddd4-ca16-4207-a55a-2f9a93e73a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
45744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2420245744
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2053951855
Short name T466
Test name
Test status
Simulation time 127885339 ps
CPU time 17.3 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:16:43 PM PDT 24
Peak memory 248756 kb
Host smart-d36d5b81-9fa7-41a3-a87f-d9b92102da84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
51855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2053951855
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3888344704
Short name T637
Test name
Test status
Simulation time 2817868985 ps
CPU time 34.41 seconds
Started May 16 02:16:08 PM PDT 24
Finished May 16 02:16:43 PM PDT 24
Peak memory 255984 kb
Host smart-daf909e4-b468-4daf-b9fc-55900275bf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
44704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3888344704
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2233785424
Short name T577
Test name
Test status
Simulation time 47410152514 ps
CPU time 562.75 seconds
Started May 16 02:16:19 PM PDT 24
Finished May 16 02:25:45 PM PDT 24
Peak memory 255480 kb
Host smart-da14472b-eba1-4793-a406-32e5f1cd2d0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233785424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2233785424
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.255604154
Short name T246
Test name
Test status
Simulation time 199371974 ps
CPU time 3.99 seconds
Started May 16 02:16:20 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 248848 kb
Host smart-98f0ecb0-3365-45cf-bbdd-f5cfdf7e9db8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=255604154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.255604154
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1536760929
Short name T570
Test name
Test status
Simulation time 2187820994 ps
CPU time 45.5 seconds
Started May 16 02:16:18 PM PDT 24
Finished May 16 02:17:06 PM PDT 24
Peak memory 248764 kb
Host smart-0568bbd5-4965-474b-9676-990db4e1b24f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1536760929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1536760929
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2854386110
Short name T13
Test name
Test status
Simulation time 20516932033 ps
CPU time 246.91 seconds
Started May 16 02:16:18 PM PDT 24
Finished May 16 02:20:27 PM PDT 24
Peak memory 256432 kb
Host smart-0431dde1-ca06-4488-bf39-83e0aadcafc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28543
86110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2854386110
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2565782998
Short name T425
Test name
Test status
Simulation time 130407984 ps
CPU time 8.26 seconds
Started May 16 02:16:19 PM PDT 24
Finished May 16 02:16:32 PM PDT 24
Peak memory 250960 kb
Host smart-d35b7b08-6a03-4d09-a819-952ad5246283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
82998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2565782998
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.765035213
Short name T514
Test name
Test status
Simulation time 16829088931 ps
CPU time 1329.51 seconds
Started May 16 02:16:22 PM PDT 24
Finished May 16 02:38:35 PM PDT 24
Peak memory 286160 kb
Host smart-b6b4ccee-0579-4d4e-905e-2a8a9f832c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765035213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.765035213
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3479369767
Short name T706
Test name
Test status
Simulation time 37461123436 ps
CPU time 2148.41 seconds
Started May 16 02:16:20 PM PDT 24
Finished May 16 02:52:12 PM PDT 24
Peak memory 273356 kb
Host smart-a047de82-8bf6-4480-94a3-f09bc3be5e97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479369767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3479369767
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2737881417
Short name T31
Test name
Test status
Simulation time 11435930934 ps
CPU time 190.18 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:19:36 PM PDT 24
Peak memory 248332 kb
Host smart-c28cb7f4-757b-473b-a529-b34d24fb7d90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737881417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2737881417
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2010571752
Short name T540
Test name
Test status
Simulation time 1021082180 ps
CPU time 21.19 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:16:46 PM PDT 24
Peak memory 248700 kb
Host smart-3928e63e-ae7d-4d1d-84f5-7afe4f9f1d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20105
71752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2010571752
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2384550706
Short name T79
Test name
Test status
Simulation time 985808797 ps
CPU time 35.84 seconds
Started May 16 02:16:19 PM PDT 24
Finished May 16 02:16:59 PM PDT 24
Peak memory 247744 kb
Host smart-f38a4bfb-85e5-44bf-8f73-ce591dbd7859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
50706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2384550706
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.604141966
Short name T461
Test name
Test status
Simulation time 1581266902 ps
CPU time 55.66 seconds
Started May 16 02:16:24 PM PDT 24
Finished May 16 02:17:22 PM PDT 24
Peak memory 248716 kb
Host smart-0448c47b-43a9-450f-b21e-a9f1b4e2d0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60414
1966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.604141966
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2311354267
Short name T85
Test name
Test status
Simulation time 106919243 ps
CPU time 11.21 seconds
Started May 16 02:16:21 PM PDT 24
Finished May 16 02:16:36 PM PDT 24
Peak memory 248716 kb
Host smart-fe088b22-9add-4922-898a-34081b59a02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
54267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2311354267
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3211291249
Short name T535
Test name
Test status
Simulation time 45072344130 ps
CPU time 671.55 seconds
Started May 16 02:16:20 PM PDT 24
Finished May 16 02:27:36 PM PDT 24
Peak memory 265184 kb
Host smart-8ad77a7f-f154-430c-88ad-6ede8ef1830a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211291249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3211291249
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1026932794
Short name T249
Test name
Test status
Simulation time 17689682 ps
CPU time 2.65 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:16:36 PM PDT 24
Peak memory 248900 kb
Host smart-c66e8f64-b30b-4e0b-8806-178eba59b4f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1026932794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1026932794
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2953347867
Short name T662
Test name
Test status
Simulation time 24175774288 ps
CPU time 1261.53 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:37:35 PM PDT 24
Peak memory 265176 kb
Host smart-26a9e50d-17e7-4c61-8213-d264204cf01f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953347867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2953347867
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4117173827
Short name T403
Test name
Test status
Simulation time 834474196 ps
CPU time 33.8 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:17:08 PM PDT 24
Peak memory 248744 kb
Host smart-2ced1ddb-ac61-4d64-baeb-77f207dcf79b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4117173827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4117173827
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2469777413
Short name T402
Test name
Test status
Simulation time 3087685485 ps
CPU time 152.74 seconds
Started May 16 02:16:33 PM PDT 24
Finished May 16 02:19:07 PM PDT 24
Peak memory 256980 kb
Host smart-9d5f71fc-81ab-4813-9606-b9abb510cd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
77413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2469777413
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1110113262
Short name T597
Test name
Test status
Simulation time 17946870444 ps
CPU time 61.14 seconds
Started May 16 02:16:33 PM PDT 24
Finished May 16 02:17:36 PM PDT 24
Peak memory 256224 kb
Host smart-721fae2e-6d7d-4a3e-89d3-fe6e9fdcfa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
13262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1110113262
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.125813380
Short name T445
Test name
Test status
Simulation time 12414160896 ps
CPU time 1412.47 seconds
Started May 16 02:16:35 PM PDT 24
Finished May 16 02:40:09 PM PDT 24
Peak memory 281588 kb
Host smart-6f79f52b-d555-424c-bcfd-b2379948e772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125813380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.125813380
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1767192296
Short name T438
Test name
Test status
Simulation time 68402660 ps
CPU time 4.67 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:16:38 PM PDT 24
Peak memory 240540 kb
Host smart-6bf1810d-d76f-4430-8b01-5b4932358335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17671
92296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1767192296
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.757924649
Short name T623
Test name
Test status
Simulation time 1843038997 ps
CPU time 64.14 seconds
Started May 16 02:16:31 PM PDT 24
Finished May 16 02:17:37 PM PDT 24
Peak memory 256664 kb
Host smart-270c91e0-920a-47ba-a144-52454536b845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75792
4649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.757924649
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3892263268
Short name T524
Test name
Test status
Simulation time 1535935350 ps
CPU time 32.53 seconds
Started May 16 02:16:35 PM PDT 24
Finished May 16 02:17:09 PM PDT 24
Peak memory 248748 kb
Host smart-a07bab10-f03e-47c8-ba4f-97c777b0bb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
63268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3892263268
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2876487754
Short name T499
Test name
Test status
Simulation time 5676043555 ps
CPU time 417.02 seconds
Started May 16 02:16:37 PM PDT 24
Finished May 16 02:23:35 PM PDT 24
Peak memory 265160 kb
Host smart-f0de1635-948b-4249-bb17-d4fdeb79d44c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876487754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2876487754
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2077895946
Short name T233
Test name
Test status
Simulation time 103660900 ps
CPU time 3.06 seconds
Started May 16 02:16:34 PM PDT 24
Finished May 16 02:16:38 PM PDT 24
Peak memory 248904 kb
Host smart-68519bde-ab39-4db2-b5ef-a3c3a046c008
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2077895946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2077895946
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3928507659
Short name T539
Test name
Test status
Simulation time 9564225893 ps
CPU time 791.84 seconds
Started May 16 02:16:34 PM PDT 24
Finished May 16 02:29:47 PM PDT 24
Peak memory 273372 kb
Host smart-53d69e52-c00a-4cbd-b9b6-d20282753ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928507659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3928507659
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2630858326
Short name T442
Test name
Test status
Simulation time 335686100 ps
CPU time 9.2 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:16:43 PM PDT 24
Peak memory 248700 kb
Host smart-1092703b-38fa-4061-b77f-79b6d9b4e3f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2630858326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2630858326
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3604015400
Short name T509
Test name
Test status
Simulation time 6284842776 ps
CPU time 133.41 seconds
Started May 16 02:16:35 PM PDT 24
Finished May 16 02:18:50 PM PDT 24
Peak memory 256956 kb
Host smart-39bd681d-68b8-4c74-bf1f-fd10473dfe76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36040
15400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3604015400
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2141022599
Short name T518
Test name
Test status
Simulation time 399153007 ps
CPU time 30.66 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:17:04 PM PDT 24
Peak memory 248756 kb
Host smart-4b15e16a-1d7d-42ab-87ef-7b3e8e195b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410
22599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2141022599
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2747210266
Short name T358
Test name
Test status
Simulation time 177706107003 ps
CPU time 2404.74 seconds
Started May 16 02:16:36 PM PDT 24
Finished May 16 02:56:42 PM PDT 24
Peak memory 270292 kb
Host smart-e118fa6b-5f40-4891-a7f6-bc8e57ad901b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747210266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2747210266
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2210133849
Short name T707
Test name
Test status
Simulation time 127319240990 ps
CPU time 2178.86 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:52:52 PM PDT 24
Peak memory 281552 kb
Host smart-595202cd-416e-4cfb-869f-3fdcf053c5fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210133849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2210133849
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3751594315
Short name T261
Test name
Test status
Simulation time 12017527289 ps
CPU time 231.53 seconds
Started May 16 02:16:33 PM PDT 24
Finished May 16 02:20:26 PM PDT 24
Peak memory 254684 kb
Host smart-4b572444-bbf5-42ee-aa3b-b1834d0dc99a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751594315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3751594315
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2006877788
Short name T453
Test name
Test status
Simulation time 2888949460 ps
CPU time 41.42 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:17:15 PM PDT 24
Peak memory 256108 kb
Host smart-16d669c6-e934-4e01-a9d1-e8233f5b8328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
77788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2006877788
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2399067353
Short name T257
Test name
Test status
Simulation time 1616067448 ps
CPU time 53.84 seconds
Started May 16 02:16:36 PM PDT 24
Finished May 16 02:17:31 PM PDT 24
Peak memory 255984 kb
Host smart-55d36a84-fa0c-4a0b-8bdd-05b44791431d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
67353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2399067353
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3964162766
Short name T552
Test name
Test status
Simulation time 2359558702 ps
CPU time 30.99 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:17:05 PM PDT 24
Peak memory 248100 kb
Host smart-7b356e68-678b-4508-84bd-c5de67bfa779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39641
62766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3964162766
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3107326928
Short name T635
Test name
Test status
Simulation time 754611300 ps
CPU time 46.8 seconds
Started May 16 02:16:32 PM PDT 24
Finished May 16 02:17:21 PM PDT 24
Peak memory 256264 kb
Host smart-ac3ef513-906d-434d-a50e-89c5eec9a02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
26928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3107326928
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2584864512
Short name T237
Test name
Test status
Simulation time 53394456 ps
CPU time 3.83 seconds
Started May 16 02:16:44 PM PDT 24
Finished May 16 02:16:49 PM PDT 24
Peak memory 248876 kb
Host smart-849121c8-90f0-4715-976e-19a51aeead84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2584864512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2584864512
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.787383594
Short name T405
Test name
Test status
Simulation time 27553343516 ps
CPU time 1371.84 seconds
Started May 16 02:16:45 PM PDT 24
Finished May 16 02:39:38 PM PDT 24
Peak memory 289216 kb
Host smart-aafa8317-33e3-4c47-9850-0eccd31cedec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787383594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.787383594
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3795666495
Short name T646
Test name
Test status
Simulation time 227469568 ps
CPU time 10.24 seconds
Started May 16 02:16:43 PM PDT 24
Finished May 16 02:16:54 PM PDT 24
Peak memory 248712 kb
Host smart-160bf191-3687-4f2c-94e8-fc8b88093f4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3795666495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3795666495
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1720458693
Short name T664
Test name
Test status
Simulation time 5358615096 ps
CPU time 55.49 seconds
Started May 16 02:16:44 PM PDT 24
Finished May 16 02:17:41 PM PDT 24
Peak memory 256868 kb
Host smart-afaa8e17-5ea6-4c66-85ae-2716060c3134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17204
58693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1720458693
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3602413123
Short name T460
Test name
Test status
Simulation time 11526564713 ps
CPU time 45.17 seconds
Started May 16 02:16:43 PM PDT 24
Finished May 16 02:17:30 PM PDT 24
Peak memory 248804 kb
Host smart-53754189-9d2b-4751-8ad6-c07b4fb2c426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
13123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3602413123
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3159384483
Short name T357
Test name
Test status
Simulation time 32717232077 ps
CPU time 1959.5 seconds
Started May 16 02:16:47 PM PDT 24
Finished May 16 02:49:28 PM PDT 24
Peak memory 272716 kb
Host smart-118f1845-54ea-4fe5-a710-1bce8dafee09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159384483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3159384483
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3966431525
Short name T380
Test name
Test status
Simulation time 16164210449 ps
CPU time 1417.61 seconds
Started May 16 02:16:43 PM PDT 24
Finished May 16 02:40:23 PM PDT 24
Peak memory 288756 kb
Host smart-5a5fd588-2d9d-435b-b688-6a8b30a0c932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966431525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3966431525
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1250626323
Short name T339
Test name
Test status
Simulation time 12752214550 ps
CPU time 506.05 seconds
Started May 16 02:16:47 PM PDT 24
Finished May 16 02:25:14 PM PDT 24
Peak memory 248308 kb
Host smart-aac0d68b-96c4-447b-96c5-5bd7b798e196
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250626323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1250626323
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1352031219
Short name T63
Test name
Test status
Simulation time 989666592 ps
CPU time 43.65 seconds
Started May 16 02:16:44 PM PDT 24
Finished May 16 02:17:29 PM PDT 24
Peak memory 248696 kb
Host smart-65db723c-3ad1-486a-a608-2f39a0ca3a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
31219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1352031219
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2553047595
Short name T476
Test name
Test status
Simulation time 211187732 ps
CPU time 3.91 seconds
Started May 16 02:16:42 PM PDT 24
Finished May 16 02:16:47 PM PDT 24
Peak memory 240528 kb
Host smart-21c3b719-6074-4047-965a-8179fd0dada0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
47595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2553047595
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2038169069
Short name T341
Test name
Test status
Simulation time 379709988 ps
CPU time 18.17 seconds
Started May 16 02:16:43 PM PDT 24
Finished May 16 02:17:03 PM PDT 24
Peak memory 248716 kb
Host smart-818fe3f3-a352-4c64-944e-7fe786571d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20381
69069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2038169069
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2831959515
Short name T459
Test name
Test status
Simulation time 273599249 ps
CPU time 15.4 seconds
Started May 16 02:16:42 PM PDT 24
Finished May 16 02:16:59 PM PDT 24
Peak memory 254656 kb
Host smart-e049788d-fbcb-4520-b51c-946784f2e369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28319
59515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2831959515
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.872062744
Short name T291
Test name
Test status
Simulation time 85288758103 ps
CPU time 2178.69 seconds
Started May 16 02:16:53 PM PDT 24
Finished May 16 02:53:12 PM PDT 24
Peak memory 322228 kb
Host smart-e080321b-8fe6-457a-aab4-3c3ca6e3aade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872062744 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.872062744
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2023703148
Short name T239
Test name
Test status
Simulation time 81152177 ps
CPU time 3.38 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:17:11 PM PDT 24
Peak memory 248880 kb
Host smart-e7725633-1485-4ab4-a8fd-bce08fe0ddd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2023703148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2023703148
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2681421950
Short name T536
Test name
Test status
Simulation time 47345837008 ps
CPU time 1154.84 seconds
Started May 16 02:16:52 PM PDT 24
Finished May 16 02:36:08 PM PDT 24
Peak memory 281944 kb
Host smart-dd59b69b-c649-48eb-b440-807f5e50c541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681421950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2681421950
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1856505257
Short name T530
Test name
Test status
Simulation time 520962123 ps
CPU time 8.33 seconds
Started May 16 02:16:56 PM PDT 24
Finished May 16 02:17:06 PM PDT 24
Peak memory 248732 kb
Host smart-298b94cf-1946-4770-9f72-427260cf558c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1856505257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1856505257
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1627338577
Short name T273
Test name
Test status
Simulation time 1806633295 ps
CPU time 102.27 seconds
Started May 16 02:16:54 PM PDT 24
Finished May 16 02:18:38 PM PDT 24
Peak memory 256768 kb
Host smart-0726dc94-fbad-4286-879b-6a135f448611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16273
38577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1627338577
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3920970602
Short name T427
Test name
Test status
Simulation time 1594852865 ps
CPU time 15.28 seconds
Started May 16 02:16:56 PM PDT 24
Finished May 16 02:17:13 PM PDT 24
Peak memory 253868 kb
Host smart-d73f4f90-7667-4a1a-aae4-0a434b3d86d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39209
70602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3920970602
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4810896
Short name T268
Test name
Test status
Simulation time 19385322245 ps
CPU time 1675.88 seconds
Started May 16 02:16:56 PM PDT 24
Finished May 16 02:44:53 PM PDT 24
Peak memory 289040 kb
Host smart-6c0a906d-2e6c-4710-8b8f-8b00e1941bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4810896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4810896
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2404338925
Short name T484
Test name
Test status
Simulation time 27902333574 ps
CPU time 804.1 seconds
Started May 16 02:16:54 PM PDT 24
Finished May 16 02:30:19 PM PDT 24
Peak memory 273364 kb
Host smart-87dbf816-481c-4190-bd54-fd1ee3eef5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404338925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2404338925
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4222603807
Short name T434
Test name
Test status
Simulation time 1383665441 ps
CPU time 23.36 seconds
Started May 16 02:16:53 PM PDT 24
Finished May 16 02:17:17 PM PDT 24
Peak memory 248748 kb
Host smart-bf6a012f-2ae0-4204-a7f9-4a4f7f80476d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
03807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4222603807
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.997505419
Short name T699
Test name
Test status
Simulation time 109455489 ps
CPU time 5.15 seconds
Started May 16 02:16:56 PM PDT 24
Finished May 16 02:17:02 PM PDT 24
Peak memory 252976 kb
Host smart-5d52c976-d233-4730-9f6e-6169e02ed9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99750
5419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.997505419
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2745031233
Short name T217
Test name
Test status
Simulation time 219272599 ps
CPU time 24.95 seconds
Started May 16 02:16:52 PM PDT 24
Finished May 16 02:17:18 PM PDT 24
Peak memory 248700 kb
Host smart-45e22736-f266-45b7-b1eb-4c942ac4abc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
31233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2745031233
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3289532652
Short name T627
Test name
Test status
Simulation time 198690408 ps
CPU time 5.45 seconds
Started May 16 02:16:54 PM PDT 24
Finished May 16 02:17:01 PM PDT 24
Peak memory 240520 kb
Host smart-f58e4bae-6c7b-4247-a8b3-91065f8e186e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
32652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3289532652
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1635837611
Short name T507
Test name
Test status
Simulation time 1923784557 ps
CPU time 104.1 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:18:51 PM PDT 24
Peak memory 256888 kb
Host smart-2359da3f-c079-41f8-badc-bcc92458b83f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635837611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1635837611
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.93969038
Short name T579
Test name
Test status
Simulation time 11407131783 ps
CPU time 1079.55 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:35:07 PM PDT 24
Peak memory 273444 kb
Host smart-57a182ac-11b8-4d32-bfbb-5f464574c432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93969038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.93969038
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2113829056
Short name T544
Test name
Test status
Simulation time 261278981 ps
CPU time 13.16 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:17:31 PM PDT 24
Peak memory 248760 kb
Host smart-367d05fc-ac2e-4752-8227-45fd38e224dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2113829056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2113829056
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2332161257
Short name T489
Test name
Test status
Simulation time 56923215604 ps
CPU time 252.89 seconds
Started May 16 02:17:05 PM PDT 24
Finished May 16 02:21:19 PM PDT 24
Peak memory 256952 kb
Host smart-873d7212-d4ef-42df-8f0b-86cfd720b6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
61257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2332161257
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1676210279
Short name T645
Test name
Test status
Simulation time 122481993 ps
CPU time 4.95 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:17:12 PM PDT 24
Peak memory 240468 kb
Host smart-3fd9d1cc-6e38-4dc0-8406-6612a1af4a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
10279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1676210279
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.842689608
Short name T350
Test name
Test status
Simulation time 14273616495 ps
CPU time 1386.73 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:40:25 PM PDT 24
Peak memory 282148 kb
Host smart-266db21e-10ee-4fb8-a74a-305f44dd831d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842689608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.842689608
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.352202821
Short name T71
Test name
Test status
Simulation time 36064558248 ps
CPU time 923.26 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:32:52 PM PDT 24
Peak memory 272392 kb
Host smart-40b6ce10-997e-4b5f-a16e-02b26bc4d6a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352202821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.352202821
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2914178054
Short name T419
Test name
Test status
Simulation time 382395844 ps
CPU time 16.88 seconds
Started May 16 02:17:07 PM PDT 24
Finished May 16 02:17:25 PM PDT 24
Peak memory 248792 kb
Host smart-83d8d924-b794-4c69-9a07-0921d419f2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
78054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2914178054
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1757039430
Short name T660
Test name
Test status
Simulation time 2847561046 ps
CPU time 42.54 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:17:50 PM PDT 24
Peak memory 254988 kb
Host smart-f75eb175-4e1d-416a-8db8-0300475fb4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570
39430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1757039430
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1461599188
Short name T283
Test name
Test status
Simulation time 291444643 ps
CPU time 11.51 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:17:19 PM PDT 24
Peak memory 252600 kb
Host smart-3c9340e8-16cf-4a10-ad49-c8c77438c086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615
99188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1461599188
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1752341396
Short name T679
Test name
Test status
Simulation time 376073301 ps
CPU time 20.07 seconds
Started May 16 02:17:06 PM PDT 24
Finished May 16 02:17:28 PM PDT 24
Peak memory 255812 kb
Host smart-f6190b87-7092-45db-9497-a8123f13c564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17523
41396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1752341396
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.120181999
Short name T114
Test name
Test status
Simulation time 6902752433 ps
CPU time 427.11 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:24:26 PM PDT 24
Peak memory 256984 kb
Host smart-54cbb318-0cb3-4eb8-93ce-782205f9d07e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120181999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.120181999
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.767974616
Short name T641
Test name
Test status
Simulation time 107067601139 ps
CPU time 5816.93 seconds
Started May 16 02:17:19 PM PDT 24
Finished May 16 03:54:17 PM PDT 24
Peak memory 321760 kb
Host smart-e8e9e0ec-7a0e-477e-a4d2-b2f4ee646a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767974616 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.767974616
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3754874693
Short name T235
Test name
Test status
Simulation time 269532742 ps
CPU time 3.47 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:14:39 PM PDT 24
Peak memory 248880 kb
Host smart-ec067913-22c4-484d-b2b1-7bdc29a7e532
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3754874693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3754874693
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3666566741
Short name T7
Test name
Test status
Simulation time 12947512262 ps
CPU time 1314.74 seconds
Started May 16 02:14:33 PM PDT 24
Finished May 16 02:36:29 PM PDT 24
Peak memory 289000 kb
Host smart-3d190fda-b262-4b0c-b296-0e22923f5ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666566741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3666566741
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1856501453
Short name T145
Test name
Test status
Simulation time 1514470379 ps
CPU time 59.56 seconds
Started May 16 02:14:35 PM PDT 24
Finished May 16 02:15:36 PM PDT 24
Peak memory 248764 kb
Host smart-75eecb7a-d623-4a38-9f1f-141d3deae0ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1856501453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1856501453
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2954367582
Short name T644
Test name
Test status
Simulation time 2487827267 ps
CPU time 34.22 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:15:10 PM PDT 24
Peak memory 256220 kb
Host smart-e9e42063-97c6-4b7a-96ed-7129de7c05e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29543
67582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2954367582
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1632032807
Short name T508
Test name
Test status
Simulation time 764194272 ps
CPU time 46.21 seconds
Started May 16 02:14:33 PM PDT 24
Finished May 16 02:15:21 PM PDT 24
Peak memory 255928 kb
Host smart-a3aed630-9e3c-41c6-8489-145ae2d84c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
32807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1632032807
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2522373482
Short name T111
Test name
Test status
Simulation time 52156436407 ps
CPU time 1469.69 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:39:06 PM PDT 24
Peak memory 271848 kb
Host smart-c7f609d0-f05f-4440-a1f9-201f20bc4540
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522373482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2522373482
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3814770441
Short name T601
Test name
Test status
Simulation time 57229662424 ps
CPU time 1303.5 seconds
Started May 16 02:14:35 PM PDT 24
Finished May 16 02:36:20 PM PDT 24
Peak memory 281604 kb
Host smart-d512a6ff-671c-4c8b-b0a1-456961b9b33d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814770441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3814770441
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1890931136
Short name T640
Test name
Test status
Simulation time 43387224357 ps
CPU time 473.03 seconds
Started May 16 02:14:36 PM PDT 24
Finished May 16 02:22:31 PM PDT 24
Peak memory 248080 kb
Host smart-dffa6e7a-b666-4601-8553-b7908e5c5cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890931136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1890931136
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2467377651
Short name T470
Test name
Test status
Simulation time 312651744 ps
CPU time 18.81 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:14:55 PM PDT 24
Peak memory 254848 kb
Host smart-acef557e-60f4-4519-80e4-188315a09064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673
77651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2467377651
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1902690371
Short name T312
Test name
Test status
Simulation time 333169606 ps
CPU time 27.66 seconds
Started May 16 02:14:33 PM PDT 24
Finished May 16 02:15:02 PM PDT 24
Peak memory 247384 kb
Host smart-66d72e73-9a58-464f-b63d-9f0daff9dd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
90371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1902690371
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2310747895
Short name T35
Test name
Test status
Simulation time 1051245683 ps
CPU time 12.27 seconds
Started May 16 02:14:35 PM PDT 24
Finished May 16 02:14:49 PM PDT 24
Peak memory 277956 kb
Host smart-be141ce0-bad2-4d4a-bed5-a68eac4e83a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2310747895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2310747895
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2203163334
Short name T534
Test name
Test status
Simulation time 1018138554 ps
CPU time 51.46 seconds
Started May 16 02:14:33 PM PDT 24
Finished May 16 02:15:25 PM PDT 24
Peak memory 248700 kb
Host smart-f6350c86-46ab-4e36-8cc8-69a059524584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
63334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2203163334
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2917354916
Short name T633
Test name
Test status
Simulation time 403163256 ps
CPU time 23.58 seconds
Started May 16 02:14:24 PM PDT 24
Finished May 16 02:14:49 PM PDT 24
Peak memory 255712 kb
Host smart-2486970d-f4e6-4a4e-8080-ef34984fb290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
54916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2917354916
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2833940723
Short name T48
Test name
Test status
Simulation time 5619738696 ps
CPU time 293.98 seconds
Started May 16 02:14:36 PM PDT 24
Finished May 16 02:19:31 PM PDT 24
Peak memory 256936 kb
Host smart-5e61b824-8e21-412f-942c-59ee9db3e1d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833940723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2833940723
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1981225737
Short name T439
Test name
Test status
Simulation time 141057374415 ps
CPU time 1979.45 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:50:18 PM PDT 24
Peak memory 281616 kb
Host smart-a663c093-5970-4c9a-bc21-8bb108f0c01d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981225737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1981225737
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.110300349
Short name T700
Test name
Test status
Simulation time 14102199031 ps
CPU time 258.72 seconds
Started May 16 02:17:18 PM PDT 24
Finished May 16 02:21:38 PM PDT 24
Peak memory 256884 kb
Host smart-91f07ae7-ba73-4198-9708-6cfa8c9ed540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
0349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.110300349
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3507089279
Short name T678
Test name
Test status
Simulation time 2842814169 ps
CPU time 41.44 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 02:18:08 PM PDT 24
Peak memory 256100 kb
Host smart-e766993f-5fc7-4a8a-95a7-cf2c8d6e4c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35070
89279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3507089279
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3970442304
Short name T70
Test name
Test status
Simulation time 94185566097 ps
CPU time 2505.97 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:59:04 PM PDT 24
Peak memory 283564 kb
Host smart-86dd008f-fd1e-4b3a-ac0d-6706e18aef92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970442304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3970442304
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2715643336
Short name T564
Test name
Test status
Simulation time 21474704830 ps
CPU time 314.8 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:22:33 PM PDT 24
Peak memory 248312 kb
Host smart-244200f9-0a1b-4f20-80e4-9e8eeb6b924b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715643336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2715643336
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.806902669
Short name T32
Test name
Test status
Simulation time 216645719 ps
CPU time 9.7 seconds
Started May 16 02:17:19 PM PDT 24
Finished May 16 02:17:30 PM PDT 24
Peak memory 248704 kb
Host smart-4f43c3c8-e3a5-484a-8df2-c3156ee444a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80690
2669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.806902669
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.271491823
Short name T77
Test name
Test status
Simulation time 215545279 ps
CPU time 22.49 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:17:40 PM PDT 24
Peak memory 248744 kb
Host smart-600b007f-3384-4cee-8155-054101cfa4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27149
1823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.271491823
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1796383118
Short name T87
Test name
Test status
Simulation time 916648043 ps
CPU time 31.43 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:17:49 PM PDT 24
Peak memory 248572 kb
Host smart-175ffff9-33b4-4199-bbb0-62f81f10a5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
83118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1796383118
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.601061090
Short name T127
Test name
Test status
Simulation time 306380186 ps
CPU time 28.74 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:17:47 PM PDT 24
Peak memory 248708 kb
Host smart-389dbb04-a74f-424a-a673-af289c351cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60106
1090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.601061090
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2346285699
Short name T259
Test name
Test status
Simulation time 58168587305 ps
CPU time 3358.87 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 03:13:17 PM PDT 24
Peak memory 289608 kb
Host smart-3d333d6a-0c09-44fe-b3a5-d488a9d8a843
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346285699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2346285699
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.427671704
Short name T528
Test name
Test status
Simulation time 672678539132 ps
CPU time 6955.6 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 04:13:20 PM PDT 24
Peak memory 347212 kb
Host smart-04212aa5-c0cf-436f-84cc-d54a6fc45f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427671704 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.427671704
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.359920999
Short name T658
Test name
Test status
Simulation time 91829199592 ps
CPU time 2751.45 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 03:03:21 PM PDT 24
Peak memory 287060 kb
Host smart-fbb1b6a3-bc57-4498-9d31-5ae3917dd8c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359920999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.359920999
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2052816099
Short name T617
Test name
Test status
Simulation time 4758683772 ps
CPU time 173.67 seconds
Started May 16 02:17:21 PM PDT 24
Finished May 16 02:20:16 PM PDT 24
Peak memory 250204 kb
Host smart-4ec3dc1f-1936-49e2-82ff-c2ef3cc668da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
16099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2052816099
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.833189488
Short name T517
Test name
Test status
Simulation time 538927849 ps
CPU time 32.74 seconds
Started May 16 02:17:17 PM PDT 24
Finished May 16 02:17:52 PM PDT 24
Peak memory 248748 kb
Host smart-4537e933-6d8e-494c-89a7-23efdbabfc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83318
9488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.833189488
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1213560167
Short name T360
Test name
Test status
Simulation time 40852300488 ps
CPU time 1320.55 seconds
Started May 16 02:17:24 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 273320 kb
Host smart-7d63fd27-8dd0-40bc-89c9-355e78e8cddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213560167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1213560167
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3727925407
Short name T130
Test name
Test status
Simulation time 78869119332 ps
CPU time 638.78 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:28:07 PM PDT 24
Peak memory 265244 kb
Host smart-4e71e5b0-2187-4d39-9d1d-56b3ea448114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727925407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3727925407
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3407058216
Short name T711
Test name
Test status
Simulation time 50064099054 ps
CPU time 197.47 seconds
Started May 16 02:17:26 PM PDT 24
Finished May 16 02:20:45 PM PDT 24
Peak memory 247960 kb
Host smart-ffc9153b-e4cb-4d7c-abd6-963019010dac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407058216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3407058216
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2485440545
Short name T578
Test name
Test status
Simulation time 431189631 ps
CPU time 30.82 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 02:17:58 PM PDT 24
Peak memory 248732 kb
Host smart-6fdf4b8a-0f95-4930-9696-fa9b23aab4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24854
40545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2485440545
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2356899975
Short name T65
Test name
Test status
Simulation time 236275102 ps
CPU time 15.6 seconds
Started May 16 02:17:15 PM PDT 24
Finished May 16 02:17:32 PM PDT 24
Peak memory 248624 kb
Host smart-ab750d42-683d-4496-9ac9-9a25a4a0ee8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23568
99975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2356899975
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1575551742
Short name T506
Test name
Test status
Simulation time 301264966 ps
CPU time 8.5 seconds
Started May 16 02:17:16 PM PDT 24
Finished May 16 02:17:26 PM PDT 24
Peak memory 248748 kb
Host smart-99f2a888-e580-4e07-bd7c-0da08cf5bad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
51742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1575551742
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.833849907
Short name T375
Test name
Test status
Simulation time 627648754 ps
CPU time 15.19 seconds
Started May 16 02:17:15 PM PDT 24
Finished May 16 02:17:31 PM PDT 24
Peak memory 256352 kb
Host smart-491bf7d8-c681-4f47-9bca-93d84d40d2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83384
9907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.833849907
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1327676439
Short name T400
Test name
Test status
Simulation time 460813715 ps
CPU time 34.83 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 02:18:04 PM PDT 24
Peak memory 255484 kb
Host smart-5009d3cd-54d3-401a-bce8-e33f2d126600
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327676439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1327676439
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1931237641
Short name T59
Test name
Test status
Simulation time 21584744986 ps
CPU time 2876.74 seconds
Started May 16 02:17:29 PM PDT 24
Finished May 16 03:05:28 PM PDT 24
Peak memory 303200 kb
Host smart-5aa8551a-b542-4fa0-9c13-68a1f1eeee69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931237641 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1931237641
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3015785674
Short name T56
Test name
Test status
Simulation time 31958933785 ps
CPU time 925.44 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:32:54 PM PDT 24
Peak memory 273396 kb
Host smart-d742f1ed-c34b-47a8-b00f-76976fbdd6d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015785674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3015785674
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4054994098
Short name T713
Test name
Test status
Simulation time 7779013295 ps
CPU time 215.48 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 02:21:01 PM PDT 24
Peak memory 256940 kb
Host smart-b8c3eaeb-afd8-4c8c-8036-a1bdea3d2e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
94098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4054994098
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.432384019
Short name T381
Test name
Test status
Simulation time 2608302778 ps
CPU time 15.39 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:17:44 PM PDT 24
Peak memory 248736 kb
Host smart-c8cd4936-c55f-4e60-8a8f-c1221ae30b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43238
4019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.432384019
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2894213059
Short name T602
Test name
Test status
Simulation time 20206439886 ps
CPU time 1457.58 seconds
Started May 16 02:17:26 PM PDT 24
Finished May 16 02:41:45 PM PDT 24
Peak memory 288756 kb
Host smart-649b33eb-4347-4bf3-828e-3e08dd787dad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894213059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2894213059
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3832116622
Short name T682
Test name
Test status
Simulation time 18866066964 ps
CPU time 1539.48 seconds
Started May 16 02:17:31 PM PDT 24
Finished May 16 02:43:12 PM PDT 24
Peak memory 289128 kb
Host smart-ac864b1f-d813-452f-a819-6e285abedd3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832116622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3832116622
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1930258741
Short name T475
Test name
Test status
Simulation time 38159976027 ps
CPU time 376.57 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 02:23:46 PM PDT 24
Peak memory 248252 kb
Host smart-aca0ba75-99e3-4012-acc7-2d146cdb6cf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930258741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1930258741
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.526434644
Short name T486
Test name
Test status
Simulation time 550410003 ps
CPU time 28.83 seconds
Started May 16 02:17:26 PM PDT 24
Finished May 16 02:17:56 PM PDT 24
Peak memory 248748 kb
Host smart-2bdcade3-9324-4fe2-bddb-bdd392cb95b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52643
4644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.526434644
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2956833658
Short name T81
Test name
Test status
Simulation time 898438638 ps
CPU time 49.44 seconds
Started May 16 02:17:31 PM PDT 24
Finished May 16 02:18:22 PM PDT 24
Peak memory 255796 kb
Host smart-01df5cbe-c668-428b-bcc1-ade6e1b610b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568
33658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2956833658
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2478768161
Short name T458
Test name
Test status
Simulation time 55619902 ps
CPU time 4.64 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 02:17:33 PM PDT 24
Peak memory 240556 kb
Host smart-721c4cdd-ef7d-46d1-8e97-aacffe3ed013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24787
68161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2478768161
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.154482263
Short name T386
Test name
Test status
Simulation time 485373205 ps
CPU time 19.87 seconds
Started May 16 02:17:25 PM PDT 24
Finished May 16 02:17:46 PM PDT 24
Peak memory 248876 kb
Host smart-4d6522b6-cf13-45ce-ab65-67c08380b8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15448
2263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.154482263
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3347368444
Short name T478
Test name
Test status
Simulation time 133447627225 ps
CPU time 6865.84 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 04:11:56 PM PDT 24
Peak memory 368692 kb
Host smart-7a1272a1-a05a-42bb-91b0-b04dfdb447e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347368444 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3347368444
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.141934580
Short name T477
Test name
Test status
Simulation time 11356039858 ps
CPU time 141.53 seconds
Started May 16 02:17:37 PM PDT 24
Finished May 16 02:20:01 PM PDT 24
Peak memory 256916 kb
Host smart-726dfdde-824a-40e8-a1f0-74b12d353da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14193
4580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.141934580
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2540413736
Short name T515
Test name
Test status
Simulation time 2843613033 ps
CPU time 60.33 seconds
Started May 16 02:17:38 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 256980 kb
Host smart-9fe98e7b-aeaf-42d4-af35-5119b113b967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
13736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2540413736
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3515834217
Short name T610
Test name
Test status
Simulation time 112145556687 ps
CPU time 1603.77 seconds
Started May 16 02:17:42 PM PDT 24
Finished May 16 02:44:27 PM PDT 24
Peak memory 273348 kb
Host smart-74d7e6d4-5341-4210-ba6d-4c66d85965c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515834217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3515834217
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2966304334
Short name T76
Test name
Test status
Simulation time 71752385270 ps
CPU time 1574.76 seconds
Started May 16 02:17:40 PM PDT 24
Finished May 16 02:43:56 PM PDT 24
Peak memory 287572 kb
Host smart-3969e6a6-9076-4ea3-bd54-acdcbe8a9e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966304334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2966304334
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3536850609
Short name T583
Test name
Test status
Simulation time 1139182578 ps
CPU time 18.43 seconds
Started May 16 02:17:27 PM PDT 24
Finished May 16 02:17:47 PM PDT 24
Peak memory 248704 kb
Host smart-a0563898-faa8-4539-b15e-03abc201e83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35368
50609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3536850609
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1773872094
Short name T383
Test name
Test status
Simulation time 862428426 ps
CPU time 56.09 seconds
Started May 16 02:17:39 PM PDT 24
Finished May 16 02:18:37 PM PDT 24
Peak memory 255416 kb
Host smart-880e20b3-3009-4f6e-9ddf-6897b115d91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17738
72094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1773872094
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1217316369
Short name T444
Test name
Test status
Simulation time 105045186 ps
CPU time 6.67 seconds
Started May 16 02:17:38 PM PDT 24
Finished May 16 02:17:46 PM PDT 24
Peak memory 250888 kb
Host smart-c48ff9c3-145a-484b-b59a-f2092f36f191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173
16369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1217316369
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.761816434
Short name T574
Test name
Test status
Simulation time 588828423 ps
CPU time 15.02 seconds
Started May 16 02:17:28 PM PDT 24
Finished May 16 02:17:44 PM PDT 24
Peak memory 256260 kb
Host smart-9f9d60fd-3b01-4056-adb8-da6f556bd716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76181
6434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.761816434
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2686175435
Short name T278
Test name
Test status
Simulation time 69755807927 ps
CPU time 4168.78 seconds
Started May 16 02:17:40 PM PDT 24
Finished May 16 03:27:11 PM PDT 24
Peak memory 297884 kb
Host smart-186852b8-608f-40e9-9b4f-57fea6043760
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686175435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2686175435
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.512064573
Short name T148
Test name
Test status
Simulation time 10842304215 ps
CPU time 1075.23 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:35:43 PM PDT 24
Peak memory 270572 kb
Host smart-fe634307-db8f-4169-8d93-43d64b1804ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512064573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.512064573
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.648014468
Short name T388
Test name
Test status
Simulation time 546770377 ps
CPU time 51.76 seconds
Started May 16 02:17:46 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 256880 kb
Host smart-5753f011-958b-4107-9794-b3633e5e4188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64801
4468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.648014468
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3578726590
Short name T491
Test name
Test status
Simulation time 313508677 ps
CPU time 17.64 seconds
Started May 16 02:17:37 PM PDT 24
Finished May 16 02:17:57 PM PDT 24
Peak memory 248728 kb
Host smart-3f57837a-0786-423e-a131-312374313f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35787
26590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3578726590
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4236192097
Short name T546
Test name
Test status
Simulation time 54480076136 ps
CPU time 1404.8 seconds
Started May 16 02:17:47 PM PDT 24
Finished May 16 02:41:14 PM PDT 24
Peak memory 281600 kb
Host smart-6cc477c4-21f2-42d1-a14e-a82d7770a871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236192097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4236192097
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.404985432
Short name T338
Test name
Test status
Simulation time 7560873017 ps
CPU time 317.41 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:23:04 PM PDT 24
Peak memory 247024 kb
Host smart-1eb872ce-d93f-4210-95ec-4b23e2bef1e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404985432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.404985432
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3340273413
Short name T255
Test name
Test status
Simulation time 1597594973 ps
CPU time 46.47 seconds
Started May 16 02:17:40 PM PDT 24
Finished May 16 02:18:28 PM PDT 24
Peak memory 256196 kb
Host smart-078e2d7a-32d7-4d70-ad5c-dedd020ebe12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33402
73413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3340273413
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2134559929
Short name T119
Test name
Test status
Simulation time 1636561042 ps
CPU time 32.56 seconds
Started May 16 02:17:37 PM PDT 24
Finished May 16 02:18:12 PM PDT 24
Peak memory 249192 kb
Host smart-9c15a416-9e6a-4ced-8cdd-5b602b646216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
59929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2134559929
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2024978377
Short name T279
Test name
Test status
Simulation time 273695969 ps
CPU time 15.68 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:18:03 PM PDT 24
Peak memory 255380 kb
Host smart-1a46ea88-5874-43d2-ac52-d42b8444fd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20249
78377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2024978377
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3638339356
Short name T415
Test name
Test status
Simulation time 1323819153 ps
CPU time 40.87 seconds
Started May 16 02:17:38 PM PDT 24
Finished May 16 02:18:20 PM PDT 24
Peak memory 248784 kb
Host smart-fe19b26a-4295-48c8-9fa9-e88cccb7f443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
39356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3638339356
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2440974012
Short name T17
Test name
Test status
Simulation time 146629206450 ps
CPU time 2452.97 seconds
Started May 16 02:17:46 PM PDT 24
Finished May 16 02:58:41 PM PDT 24
Peak memory 283068 kb
Host smart-af06c7c0-1df4-475b-bc22-8b948720145f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440974012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2440974012
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3025974068
Short name T299
Test name
Test status
Simulation time 18220264884 ps
CPU time 955.75 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:33:44 PM PDT 24
Peak memory 272780 kb
Host smart-fdc6f552-4daa-4842-adaa-65d1d5256bcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025974068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3025974068
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1739737813
Short name T590
Test name
Test status
Simulation time 1543525062 ps
CPU time 120.66 seconds
Started May 16 02:17:47 PM PDT 24
Finished May 16 02:19:50 PM PDT 24
Peak memory 250792 kb
Host smart-8a7f3ca8-d177-4d33-bd10-edfbd2881ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397
37813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1739737813
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1792279847
Short name T113
Test name
Test status
Simulation time 2281867759 ps
CPU time 32.93 seconds
Started May 16 02:17:46 PM PDT 24
Finished May 16 02:18:22 PM PDT 24
Peak memory 256928 kb
Host smart-0b7ac68b-115b-44d7-ae30-8b7e66db2c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17922
79847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1792279847
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3986729616
Short name T671
Test name
Test status
Simulation time 171576692772 ps
CPU time 2571.82 seconds
Started May 16 02:17:48 PM PDT 24
Finished May 16 03:00:42 PM PDT 24
Peak memory 289036 kb
Host smart-4271cef7-aa33-4c58-a0de-8d05a3021552
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986729616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3986729616
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2587612360
Short name T23
Test name
Test status
Simulation time 47772504435 ps
CPU time 2754.75 seconds
Started May 16 02:17:46 PM PDT 24
Finished May 16 03:03:43 PM PDT 24
Peak memory 288764 kb
Host smart-abb83b53-2a98-4293-a983-21d624348065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587612360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2587612360
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2919717603
Short name T211
Test name
Test status
Simulation time 22934014295 ps
CPU time 489.56 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:25:58 PM PDT 24
Peak memory 248056 kb
Host smart-52fce045-0540-41c4-8dc6-317f815c845d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919717603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2919717603
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2105441071
Short name T510
Test name
Test status
Simulation time 597529363 ps
CPU time 11.47 seconds
Started May 16 02:17:48 PM PDT 24
Finished May 16 02:18:02 PM PDT 24
Peak memory 254372 kb
Host smart-7eb0edc2-74a2-475b-ac2a-3458c04e59d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21054
41071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2105441071
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.182459241
Short name T411
Test name
Test status
Simulation time 53458618 ps
CPU time 4.6 seconds
Started May 16 02:17:46 PM PDT 24
Finished May 16 02:17:53 PM PDT 24
Peak memory 239236 kb
Host smart-5ef0d669-cfd2-453e-acc7-f15f4c04bc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18245
9241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.182459241
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3118194703
Short name T661
Test name
Test status
Simulation time 350908595 ps
CPU time 22.14 seconds
Started May 16 02:17:48 PM PDT 24
Finished May 16 02:18:12 PM PDT 24
Peak memory 255888 kb
Host smart-5dff2c01-7e7e-45dd-857a-5c8c8b628b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31181
94703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3118194703
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2744330129
Short name T428
Test name
Test status
Simulation time 2917143408 ps
CPU time 35.76 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:18:24 PM PDT 24
Peak memory 248780 kb
Host smart-72176d57-9213-4490-a111-7d7895e347ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27443
30129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2744330129
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2815156801
Short name T553
Test name
Test status
Simulation time 69122067622 ps
CPU time 1329.26 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 02:39:56 PM PDT 24
Peak memory 281584 kb
Host smart-31077a70-38f1-4bac-90d5-748316e3fc1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815156801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2815156801
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1508192162
Short name T72
Test name
Test status
Simulation time 182817766535 ps
CPU time 3646.86 seconds
Started May 16 02:17:45 PM PDT 24
Finished May 16 03:18:35 PM PDT 24
Peak memory 314476 kb
Host smart-77aad74c-4055-4fe5-bcb8-34d4c9cdd588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508192162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1508192162
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1438482378
Short name T695
Test name
Test status
Simulation time 27970589170 ps
CPU time 1668.16 seconds
Started May 16 02:17:54 PM PDT 24
Finished May 16 02:45:44 PM PDT 24
Peak memory 273352 kb
Host smart-b2ae941d-e74e-41d9-bb61-c1277e77ba85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438482378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1438482378
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2331220587
Short name T136
Test name
Test status
Simulation time 11346037528 ps
CPU time 339.08 seconds
Started May 16 02:17:55 PM PDT 24
Finished May 16 02:23:36 PM PDT 24
Peak memory 256912 kb
Host smart-ad6d8df6-974d-46f2-9647-2c3dae0b60c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23312
20587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2331220587
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2260212853
Short name T698
Test name
Test status
Simulation time 386222935 ps
CPU time 4.44 seconds
Started May 16 02:18:00 PM PDT 24
Finished May 16 02:18:06 PM PDT 24
Peak memory 252040 kb
Host smart-bd3be83a-6757-4af9-85aa-41c378db880f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
12853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2260212853
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4185845551
Short name T353
Test name
Test status
Simulation time 165854527943 ps
CPU time 2435.06 seconds
Started May 16 02:17:56 PM PDT 24
Finished May 16 02:58:32 PM PDT 24
Peak memory 289320 kb
Host smart-7751fc7d-8c5b-49f8-b0a8-decc5d72fd06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185845551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4185845551
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1492402237
Short name T656
Test name
Test status
Simulation time 91330206340 ps
CPU time 1353.15 seconds
Started May 16 02:18:00 PM PDT 24
Finished May 16 02:40:35 PM PDT 24
Peak memory 270612 kb
Host smart-6dd38b0e-9516-4b6d-92ed-59eccbf16f74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492402237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1492402237
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.331426927
Short name T340
Test name
Test status
Simulation time 3383235538 ps
CPU time 54.01 seconds
Started May 16 02:17:54 PM PDT 24
Finished May 16 02:18:50 PM PDT 24
Peak memory 248216 kb
Host smart-bf91c1b9-9f34-4979-9091-852445867768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331426927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.331426927
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.12012286
Short name T591
Test name
Test status
Simulation time 770228728 ps
CPU time 14.22 seconds
Started May 16 02:17:56 PM PDT 24
Finished May 16 02:18:12 PM PDT 24
Peak memory 248748 kb
Host smart-21bb0cea-1d02-4edc-b063-723f113a6f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012
286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.12012286
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2314551443
Short name T107
Test name
Test status
Simulation time 1472242900 ps
CPU time 12.58 seconds
Started May 16 02:17:53 PM PDT 24
Finished May 16 02:18:07 PM PDT 24
Peak memory 247316 kb
Host smart-1322fcc2-bdbc-4ffe-8b8e-805578d2f98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
51443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2314551443
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.711918588
Short name T40
Test name
Test status
Simulation time 108121081 ps
CPU time 14.28 seconds
Started May 16 02:17:57 PM PDT 24
Finished May 16 02:18:12 PM PDT 24
Peak memory 255836 kb
Host smart-2da504ac-2604-4f05-aa76-1b5f75640adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71191
8588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.711918588
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1533001657
Short name T95
Test name
Test status
Simulation time 242795073201 ps
CPU time 3924.65 seconds
Started May 16 02:18:01 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 299696 kb
Host smart-50b5d4e6-4d17-4e31-808f-715a4f198bc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533001657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1533001657
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3757718420
Short name T389
Test name
Test status
Simulation time 99529153563 ps
CPU time 1924.4 seconds
Started May 16 02:18:04 PM PDT 24
Finished May 16 02:50:10 PM PDT 24
Peak memory 281572 kb
Host smart-522c7427-eee4-4d00-911d-c3cded847333
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757718420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3757718420
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3740630558
Short name T556
Test name
Test status
Simulation time 5340016532 ps
CPU time 149.52 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 02:20:34 PM PDT 24
Peak memory 250184 kb
Host smart-169209a1-a00f-40b3-b8a6-b95e3e4b1caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37406
30558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3740630558
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.152406150
Short name T526
Test name
Test status
Simulation time 2392743423 ps
CPU time 30.5 seconds
Started May 16 02:17:55 PM PDT 24
Finished May 16 02:18:27 PM PDT 24
Peak memory 248808 kb
Host smart-fde79c4d-516f-4794-8e69-4eb275b51bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
6150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.152406150
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2870482395
Short name T503
Test name
Test status
Simulation time 36238964235 ps
CPU time 2111.04 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 02:53:16 PM PDT 24
Peak memory 288684 kb
Host smart-5820c699-71ef-4da0-b6c9-60e5e8eef43f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870482395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2870482395
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2794804476
Short name T330
Test name
Test status
Simulation time 5449020114 ps
CPU time 221.18 seconds
Started May 16 02:18:05 PM PDT 24
Finished May 16 02:21:48 PM PDT 24
Peak memory 254860 kb
Host smart-5897aaa1-483f-4f35-ab71-a8bedb4c3e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794804476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2794804476
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3955745848
Short name T561
Test name
Test status
Simulation time 508783466 ps
CPU time 26.71 seconds
Started May 16 02:17:56 PM PDT 24
Finished May 16 02:18:25 PM PDT 24
Peak memory 256920 kb
Host smart-406b69dd-ff6d-402f-acd5-fe31c5cf4b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39557
45848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3955745848
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.866103151
Short name T614
Test name
Test status
Simulation time 553959278 ps
CPU time 25.92 seconds
Started May 16 02:17:56 PM PDT 24
Finished May 16 02:18:24 PM PDT 24
Peak memory 255180 kb
Host smart-fbf14da4-1062-46bc-94a8-a0cf6577b08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86610
3151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.866103151
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2021259748
Short name T433
Test name
Test status
Simulation time 223851720 ps
CPU time 22.36 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 02:18:27 PM PDT 24
Peak memory 254732 kb
Host smart-9e4794e6-2cf0-40de-8a86-fea590b6a21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20212
59748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2021259748
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.526306779
Short name T479
Test name
Test status
Simulation time 2483798079 ps
CPU time 38.43 seconds
Started May 16 02:18:01 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 248752 kb
Host smart-a441fa1c-ee2f-447e-8d95-430fa36eccc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52630
6779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.526306779
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.787545205
Short name T118
Test name
Test status
Simulation time 84912732839 ps
CPU time 2728.52 seconds
Started May 16 02:18:04 PM PDT 24
Finished May 16 03:03:34 PM PDT 24
Peak memory 289380 kb
Host smart-b7f0b139-8870-47da-b1fb-b4536996412a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787545205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.787545205
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.981581147
Short name T531
Test name
Test status
Simulation time 33546083261 ps
CPU time 900.55 seconds
Started May 16 02:18:22 PM PDT 24
Finished May 16 02:33:24 PM PDT 24
Peak memory 281608 kb
Host smart-abef4bb2-2f2a-467e-9a4f-a40fe7d52ab3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981581147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.981581147
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1240111571
Short name T569
Test name
Test status
Simulation time 8923768582 ps
CPU time 202.09 seconds
Started May 16 02:18:04 PM PDT 24
Finished May 16 02:21:28 PM PDT 24
Peak memory 256392 kb
Host smart-d18d90eb-52ed-4ce7-8db0-6f8ac2e93474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
11571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1240111571
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2497458861
Short name T254
Test name
Test status
Simulation time 760903630 ps
CPU time 18.65 seconds
Started May 16 02:18:03 PM PDT 24
Finished May 16 02:18:24 PM PDT 24
Peak memory 248736 kb
Host smart-5e7dfdf6-522e-4773-834a-632dad6b9256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24974
58861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2497458861
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.19944280
Short name T349
Test name
Test status
Simulation time 61410538580 ps
CPU time 1863.49 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:49:26 PM PDT 24
Peak memory 289028 kb
Host smart-fff6d337-0fb6-4c2c-9640-dc48f1a0a477
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19944280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.19944280
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4033260033
Short name T587
Test name
Test status
Simulation time 53263100965 ps
CPU time 1594.03 seconds
Started May 16 02:18:22 PM PDT 24
Finished May 16 02:44:58 PM PDT 24
Peak memory 289208 kb
Host smart-fe6f4407-d4a8-43a2-8ff1-2b80699deae4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033260033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4033260033
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1916876311
Short name T105
Test name
Test status
Simulation time 8796962277 ps
CPU time 321 seconds
Started May 16 02:18:22 PM PDT 24
Finished May 16 02:23:45 PM PDT 24
Peak memory 247884 kb
Host smart-ca01ce84-c237-4aab-b6da-a673090468ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916876311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1916876311
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.84904177
Short name T566
Test name
Test status
Simulation time 3409728415 ps
CPU time 51.29 seconds
Started May 16 02:18:02 PM PDT 24
Finished May 16 02:18:55 PM PDT 24
Peak memory 248752 kb
Host smart-e18882d9-c8c8-4f9e-aa2f-b77568ca753d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84904
177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.84904177
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3757285796
Short name T342
Test name
Test status
Simulation time 772945984 ps
CPU time 10.86 seconds
Started May 16 02:18:04 PM PDT 24
Finished May 16 02:18:16 PM PDT 24
Peak memory 252732 kb
Host smart-7afe1519-9247-4d6b-b660-90a32cc6a3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37572
85796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3757285796
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.409024993
Short name T673
Test name
Test status
Simulation time 725072852 ps
CPU time 51.44 seconds
Started May 16 02:18:06 PM PDT 24
Finished May 16 02:18:59 PM PDT 24
Peak memory 256896 kb
Host smart-c1cf1f07-e07d-46af-bfa1-7c31d7e426ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40902
4993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.409024993
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3461920077
Short name T282
Test name
Test status
Simulation time 144878418288 ps
CPU time 1831.73 seconds
Started May 16 02:18:22 PM PDT 24
Finished May 16 02:48:56 PM PDT 24
Peak memory 285288 kb
Host smart-6de4b6f8-6a60-4f8a-a3a4-9aacc910cd95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461920077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3461920077
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2345769889
Short name T392
Test name
Test status
Simulation time 7970664061 ps
CPU time 788.94 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:31:32 PM PDT 24
Peak memory 273376 kb
Host smart-4cfec999-b483-4bc8-9904-3b008f66abd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345769889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2345769889
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2588458053
Short name T385
Test name
Test status
Simulation time 3865575377 ps
CPU time 210.91 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:21:54 PM PDT 24
Peak memory 256920 kb
Host smart-b10b1952-9b52-47cb-ae23-06509ddbf24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
58053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2588458053
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.557684302
Short name T631
Test name
Test status
Simulation time 1081092709 ps
CPU time 66.9 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:19:30 PM PDT 24
Peak memory 255884 kb
Host smart-948aea51-4d79-4af6-8ca0-a3483e2d0e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55768
4302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.557684302
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.786786800
Short name T21
Test name
Test status
Simulation time 54326979062 ps
CPU time 2783.08 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 03:04:46 PM PDT 24
Peak memory 281528 kb
Host smart-0a21b68a-f116-4647-a786-f01b64d45beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786786800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.786786800
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2333864076
Short name T694
Test name
Test status
Simulation time 56723929478 ps
CPU time 3186.78 seconds
Started May 16 02:18:20 PM PDT 24
Finished May 16 03:11:28 PM PDT 24
Peak memory 289724 kb
Host smart-dd7d70e0-c4d6-4707-a0a3-8a877aa3ecf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333864076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2333864076
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3485872807
Short name T629
Test name
Test status
Simulation time 15919454031 ps
CPU time 174.5 seconds
Started May 16 02:18:23 PM PDT 24
Finished May 16 02:21:19 PM PDT 24
Peak memory 248088 kb
Host smart-f5088e5a-11d5-49aa-811b-c4dddaa634a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485872807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3485872807
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1293226670
Short name T651
Test name
Test status
Simulation time 204586446 ps
CPU time 21.05 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:18:44 PM PDT 24
Peak memory 248676 kb
Host smart-03feb74e-b133-445e-a528-beb6faf28d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
26670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1293226670
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3767126774
Short name T683
Test name
Test status
Simulation time 759315756 ps
CPU time 28.47 seconds
Started May 16 02:18:23 PM PDT 24
Finished May 16 02:18:53 PM PDT 24
Peak memory 248748 kb
Host smart-5f670aaa-cc11-4d46-a976-f0a353d361e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
26774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3767126774
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3118954163
Short name T286
Test name
Test status
Simulation time 748342464 ps
CPU time 56.04 seconds
Started May 16 02:18:25 PM PDT 24
Finished May 16 02:19:22 PM PDT 24
Peak memory 247420 kb
Host smart-d86377ba-5562-44d7-bbf4-a21300f9d4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
54163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3118954163
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3827919608
Short name T549
Test name
Test status
Simulation time 1175680810 ps
CPU time 19.63 seconds
Started May 16 02:18:21 PM PDT 24
Finished May 16 02:18:43 PM PDT 24
Peak memory 248948 kb
Host smart-74278e9d-1c71-42bb-b050-ac7eae13dfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
19608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3827919608
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1459355275
Short name T106
Test name
Test status
Simulation time 1755356468 ps
CPU time 38.43 seconds
Started May 16 02:18:20 PM PDT 24
Finished May 16 02:18:59 PM PDT 24
Peak memory 248832 kb
Host smart-e5d6b1a1-298a-4cc6-a87c-302aca0b68a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459355275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1459355275
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1356874118
Short name T648
Test name
Test status
Simulation time 1812364194 ps
CPU time 149.23 seconds
Started May 16 02:18:20 PM PDT 24
Finished May 16 02:20:50 PM PDT 24
Peak memory 265220 kb
Host smart-a7888b2a-b717-4a7d-991b-f80589b6afd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356874118 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1356874118
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.391999568
Short name T240
Test name
Test status
Simulation time 36672877 ps
CPU time 3.13 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:14:51 PM PDT 24
Peak memory 248900 kb
Host smart-dcd3277e-c101-4a7a-bbbb-da13fa66ee14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=391999568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.391999568
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3157710741
Short name T423
Test name
Test status
Simulation time 8496747871 ps
CPU time 646.34 seconds
Started May 16 02:14:36 PM PDT 24
Finished May 16 02:25:23 PM PDT 24
Peak memory 265428 kb
Host smart-a100d76c-6a2e-4648-8454-775184e0002a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157710741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3157710741
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1635987935
Short name T413
Test name
Test status
Simulation time 331759042 ps
CPU time 14.77 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:15:02 PM PDT 24
Peak memory 248740 kb
Host smart-8847b3b9-9e98-4089-bf33-26c85e7289b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635987935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1635987935
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.146823121
Short name T45
Test name
Test status
Simulation time 5301325997 ps
CPU time 133.38 seconds
Started May 16 02:14:33 PM PDT 24
Finished May 16 02:16:48 PM PDT 24
Peak memory 256936 kb
Host smart-b2b7a24c-c855-4c6d-a55c-cd6507cc36ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
3121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.146823121
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4275093489
Short name T391
Test name
Test status
Simulation time 3716606314 ps
CPU time 57.15 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:15:33 PM PDT 24
Peak memory 256244 kb
Host smart-4a381eb4-65ef-4bb8-8d40-b29d20a556b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
93489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4275093489
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.404572177
Short name T335
Test name
Test status
Simulation time 18160443070 ps
CPU time 1363.48 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:37:32 PM PDT 24
Peak memory 288896 kb
Host smart-00486eb1-1895-401b-aeb5-c8f1dd710741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404572177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.404572177
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1132145301
Short name T409
Test name
Test status
Simulation time 132337503128 ps
CPU time 1524.42 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:40:13 PM PDT 24
Peak memory 265428 kb
Host smart-c5d48fc4-cce6-43a4-af0d-254a694edd16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132145301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1132145301
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3216147938
Short name T323
Test name
Test status
Simulation time 12999261443 ps
CPU time 327.61 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:20:03 PM PDT 24
Peak memory 248008 kb
Host smart-86ad4001-da49-4ce4-9a65-3a42f0dbaa2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216147938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3216147938
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1207744601
Short name T306
Test name
Test status
Simulation time 1141541747 ps
CPU time 26.93 seconds
Started May 16 02:14:36 PM PDT 24
Finished May 16 02:15:04 PM PDT 24
Peak memory 248664 kb
Host smart-549c68a4-a073-4afc-a169-71b5d93c32cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
44601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1207744601
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.828075453
Short name T102
Test name
Test status
Simulation time 1063273920 ps
CPU time 14.29 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:14:50 PM PDT 24
Peak memory 255564 kb
Host smart-60e09475-d411-4dac-b0e1-6e60a1a6a5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82807
5453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.828075453
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1582601323
Short name T9
Test name
Test status
Simulation time 252142363 ps
CPU time 14.38 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:15:02 PM PDT 24
Peak memory 270304 kb
Host smart-5f0fc473-91c8-46f7-90c7-387cfa1df12d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1582601323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1582601323
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.178437306
Short name T288
Test name
Test status
Simulation time 2309111038 ps
CPU time 35.86 seconds
Started May 16 02:14:36 PM PDT 24
Finished May 16 02:15:13 PM PDT 24
Peak memory 255540 kb
Host smart-d23b333a-2196-423b-ab9c-179ad3ad144f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
7306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.178437306
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2049429394
Short name T24
Test name
Test status
Simulation time 6683476220 ps
CPU time 73.4 seconds
Started May 16 02:14:34 PM PDT 24
Finished May 16 02:15:49 PM PDT 24
Peak memory 249188 kb
Host smart-ca31a267-0753-4bb0-87e0-bb054493059d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494
29394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2049429394
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2519024780
Short name T613
Test name
Test status
Simulation time 76257697984 ps
CPU time 3512.73 seconds
Started May 16 02:14:45 PM PDT 24
Finished May 16 03:13:20 PM PDT 24
Peak memory 338288 kb
Host smart-7a456e14-02b3-4aa9-8b47-331afc991a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519024780 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2519024780
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.877512051
Short name T382
Test name
Test status
Simulation time 138526025061 ps
CPU time 910.39 seconds
Started May 16 02:18:30 PM PDT 24
Finished May 16 02:33:43 PM PDT 24
Peak memory 272116 kb
Host smart-10a7d777-52ef-43fb-bb43-f39d195b4df3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877512051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.877512051
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2157208623
Short name T12
Test name
Test status
Simulation time 2555730532 ps
CPU time 55.52 seconds
Started May 16 02:18:34 PM PDT 24
Finished May 16 02:19:32 PM PDT 24
Peak memory 256916 kb
Host smart-62d9619e-40da-463c-a3c7-90cc54aea4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21572
08623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2157208623
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.458058600
Short name T84
Test name
Test status
Simulation time 60391774 ps
CPU time 2.87 seconds
Started May 16 02:18:34 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 240552 kb
Host smart-181e8346-0c3b-47f4-8b4e-8c3ffae8461b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45805
8600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.458058600
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3602382883
Short name T344
Test name
Test status
Simulation time 54966853265 ps
CPU time 1779.57 seconds
Started May 16 02:18:32 PM PDT 24
Finished May 16 02:48:15 PM PDT 24
Peak memory 289440 kb
Host smart-296c5a69-9631-4471-838b-2deadd8dd908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602382883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3602382883
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.197967093
Short name T131
Test name
Test status
Simulation time 30648699861 ps
CPU time 2191.38 seconds
Started May 16 02:18:33 PM PDT 24
Finished May 16 02:55:07 PM PDT 24
Peak memory 281600 kb
Host smart-25eccaa5-30ff-4d68-a94f-327536c6bfee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197967093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.197967093
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.131461821
Short name T498
Test name
Test status
Simulation time 6203461832 ps
CPU time 125.24 seconds
Started May 16 02:18:33 PM PDT 24
Finished May 16 02:20:40 PM PDT 24
Peak memory 248240 kb
Host smart-1c0359a7-e758-4b63-8fa9-0b763379377c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131461821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.131461821
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3219390070
Short name T454
Test name
Test status
Simulation time 39996203 ps
CPU time 4.74 seconds
Started May 16 02:18:32 PM PDT 24
Finished May 16 02:18:39 PM PDT 24
Peak memory 248756 kb
Host smart-a0b9c9e7-00cb-4e89-acaf-347a4916a796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
90070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3219390070
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.163171557
Short name T109
Test name
Test status
Simulation time 2766403055 ps
CPU time 39.79 seconds
Started May 16 02:18:32 PM PDT 24
Finished May 16 02:19:13 PM PDT 24
Peak memory 255524 kb
Host smart-af4a1e87-1793-40ce-b121-dc1b8c658722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
1557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.163171557
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1368760574
Short name T314
Test name
Test status
Simulation time 2942189962 ps
CPU time 24.69 seconds
Started May 16 02:18:31 PM PDT 24
Finished May 16 02:18:58 PM PDT 24
Peak memory 247444 kb
Host smart-74ccb55b-f83b-49df-9e05-9474703dd9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687
60574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1368760574
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.114859970
Short name T313
Test name
Test status
Simulation time 835470086 ps
CPU time 27.75 seconds
Started May 16 02:18:33 PM PDT 24
Finished May 16 02:19:04 PM PDT 24
Peak memory 248732 kb
Host smart-82ca1e23-c0f5-4509-8399-39be3b093955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11485
9970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.114859970
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2458514151
Short name T667
Test name
Test status
Simulation time 9816633744 ps
CPU time 908.24 seconds
Started May 16 02:18:33 PM PDT 24
Finished May 16 02:33:44 PM PDT 24
Peak memory 272444 kb
Host smart-482e6b54-8b8e-43fd-af76-748fee40c636
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458514151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2458514151
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4107057016
Short name T218
Test name
Test status
Simulation time 44485135140 ps
CPU time 2476.01 seconds
Started May 16 02:18:33 PM PDT 24
Finished May 16 02:59:53 PM PDT 24
Peak memory 305296 kb
Host smart-b2d0c5b3-e025-44d1-817f-383fa26f4546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107057016 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4107057016
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.261777488
Short name T572
Test name
Test status
Simulation time 4396035414 ps
CPU time 112.51 seconds
Started May 16 02:18:34 PM PDT 24
Finished May 16 02:20:30 PM PDT 24
Peak memory 256840 kb
Host smart-cf70c4f3-4b5b-4834-b977-7c34ea29a269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26177
7488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.261777488
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2129135507
Short name T447
Test name
Test status
Simulation time 441492079 ps
CPU time 22.73 seconds
Started May 16 02:18:32 PM PDT 24
Finished May 16 02:18:57 PM PDT 24
Peak memory 249088 kb
Host smart-38c9c0b0-cfe0-4663-9a91-0071eba63b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291
35507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2129135507
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1547994253
Short name T710
Test name
Test status
Simulation time 41429448687 ps
CPU time 899.81 seconds
Started May 16 02:18:44 PM PDT 24
Finished May 16 02:33:45 PM PDT 24
Peak memory 267192 kb
Host smart-e846c1d9-a19d-48e8-8826-be3ad6a9875d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547994253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1547994253
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1828553000
Short name T132
Test name
Test status
Simulation time 48949450949 ps
CPU time 1037.09 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:36:01 PM PDT 24
Peak memory 272812 kb
Host smart-85f3f845-bfdd-4179-80cb-c69a78b07a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828553000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1828553000
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.907296628
Short name T533
Test name
Test status
Simulation time 11471089816 ps
CPU time 131.83 seconds
Started May 16 02:18:31 PM PDT 24
Finished May 16 02:20:45 PM PDT 24
Peak memory 248320 kb
Host smart-97f31fba-32e4-4f5d-be8f-d9f69900b1b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907296628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.907296628
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1769298397
Short name T448
Test name
Test status
Simulation time 532011181 ps
CPU time 11.19 seconds
Started May 16 02:18:34 PM PDT 24
Finished May 16 02:18:48 PM PDT 24
Peak memory 249028 kb
Host smart-da1934d1-9034-4b04-af64-13a99ae0a2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
98397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1769298397
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2499807941
Short name T573
Test name
Test status
Simulation time 540374949 ps
CPU time 11.61 seconds
Started May 16 02:18:30 PM PDT 24
Finished May 16 02:18:43 PM PDT 24
Peak memory 248732 kb
Host smart-7eb85ffc-7047-4114-8d5f-86f69da116ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998
07941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2499807941
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.355902325
Short name T596
Test name
Test status
Simulation time 438931743 ps
CPU time 13.38 seconds
Started May 16 02:18:30 PM PDT 24
Finished May 16 02:18:45 PM PDT 24
Peak memory 254764 kb
Host smart-3c3f6981-b57b-4d06-a462-3bd235fbb7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35590
2325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.355902325
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2262197460
Short name T704
Test name
Test status
Simulation time 157748219 ps
CPU time 11.52 seconds
Started May 16 02:18:31 PM PDT 24
Finished May 16 02:18:44 PM PDT 24
Peak memory 248720 kb
Host smart-bf3e72f2-f4a1-4db2-9671-474a2b64b414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22621
97460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2262197460
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1548758561
Short name T550
Test name
Test status
Simulation time 224986846173 ps
CPU time 6282.78 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 04:03:27 PM PDT 24
Peak memory 354708 kb
Host smart-15c4e211-e4d0-42ba-a187-2a8dd2b0bae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548758561 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1548758561
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.889830171
Short name T25
Test name
Test status
Simulation time 294932194 ps
CPU time 8.75 seconds
Started May 16 02:18:44 PM PDT 24
Finished May 16 02:18:54 PM PDT 24
Peak memory 253008 kb
Host smart-10353ed7-2afa-4965-b5c9-d9383d712ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88983
0171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.889830171
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.805420082
Short name T418
Test name
Test status
Simulation time 614287599 ps
CPU time 11.98 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:18:55 PM PDT 24
Peak memory 248632 kb
Host smart-27914b97-1f6c-4243-94be-69ef7f19f769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80542
0082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.805420082
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.90173452
Short name T117
Test name
Test status
Simulation time 113265789930 ps
CPU time 2022.31 seconds
Started May 16 02:18:42 PM PDT 24
Finished May 16 02:52:26 PM PDT 24
Peak memory 282464 kb
Host smart-52fc7c2e-6ff5-49bf-baff-603b322b3046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90173452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.90173452
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3370227772
Short name T387
Test name
Test status
Simulation time 57178311799 ps
CPU time 1729.95 seconds
Started May 16 02:18:42 PM PDT 24
Finished May 16 02:47:34 PM PDT 24
Peak memory 273352 kb
Host smart-f8047872-21da-4b88-ac52-282713e8803e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370227772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3370227772
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2754511132
Short name T492
Test name
Test status
Simulation time 145789657 ps
CPU time 11.62 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:18:54 PM PDT 24
Peak memory 248628 kb
Host smart-a6f10322-7f1f-4cd2-a6a2-5907d389284f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27545
11132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2754511132
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2186733419
Short name T135
Test name
Test status
Simulation time 1477963632 ps
CPU time 27.06 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:19:10 PM PDT 24
Peak memory 255488 kb
Host smart-171811c4-538d-4c80-97e9-d64a40793d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
33419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2186733419
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1505623755
Short name T575
Test name
Test status
Simulation time 281380692 ps
CPU time 22.11 seconds
Started May 16 02:18:42 PM PDT 24
Finished May 16 02:19:06 PM PDT 24
Peak memory 255132 kb
Host smart-272f4a7f-f6ad-41f6-8ad2-b360a169a9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15056
23755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1505623755
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.692263958
Short name T67
Test name
Test status
Simulation time 3586813534 ps
CPU time 60.25 seconds
Started May 16 02:18:43 PM PDT 24
Finished May 16 02:19:45 PM PDT 24
Peak memory 248788 kb
Host smart-4c0e30d9-1a5b-4c44-832e-6dc7e6576279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69226
3958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.692263958
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.511460498
Short name T108
Test name
Test status
Simulation time 841930601 ps
CPU time 20.09 seconds
Started May 16 02:18:41 PM PDT 24
Finished May 16 02:19:02 PM PDT 24
Peak memory 248728 kb
Host smart-cfe0e7b3-81a9-4438-941b-7389992c373c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511460498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.511460498
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4189306216
Short name T634
Test name
Test status
Simulation time 141122479453 ps
CPU time 2527.35 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 03:01:02 PM PDT 24
Peak memory 289336 kb
Host smart-51938afa-6670-4769-8c9d-9749d2dae9a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189306216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4189306216
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1762848523
Short name T406
Test name
Test status
Simulation time 3050223072 ps
CPU time 133.45 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 02:21:09 PM PDT 24
Peak memory 256940 kb
Host smart-9b97493c-6c5a-46c4-8884-63de75f85153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
48523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1762848523
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2081050122
Short name T37
Test name
Test status
Simulation time 1538680338 ps
CPU time 47.22 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:41 PM PDT 24
Peak memory 248724 kb
Host smart-41a2ee3a-0e9d-422d-af8c-406da47e5526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
50122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2081050122
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1947910757
Short name T615
Test name
Test status
Simulation time 28208891693 ps
CPU time 1712.59 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 02:47:28 PM PDT 24
Peak memory 273348 kb
Host smart-64784dbb-3d2c-4605-b078-21d10af5d1cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947910757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1947910757
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.923837602
Short name T607
Test name
Test status
Simulation time 47020115604 ps
CPU time 2555.22 seconds
Started May 16 02:18:50 PM PDT 24
Finished May 16 03:01:27 PM PDT 24
Peak memory 288236 kb
Host smart-dc43128c-8eb5-4786-9c89-df20047a9334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923837602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.923837602
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.982844102
Short name T20
Test name
Test status
Simulation time 3233918997 ps
CPU time 131.22 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:21:05 PM PDT 24
Peak memory 248312 kb
Host smart-ce4c5418-b74b-4677-82d5-263476ea14d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982844102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.982844102
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.739566031
Short name T57
Test name
Test status
Simulation time 705690375 ps
CPU time 45.37 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:40 PM PDT 24
Peak memory 248736 kb
Host smart-0a352e67-a552-479e-9b1c-aae3a88768a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73956
6031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.739566031
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3385521458
Short name T467
Test name
Test status
Simulation time 178086203 ps
CPU time 17.82 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:12 PM PDT 24
Peak memory 255968 kb
Host smart-b0dd6141-4a7f-48b1-af75-96dbdedc098e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
21458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3385521458
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.422788931
Short name T404
Test name
Test status
Simulation time 450621960 ps
CPU time 35.79 seconds
Started May 16 02:18:53 PM PDT 24
Finished May 16 02:19:32 PM PDT 24
Peak memory 256424 kb
Host smart-2e837e36-4413-4015-a190-12a65ff500ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
8931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.422788931
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1562339753
Short name T663
Test name
Test status
Simulation time 245898096 ps
CPU time 14.27 seconds
Started May 16 02:18:45 PM PDT 24
Finished May 16 02:19:00 PM PDT 24
Peak memory 248676 kb
Host smart-49fea4ad-eb5a-4172-9f48-00de26f6934d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
39753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1562339753
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3020601495
Short name T210
Test name
Test status
Simulation time 32502822418 ps
CPU time 3499.82 seconds
Started May 16 02:18:49 PM PDT 24
Finished May 16 03:17:11 PM PDT 24
Peak memory 322660 kb
Host smart-eeae9ac8-e42c-425f-8624-0a9d3f3fdd02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020601495 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3020601495
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1138667305
Short name T619
Test name
Test status
Simulation time 26251818201 ps
CPU time 708.3 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 02:30:44 PM PDT 24
Peak memory 273316 kb
Host smart-0c5f3630-5261-42a5-89fa-b5cfab041642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138667305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1138667305
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.773632972
Short name T450
Test name
Test status
Simulation time 3710131473 ps
CPU time 117.67 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:20:52 PM PDT 24
Peak memory 256696 kb
Host smart-e85b0215-431d-4653-9b6a-f74ff1023245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77363
2972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.773632972
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3079657801
Short name T377
Test name
Test status
Simulation time 1500666461 ps
CPU time 42.28 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 02:19:37 PM PDT 24
Peak memory 248724 kb
Host smart-48a13098-9954-4ff4-a925-cfc5808f3747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
57801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3079657801
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1430506824
Short name T636
Test name
Test status
Simulation time 240534622999 ps
CPU time 2853.36 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 03:06:39 PM PDT 24
Peak memory 289208 kb
Host smart-99f046b9-7541-4404-8a73-4185c503fceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430506824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1430506824
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1249418704
Short name T435
Test name
Test status
Simulation time 159946697 ps
CPU time 12.96 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:07 PM PDT 24
Peak memory 248712 kb
Host smart-46be56bd-9e94-4928-ba7f-f9b3e00a0c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12494
18704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1249418704
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.516085109
Short name T51
Test name
Test status
Simulation time 1013673723 ps
CPU time 35.38 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:29 PM PDT 24
Peak memory 255916 kb
Host smart-14b06e91-ed20-4341-bdf2-5eb7a7b423b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51608
5109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.516085109
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1809256496
Short name T294
Test name
Test status
Simulation time 4433029679 ps
CPU time 33.6 seconds
Started May 16 02:18:52 PM PDT 24
Finished May 16 02:19:28 PM PDT 24
Peak memory 256056 kb
Host smart-8badd627-6bf5-4cc7-b304-da34e6887a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18092
56496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1809256496
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3475588266
Short name T618
Test name
Test status
Simulation time 854736625 ps
CPU time 20.57 seconds
Started May 16 02:18:51 PM PDT 24
Finished May 16 02:19:15 PM PDT 24
Peak memory 255896 kb
Host smart-76cc5416-44b9-440d-9b60-2d2174a0933c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34755
88266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3475588266
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3125275498
Short name T622
Test name
Test status
Simulation time 47797555059 ps
CPU time 3263.62 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 03:13:28 PM PDT 24
Peak memory 306140 kb
Host smart-726bcb56-cdfb-4a94-b50c-9cc2756bc293
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125275498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3125275498
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.212414627
Short name T264
Test name
Test status
Simulation time 93884402833 ps
CPU time 6009.38 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 03:59:14 PM PDT 24
Peak memory 321536 kb
Host smart-eb55e7fb-bb39-4263-9d55-4043f646ff57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212414627 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.212414627
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2314543411
Short name T571
Test name
Test status
Simulation time 29984330408 ps
CPU time 2030.85 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 02:52:57 PM PDT 24
Peak memory 289180 kb
Host smart-957dd261-e934-4e0f-9f6c-08d23a936f5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314543411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2314543411
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1666473497
Short name T677
Test name
Test status
Simulation time 4054447577 ps
CPU time 190.19 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 02:22:15 PM PDT 24
Peak memory 249888 kb
Host smart-4146aa6f-6e00-4a37-a76b-ce549d894e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
73497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1666473497
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3388652142
Short name T606
Test name
Test status
Simulation time 214121166 ps
CPU time 18.32 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:19:23 PM PDT 24
Peak memory 248804 kb
Host smart-ec8ba538-0631-4c0b-bb27-db30c5d05a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
52142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3388652142
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3023555605
Short name T356
Test name
Test status
Simulation time 65498754077 ps
CPU time 1940.26 seconds
Started May 16 02:19:04 PM PDT 24
Finished May 16 02:51:26 PM PDT 24
Peak memory 281284 kb
Host smart-d64c422f-ff59-422c-b7bf-692dd858d032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023555605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3023555605
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2408554511
Short name T654
Test name
Test status
Simulation time 34243958315 ps
CPU time 712.48 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:30:57 PM PDT 24
Peak memory 265400 kb
Host smart-67c3d5f1-4e60-4592-80ea-07f1972af8ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408554511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2408554511
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1805319707
Short name T690
Test name
Test status
Simulation time 37580117811 ps
CPU time 418.38 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 02:26:04 PM PDT 24
Peak memory 247168 kb
Host smart-14996103-518e-48c1-b4ee-4fbafc64b677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805319707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1805319707
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2048842481
Short name T689
Test name
Test status
Simulation time 220364038 ps
CPU time 6.56 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:19:10 PM PDT 24
Peak memory 248724 kb
Host smart-5bb2cb45-4961-407e-8286-d8579278a96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
42481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2048842481
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1973138783
Short name T393
Test name
Test status
Simulation time 1784802103 ps
CPU time 57.55 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:20:02 PM PDT 24
Peak memory 254700 kb
Host smart-8092bfef-d9ef-4e51-ad29-8d295e628aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
38783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1973138783
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1220246457
Short name T88
Test name
Test status
Simulation time 1902796446 ps
CPU time 67.38 seconds
Started May 16 02:19:02 PM PDT 24
Finished May 16 02:20:12 PM PDT 24
Peak memory 248748 kb
Host smart-695b05db-e750-474a-ae8a-41864923083d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
46457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1220246457
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1810444736
Short name T397
Test name
Test status
Simulation time 356690245 ps
CPU time 17.95 seconds
Started May 16 02:19:03 PM PDT 24
Finished May 16 02:19:24 PM PDT 24
Peak memory 248688 kb
Host smart-9257298f-1e6b-46f5-8158-13e510e4ba7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
44736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1810444736
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3022270808
Short name T96
Test name
Test status
Simulation time 7237355878 ps
CPU time 430.14 seconds
Started May 16 02:19:04 PM PDT 24
Finished May 16 02:26:17 PM PDT 24
Peak memory 256940 kb
Host smart-49625fa5-907d-4171-aa75-49a0e24a6d95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022270808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3022270808
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.670383192
Short name T481
Test name
Test status
Simulation time 6387777296 ps
CPU time 821.24 seconds
Started May 16 02:19:14 PM PDT 24
Finished May 16 02:32:58 PM PDT 24
Peak memory 273408 kb
Host smart-6d450067-4b4d-44e3-8586-0492d4882ebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670383192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.670383192
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1753540945
Short name T46
Test name
Test status
Simulation time 1117498821 ps
CPU time 49.18 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:20:06 PM PDT 24
Peak memory 256804 kb
Host smart-40b0b217-6333-45a5-9a74-7f482a19cddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
40945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1753540945
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3694039407
Short name T584
Test name
Test status
Simulation time 3156001638 ps
CPU time 50.16 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:20:07 PM PDT 24
Peak memory 255948 kb
Host smart-917f197b-ffe2-49bc-a0b6-791bbaa9cf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36940
39407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3694039407
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1802648917
Short name T146
Test name
Test status
Simulation time 31787011862 ps
CPU time 1431.45 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:43:08 PM PDT 24
Peak memory 281584 kb
Host smart-b97fb74f-514b-40a8-b8b4-e046937a18a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802648917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1802648917
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.329845033
Short name T401
Test name
Test status
Simulation time 104644827959 ps
CPU time 3067.41 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 03:10:25 PM PDT 24
Peak memory 289108 kb
Host smart-8f2bd635-5f27-421c-94e7-f4c58a945eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329845033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.329845033
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2202629345
Short name T321
Test name
Test status
Simulation time 22895709743 ps
CPU time 468.78 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:27:06 PM PDT 24
Peak memory 248184 kb
Host smart-747bf4ce-5a1f-4f99-81ba-c78ad3b02e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202629345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2202629345
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4149181196
Short name T692
Test name
Test status
Simulation time 2710886211 ps
CPU time 29.8 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:19:46 PM PDT 24
Peak memory 256044 kb
Host smart-5d668902-f1bb-46a8-8b21-6fd4ad7e3b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
81196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4149181196
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.107276474
Short name T398
Test name
Test status
Simulation time 1232337283 ps
CPU time 25.59 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:19:42 PM PDT 24
Peak memory 255804 kb
Host smart-61fa7918-cb09-455a-a59f-126740a52ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10727
6474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.107276474
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3279601816
Short name T666
Test name
Test status
Simulation time 126444359 ps
CPU time 10.39 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:19:27 PM PDT 24
Peak memory 248704 kb
Host smart-82b6a797-a6b2-4e2c-8c4c-603041194d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796
01816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3279601816
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2576929927
Short name T437
Test name
Test status
Simulation time 711045958 ps
CPU time 40.77 seconds
Started May 16 02:19:14 PM PDT 24
Finished May 16 02:19:55 PM PDT 24
Peak memory 248648 kb
Host smart-49e1727e-8ee6-4eb1-9cf4-9fa9bb4a0789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
29927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2576929927
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.166046194
Short name T293
Test name
Test status
Simulation time 71224809769 ps
CPU time 4865.94 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 03:40:24 PM PDT 24
Peak memory 321740 kb
Host smart-53793709-ecff-48b4-80bb-7287280590b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166046194 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.166046194
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3829118861
Short name T705
Test name
Test status
Simulation time 36303312725 ps
CPU time 2411.16 seconds
Started May 16 02:19:26 PM PDT 24
Finished May 16 02:59:38 PM PDT 24
Peak memory 289764 kb
Host smart-dbead5ac-69ba-4bdb-830c-6cb73dffd6bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829118861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3829118861
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2119380373
Short name T685
Test name
Test status
Simulation time 4146581658 ps
CPU time 20.72 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:19:51 PM PDT 24
Peak memory 255084 kb
Host smart-f3439263-cc4c-49a2-a1c1-3a6d06536e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21193
80373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2119380373
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2958235999
Short name T270
Test name
Test status
Simulation time 45934081 ps
CPU time 3.92 seconds
Started May 16 02:19:26 PM PDT 24
Finished May 16 02:19:31 PM PDT 24
Peak memory 240556 kb
Host smart-233ab607-7da4-4299-9546-a8e35777d7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
35999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2958235999
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.961612231
Short name T588
Test name
Test status
Simulation time 71432883171 ps
CPU time 2042.62 seconds
Started May 16 02:19:24 PM PDT 24
Finished May 16 02:53:28 PM PDT 24
Peak memory 271548 kb
Host smart-c1a63d3a-6e06-4c72-99b1-a0390e93226f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961612231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.961612231
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1649661103
Short name T494
Test name
Test status
Simulation time 9989067099 ps
CPU time 368.44 seconds
Started May 16 02:19:29 PM PDT 24
Finished May 16 02:25:39 PM PDT 24
Peak memory 248288 kb
Host smart-762de51a-edac-4b38-a63e-4b39038097f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649661103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1649661103
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.426813020
Short name T643
Test name
Test status
Simulation time 489939738 ps
CPU time 13.19 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:19:30 PM PDT 24
Peak memory 248708 kb
Host smart-e915fa45-33ef-4aec-9997-76ab6b4a9c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42681
3020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.426813020
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1985190968
Short name T519
Test name
Test status
Simulation time 230283782 ps
CPU time 19.55 seconds
Started May 16 02:19:15 PM PDT 24
Finished May 16 02:19:37 PM PDT 24
Peak memory 256076 kb
Host smart-2d16b68a-1147-48f2-9728-f6c82212a139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19851
90968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1985190968
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3135469385
Short name T129
Test name
Test status
Simulation time 626142865 ps
CPU time 16.01 seconds
Started May 16 02:19:16 PM PDT 24
Finished May 16 02:19:33 PM PDT 24
Peak memory 256052 kb
Host smart-bd926359-b96e-46c2-b670-2036cf491311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
69385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3135469385
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1856946321
Short name T260
Test name
Test status
Simulation time 16856991692 ps
CPU time 984.92 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:35:55 PM PDT 24
Peak memory 265228 kb
Host smart-d9769492-c196-4447-81ab-01c140410d98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856946321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1856946321
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4173923787
Short name T271
Test name
Test status
Simulation time 10898236344 ps
CPU time 330.38 seconds
Started May 16 02:19:26 PM PDT 24
Finished May 16 02:24:58 PM PDT 24
Peak memory 256924 kb
Host smart-dfd5685e-d8f3-45cf-bcb9-e0442da1a2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
23787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4173923787
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3296569281
Short name T376
Test name
Test status
Simulation time 28654131 ps
CPU time 4.75 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:19:35 PM PDT 24
Peak memory 249840 kb
Host smart-239f173a-5a5c-41fc-9f73-4c8f95a82efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32965
69281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3296569281
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.732204478
Short name T701
Test name
Test status
Simulation time 45500945296 ps
CPU time 2648.83 seconds
Started May 16 02:19:29 PM PDT 24
Finished May 16 03:03:40 PM PDT 24
Peak memory 282496 kb
Host smart-ca4de1ae-177a-4a98-94bd-b6f1cc20f17d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732204478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.732204478
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1781128974
Short name T267
Test name
Test status
Simulation time 36636835640 ps
CPU time 1650.26 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:47:00 PM PDT 24
Peak memory 289732 kb
Host smart-5e31e488-c75d-4c30-b682-00ba45fb8c60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781128974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1781128974
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.561231262
Short name T318
Test name
Test status
Simulation time 4462203157 ps
CPU time 90.03 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:21:00 PM PDT 24
Peak memory 247060 kb
Host smart-73509946-7805-4aae-a922-7b3848c780c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561231262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.561231262
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.70764208
Short name T650
Test name
Test status
Simulation time 1264740822 ps
CPU time 19.83 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:19:49 PM PDT 24
Peak memory 248700 kb
Host smart-aa701de2-60e4-4394-af46-1a661f96b9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70764
208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.70764208
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1473829960
Short name T485
Test name
Test status
Simulation time 716221864 ps
CPU time 40.7 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:20:11 PM PDT 24
Peak memory 248744 kb
Host smart-b59a31dd-1b82-4167-ad98-51cd37d1a430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14738
29960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1473829960
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.553767167
Short name T432
Test name
Test status
Simulation time 572648388 ps
CPU time 29.58 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:19:59 PM PDT 24
Peak memory 248752 kb
Host smart-57a76414-5527-461f-8ac1-1be45d118b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55376
7167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.553767167
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.404406202
Short name T600
Test name
Test status
Simulation time 690456577 ps
CPU time 30.65 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:20:00 PM PDT 24
Peak memory 248752 kb
Host smart-d0f08fe4-6d8f-4f88-9f93-532b8e08b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
6202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.404406202
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3579795048
Short name T493
Test name
Test status
Simulation time 2078924865 ps
CPU time 136.71 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:21:47 PM PDT 24
Peak memory 248768 kb
Host smart-fd4d5ca1-6c70-4ce5-b23b-769fc34b45e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35797
95048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3579795048
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2665749346
Short name T410
Test name
Test status
Simulation time 299187162 ps
CPU time 17.98 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:19:47 PM PDT 24
Peak memory 248696 kb
Host smart-0ef42482-d9ab-4136-b797-50e92579f53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
49346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2665749346
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1143958575
Short name T316
Test name
Test status
Simulation time 34206476391 ps
CPU time 817.85 seconds
Started May 16 02:19:35 PM PDT 24
Finished May 16 02:33:15 PM PDT 24
Peak memory 265088 kb
Host smart-3ec9068d-414a-4afa-a884-494481a24a8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143958575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1143958575
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2789934713
Short name T99
Test name
Test status
Simulation time 36530039840 ps
CPU time 2485.16 seconds
Started May 16 02:19:40 PM PDT 24
Finished May 16 03:01:07 PM PDT 24
Peak memory 288472 kb
Host smart-74b4e5c6-c38b-4d2d-b90b-f535126e223c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789934713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2789934713
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3497930389
Short name T332
Test name
Test status
Simulation time 23492729138 ps
CPU time 540.13 seconds
Started May 16 02:19:26 PM PDT 24
Finished May 16 02:28:27 PM PDT 24
Peak memory 248236 kb
Host smart-8d8968c7-4f1d-4a0a-894c-156fa2a6927e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497930389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3497930389
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3869878689
Short name T468
Test name
Test status
Simulation time 275574906 ps
CPU time 5.06 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:19:34 PM PDT 24
Peak memory 240496 kb
Host smart-7551c635-90f9-465b-8526-26d93cf98bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
78689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3869878689
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3820950412
Short name T443
Test name
Test status
Simulation time 1506447470 ps
CPU time 36.08 seconds
Started May 16 02:19:27 PM PDT 24
Finished May 16 02:20:05 PM PDT 24
Peak memory 255244 kb
Host smart-4d41e300-8b3d-4848-a0ca-932e8e109ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
50412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3820950412
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2765157116
Short name T287
Test name
Test status
Simulation time 2200246940 ps
CPU time 44.18 seconds
Started May 16 02:19:25 PM PDT 24
Finished May 16 02:20:10 PM PDT 24
Peak memory 247732 kb
Host smart-f75d3161-f28e-48b5-abee-b3d0d2508135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
57116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2765157116
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4100973745
Short name T611
Test name
Test status
Simulation time 1922599906 ps
CPU time 58.97 seconds
Started May 16 02:19:28 PM PDT 24
Finished May 16 02:20:29 PM PDT 24
Peak memory 255616 kb
Host smart-1367c57e-7283-47c3-93be-ad0361a76d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41009
73745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4100973745
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.4136515705
Short name T652
Test name
Test status
Simulation time 20692313351 ps
CPU time 1887.27 seconds
Started May 16 02:19:40 PM PDT 24
Finished May 16 02:51:09 PM PDT 24
Peak memory 289056 kb
Host smart-bdcdc708-3d91-47e6-812c-c89ecf3f64e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136515705 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.4136515705
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.896090959
Short name T247
Test name
Test status
Simulation time 18664110 ps
CPU time 2.75 seconds
Started May 16 02:15:00 PM PDT 24
Finished May 16 02:15:04 PM PDT 24
Peak memory 248884 kb
Host smart-084ebc3b-da00-4e46-a378-58d59fca547c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=896090959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.896090959
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3852756817
Short name T121
Test name
Test status
Simulation time 32362091478 ps
CPU time 1397.27 seconds
Started May 16 02:14:49 PM PDT 24
Finished May 16 02:38:07 PM PDT 24
Peak memory 289376 kb
Host smart-61b6d73d-8da8-4e13-a102-b73a2d40a5e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852756817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3852756817
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1862350999
Short name T496
Test name
Test status
Simulation time 746486239 ps
CPU time 10.82 seconds
Started May 16 02:14:59 PM PDT 24
Finished May 16 02:15:11 PM PDT 24
Peak memory 252472 kb
Host smart-45d25868-4b18-4f58-8213-3d9845bfd8f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1862350999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1862350999
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2113344617
Short name T513
Test name
Test status
Simulation time 3405102732 ps
CPU time 193.41 seconds
Started May 16 02:14:48 PM PDT 24
Finished May 16 02:18:03 PM PDT 24
Peak memory 256940 kb
Host smart-93966eb2-9c99-42d0-bb2a-c3e1691ec375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21133
44617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2113344617
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1598065680
Short name T520
Test name
Test status
Simulation time 523993076 ps
CPU time 13.5 seconds
Started May 16 02:14:47 PM PDT 24
Finished May 16 02:15:02 PM PDT 24
Peak memory 248748 kb
Host smart-9aca8801-deb6-437c-b7df-67f2de94b9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
65680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1598065680
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2877328513
Short name T709
Test name
Test status
Simulation time 96403867170 ps
CPU time 2663.5 seconds
Started May 16 02:15:00 PM PDT 24
Finished May 16 02:59:25 PM PDT 24
Peak memory 288188 kb
Host smart-a6b5e77c-b21d-4c3c-8e5c-d3a07f8a4f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877328513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2877328513
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1362513027
Short name T394
Test name
Test status
Simulation time 8404709302 ps
CPU time 721.08 seconds
Started May 16 02:14:58 PM PDT 24
Finished May 16 02:27:00 PM PDT 24
Peak memory 272796 kb
Host smart-1e060240-5337-47dd-b252-1603c4f5b1e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362513027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1362513027
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.424756890
Short name T474
Test name
Test status
Simulation time 13047794461 ps
CPU time 256.72 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:19:05 PM PDT 24
Peak memory 256036 kb
Host smart-f195e48d-d62a-410c-9cb0-cf24d2696bbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424756890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.424756890
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1675599068
Short name T250
Test name
Test status
Simulation time 532146659 ps
CPU time 33.12 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:15:21 PM PDT 24
Peak memory 248732 kb
Host smart-bb96ee33-a29b-4ad1-92f0-ec0158ed3182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755
99068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1675599068
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.540428094
Short name T548
Test name
Test status
Simulation time 2400854511 ps
CPU time 35.67 seconds
Started May 16 02:14:46 PM PDT 24
Finished May 16 02:15:24 PM PDT 24
Peak memory 255012 kb
Host smart-5568d635-cac7-4ec2-98cf-3bbf81168d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54042
8094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.540428094
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.153953455
Short name T141
Test name
Test status
Simulation time 2707418488 ps
CPU time 31.85 seconds
Started May 16 02:14:48 PM PDT 24
Finished May 16 02:15:21 PM PDT 24
Peak memory 255672 kb
Host smart-db96b295-42fe-4ef3-b8a5-21634e25c4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15395
3455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.153953455
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1834632224
Short name T258
Test name
Test status
Simulation time 256084121 ps
CPU time 20.56 seconds
Started May 16 02:14:48 PM PDT 24
Finished May 16 02:15:10 PM PDT 24
Peak memory 248760 kb
Host smart-e237271b-3574-457f-9c3c-fe56684e00a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18346
32224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1834632224
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.630688827
Short name T140
Test name
Test status
Simulation time 15100228255 ps
CPU time 1095.26 seconds
Started May 16 02:15:00 PM PDT 24
Finished May 16 02:33:16 PM PDT 24
Peak memory 283808 kb
Host smart-e5cd74f2-bd4b-484b-8bed-df8b58919954
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630688827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.630688827
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2921573761
Short name T289
Test name
Test status
Simulation time 154108549750 ps
CPU time 8566.92 seconds
Started May 16 02:15:01 PM PDT 24
Finished May 16 04:37:50 PM PDT 24
Peak memory 371508 kb
Host smart-858f02b9-3ce0-45b9-805b-fda92d178fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921573761 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2921573761
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3437249434
Short name T676
Test name
Test status
Simulation time 222278672421 ps
CPU time 3188.27 seconds
Started May 16 02:19:34 PM PDT 24
Finished May 16 03:12:45 PM PDT 24
Peak memory 288648 kb
Host smart-e765df05-2357-4f06-a9fe-d273f9bfde44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437249434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3437249434
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.380591766
Short name T390
Test name
Test status
Simulation time 4176037029 ps
CPU time 54.1 seconds
Started May 16 02:19:35 PM PDT 24
Finished May 16 02:20:31 PM PDT 24
Peak memory 248612 kb
Host smart-32421b2c-52d6-409b-9144-89e8848384c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38059
1766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.380591766
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2990658312
Short name T669
Test name
Test status
Simulation time 564311921 ps
CPU time 15.51 seconds
Started May 16 02:19:34 PM PDT 24
Finished May 16 02:19:50 PM PDT 24
Peak memory 255644 kb
Host smart-c1b769e1-12d8-4411-90f3-cc7bed1b1cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
58312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2990658312
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.864774772
Short name T303
Test name
Test status
Simulation time 71222198469 ps
CPU time 1537.2 seconds
Started May 16 02:19:35 PM PDT 24
Finished May 16 02:45:15 PM PDT 24
Peak memory 288912 kb
Host smart-7bd5d711-82e8-429a-98b8-2cb8190b65f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864774772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.864774772
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1716851654
Short name T337
Test name
Test status
Simulation time 9972405347 ps
CPU time 395.58 seconds
Started May 16 02:19:39 PM PDT 24
Finished May 16 02:26:17 PM PDT 24
Peak memory 248160 kb
Host smart-769ce240-a830-45f9-a2d6-9b6195a6fc52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716851654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1716851654
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2326144085
Short name T315
Test name
Test status
Simulation time 783532426 ps
CPU time 44.56 seconds
Started May 16 02:19:34 PM PDT 24
Finished May 16 02:20:20 PM PDT 24
Peak memory 248628 kb
Host smart-b8e5c606-b6dc-4ca6-b008-af208807b833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
44085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2326144085
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.481000667
Short name T422
Test name
Test status
Simulation time 873479180 ps
CPU time 14.11 seconds
Started May 16 02:19:35 PM PDT 24
Finished May 16 02:19:52 PM PDT 24
Peak memory 248644 kb
Host smart-3f21aecc-e7f4-41d1-9e3e-71775f927769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48100
0667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.481000667
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3327992601
Short name T41
Test name
Test status
Simulation time 1801810857 ps
CPU time 42.59 seconds
Started May 16 02:19:34 PM PDT 24
Finished May 16 02:20:19 PM PDT 24
Peak memory 256160 kb
Host smart-7d12d59d-381a-4242-a595-2612974b0aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33279
92601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3327992601
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.697145225
Short name T122
Test name
Test status
Simulation time 165948367359 ps
CPU time 2513.56 seconds
Started May 16 02:19:37 PM PDT 24
Finished May 16 03:01:33 PM PDT 24
Peak memory 287672 kb
Host smart-1578b5af-e038-4b33-a671-3dffa1c7b2d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697145225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.697145225
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2995973324
Short name T440
Test name
Test status
Simulation time 12398852627 ps
CPU time 605.28 seconds
Started May 16 02:19:46 PM PDT 24
Finished May 16 02:29:55 PM PDT 24
Peak memory 265308 kb
Host smart-f0f95c20-41b6-4ab4-9429-0b2e70f14640
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995973324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2995973324
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3490978203
Short name T125
Test name
Test status
Simulation time 1289219710 ps
CPU time 105.62 seconds
Started May 16 02:19:46 PM PDT 24
Finished May 16 02:21:36 PM PDT 24
Peak memory 256852 kb
Host smart-e51d22b7-d0de-466c-ba64-05a6f835fd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
78203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3490978203
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3139018600
Short name T595
Test name
Test status
Simulation time 839369381 ps
CPU time 50.38 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:40 PM PDT 24
Peak memory 255196 kb
Host smart-104f9a1e-ee9e-4383-af6b-788f3171724c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
18600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3139018600
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2064098856
Short name T527
Test name
Test status
Simulation time 165225353413 ps
CPU time 2428.64 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 03:00:18 PM PDT 24
Peak memory 289288 kb
Host smart-d49db4aa-528f-495f-a5c9-3ee1cd69cdcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064098856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2064098856
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.430584821
Short name T47
Test name
Test status
Simulation time 120070201618 ps
CPU time 2474.47 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 03:01:03 PM PDT 24
Peak memory 288664 kb
Host smart-7e2a1f57-dc2c-482d-bb67-ebfcf1bf7aeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430584821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.430584821
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3052100915
Short name T333
Test name
Test status
Simulation time 7193454118 ps
CPU time 284.06 seconds
Started May 16 02:19:49 PM PDT 24
Finished May 16 02:24:36 PM PDT 24
Peak memory 248340 kb
Host smart-f09156ae-deb4-4a1e-9f64-7b3d6c83645c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052100915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3052100915
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2098767993
Short name T216
Test name
Test status
Simulation time 1667506357 ps
CPU time 24.78 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:14 PM PDT 24
Peak memory 248748 kb
Host smart-bdab9a33-0973-493a-a6e3-771f5902c313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
67993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2098767993
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2788568761
Short name T452
Test name
Test status
Simulation time 7192258185 ps
CPU time 63.07 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:52 PM PDT 24
Peak memory 256656 kb
Host smart-fd78343f-ca2c-4a26-8e02-1f377c6c6186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
68761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2788568761
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1321222099
Short name T379
Test name
Test status
Simulation time 296899304 ps
CPU time 30.78 seconds
Started May 16 02:19:46 PM PDT 24
Finished May 16 02:20:21 PM PDT 24
Peak memory 248740 kb
Host smart-250f033d-8676-4dd5-a15f-77d4bac5cdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
22099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1321222099
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1594193641
Short name T441
Test name
Test status
Simulation time 752629398 ps
CPU time 40.95 seconds
Started May 16 02:19:34 PM PDT 24
Finished May 16 02:20:17 PM PDT 24
Peak memory 255620 kb
Host smart-3bc9fc9c-d10d-4ef7-be7f-1c5b86b97a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
93641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1594193641
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1156261128
Short name T465
Test name
Test status
Simulation time 38413694151 ps
CPU time 1293.29 seconds
Started May 16 02:19:48 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 273320 kb
Host smart-06b155d8-1179-49bf-8bac-e6bc78c3c2b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156261128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1156261128
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.572645191
Short name T123
Test name
Test status
Simulation time 19389218843 ps
CPU time 1014.85 seconds
Started May 16 02:19:44 PM PDT 24
Finished May 16 02:36:41 PM PDT 24
Peak memory 273492 kb
Host smart-cf62c05d-127e-42f5-abd8-1cf58647f059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572645191 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.572645191
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1221136373
Short name T529
Test name
Test status
Simulation time 50621031393 ps
CPU time 3011.28 seconds
Started May 16 02:19:48 PM PDT 24
Finished May 16 03:10:03 PM PDT 24
Peak memory 288856 kb
Host smart-327b8f59-1dcd-4733-b637-233465e6ecec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221136373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1221136373
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3961537203
Short name T647
Test name
Test status
Simulation time 813071506 ps
CPU time 14.4 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:03 PM PDT 24
Peak memory 249052 kb
Host smart-a2ec1432-8226-4151-97d3-4d1fa4f7e1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39615
37203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3961537203
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1123282603
Short name T351
Test name
Test status
Simulation time 140049785381 ps
CPU time 1868.37 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 02:51:06 PM PDT 24
Peak memory 272512 kb
Host smart-1544c634-53ce-42e1-b034-e5576c335dad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123282603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1123282603
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3739452376
Short name T97
Test name
Test status
Simulation time 34294337342 ps
CPU time 563.8 seconds
Started May 16 02:19:55 PM PDT 24
Finished May 16 02:29:20 PM PDT 24
Peak memory 265172 kb
Host smart-33e76d1c-352f-4962-914e-768761da64c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739452376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3739452376
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3979112473
Short name T73
Test name
Test status
Simulation time 12041620096 ps
CPU time 134.61 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 02:22:12 PM PDT 24
Peak memory 248008 kb
Host smart-1e3de74c-ed25-4a85-851b-a0e72e11462b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979112473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3979112473
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.212979448
Short name T252
Test name
Test status
Simulation time 565213553 ps
CPU time 33.61 seconds
Started May 16 02:19:46 PM PDT 24
Finished May 16 02:20:24 PM PDT 24
Peak memory 248724 kb
Host smart-e41c642a-076d-4838-b112-14edd9097ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
9448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.212979448
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3854506339
Short name T50
Test name
Test status
Simulation time 406304068 ps
CPU time 22.22 seconds
Started May 16 02:19:46 PM PDT 24
Finished May 16 02:20:12 PM PDT 24
Peak memory 248660 kb
Host smart-3ea337ea-152f-4f8a-8015-909920522fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38545
06339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3854506339
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3223822375
Short name T14
Test name
Test status
Simulation time 256422959 ps
CPU time 31.64 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:21 PM PDT 24
Peak memory 247408 kb
Host smart-f33964b5-7881-4b7f-a480-ed14308a65f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
22375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3223822375
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4092472121
Short name T480
Test name
Test status
Simulation time 241314510 ps
CPU time 15.89 seconds
Started May 16 02:19:45 PM PDT 24
Finished May 16 02:20:05 PM PDT 24
Peak memory 248712 kb
Host smart-001b979b-82e7-483a-bcb3-d1560a516823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
72121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4092472121
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2946060581
Short name T256
Test name
Test status
Simulation time 137821004249 ps
CPU time 2541.79 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 03:02:19 PM PDT 24
Peak memory 289040 kb
Host smart-dbf29866-0520-4a44-9014-bf3cbdeb6b65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946060581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2946060581
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1735820140
Short name T53
Test name
Test status
Simulation time 76442298642 ps
CPU time 1606.48 seconds
Started May 16 02:19:57 PM PDT 24
Finished May 16 02:46:45 PM PDT 24
Peak memory 289416 kb
Host smart-87b81bd5-f5a8-4753-89ea-3f8fac673684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735820140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1735820140
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.81624972
Short name T302
Test name
Test status
Simulation time 4355689197 ps
CPU time 257.69 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 02:24:14 PM PDT 24
Peak memory 256980 kb
Host smart-b6285c07-5610-473b-a344-2c9275f218b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81624
972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.81624972
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.960017304
Short name T384
Test name
Test status
Simulation time 3948259779 ps
CPU time 58.69 seconds
Started May 16 02:19:57 PM PDT 24
Finished May 16 02:20:57 PM PDT 24
Peak memory 248716 kb
Host smart-612dd25f-4ad3-445d-9856-ce57e465741a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96001
7304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.960017304
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3102909495
Short name T543
Test name
Test status
Simulation time 27380475103 ps
CPU time 1588.06 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 02:46:37 PM PDT 24
Peak memory 272808 kb
Host smart-03682a7d-862b-4eca-89e3-c8659b8445ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102909495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3102909495
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1759302566
Short name T525
Test name
Test status
Simulation time 24875199254 ps
CPU time 1502.32 seconds
Started May 16 02:20:08 PM PDT 24
Finished May 16 02:45:12 PM PDT 24
Peak memory 270312 kb
Host smart-e2b86dc7-b007-48bb-a2ce-064651aef0a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759302566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1759302566
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2914217039
Short name T336
Test name
Test status
Simulation time 12284450371 ps
CPU time 248.96 seconds
Started May 16 02:19:57 PM PDT 24
Finished May 16 02:24:07 PM PDT 24
Peak memory 248196 kb
Host smart-edbb3694-87ab-43b1-b340-2db6bbe330ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914217039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2914217039
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3560651319
Short name T560
Test name
Test status
Simulation time 496349776 ps
CPU time 20.59 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 02:20:18 PM PDT 24
Peak memory 248740 kb
Host smart-496ae15d-99ac-408a-974a-83b19b6485f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
51319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3560651319
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2397440179
Short name T68
Test name
Test status
Simulation time 1550835893 ps
CPU time 27.46 seconds
Started May 16 02:19:56 PM PDT 24
Finished May 16 02:20:25 PM PDT 24
Peak memory 248840 kb
Host smart-4666be1d-b4dc-44af-b404-14ccc94b0ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
40179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2397440179
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3917310787
Short name T399
Test name
Test status
Simulation time 450517538 ps
CPU time 34.17 seconds
Started May 16 02:19:54 PM PDT 24
Finished May 16 02:20:29 PM PDT 24
Peak memory 248912 kb
Host smart-8734fe5b-0e37-4f7c-af15-c8bb448146d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
10787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3917310787
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2432131676
Short name T603
Test name
Test status
Simulation time 294299905 ps
CPU time 21.63 seconds
Started May 16 02:19:55 PM PDT 24
Finished May 16 02:20:18 PM PDT 24
Peak memory 248732 kb
Host smart-aeec48be-8a99-48c2-8628-2876a1dc1daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
31676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2432131676
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3383244961
Short name T52
Test name
Test status
Simulation time 11596652488 ps
CPU time 735.59 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 02:32:24 PM PDT 24
Peak memory 272872 kb
Host smart-c98cea72-337a-4f0a-8b44-7e3fd677f5d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383244961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3383244961
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.115361730
Short name T112
Test name
Test status
Simulation time 19868631905 ps
CPU time 2121.39 seconds
Started May 16 02:20:06 PM PDT 24
Finished May 16 02:55:29 PM PDT 24
Peak memory 300012 kb
Host smart-0e4a8b3c-c6f1-45d9-a510-236e075e4bfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115361730 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.115361730
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3232720228
Short name T642
Test name
Test status
Simulation time 24449960969 ps
CPU time 1433.33 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 02:44:02 PM PDT 24
Peak memory 273388 kb
Host smart-6099abf6-b8f3-42ce-85ed-afb125b944fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232720228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3232720228
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1191339573
Short name T482
Test name
Test status
Simulation time 1731613969 ps
CPU time 25.83 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 02:20:34 PM PDT 24
Peak memory 247496 kb
Host smart-ecc0f47d-1b08-4e02-834a-b3cbf776a348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
39573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1191339573
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3432821614
Short name T567
Test name
Test status
Simulation time 6381506168 ps
CPU time 54.77 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 02:21:03 PM PDT 24
Peak memory 249120 kb
Host smart-0867a7c0-220f-4ee0-a191-2514f05e599d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
21614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3432821614
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4197621929
Short name T359
Test name
Test status
Simulation time 166691554547 ps
CPU time 2705.4 seconds
Started May 16 02:20:07 PM PDT 24
Finished May 16 03:05:14 PM PDT 24
Peak memory 289320 kb
Host smart-472924b9-1a4d-4217-82e6-a4df1ee7eee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197621929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4197621929
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.144126220
Short name T305
Test name
Test status
Simulation time 33845297032 ps
CPU time 2120.09 seconds
Started May 16 02:20:06 PM PDT 24
Finished May 16 02:55:28 PM PDT 24
Peak memory 281584 kb
Host smart-80c809c2-e942-4dc4-b7f2-98266ebe882e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144126220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.144126220
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1014922273
Short name T715
Test name
Test status
Simulation time 43583907834 ps
CPU time 455.63 seconds
Started May 16 02:20:06 PM PDT 24
Finished May 16 02:27:44 PM PDT 24
Peak memory 248196 kb
Host smart-dff25254-1258-4d3b-a59b-7eb3c0612306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014922273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1014922273
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2329729409
Short name T624
Test name
Test status
Simulation time 758806961 ps
CPU time 21.93 seconds
Started May 16 02:20:06 PM PDT 24
Finished May 16 02:20:30 PM PDT 24
Peak memory 248716 kb
Host smart-93f05d08-8677-4635-b97b-47a7ceb5e8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23297
29409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2329729409
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3895961391
Short name T103
Test name
Test status
Simulation time 353516352 ps
CPU time 27.73 seconds
Started May 16 02:20:05 PM PDT 24
Finished May 16 02:20:34 PM PDT 24
Peak memory 255904 kb
Host smart-1ce603ae-0e92-453e-82fa-e74120e66993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959
61391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3895961391
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3987843698
Short name T311
Test name
Test status
Simulation time 640872461 ps
CPU time 13.08 seconds
Started May 16 02:20:08 PM PDT 24
Finished May 16 02:20:23 PM PDT 24
Peak memory 248768 kb
Host smart-9138eb28-de66-452b-8ada-273a232ea909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39878
43698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3987843698
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.332960283
Short name T124
Test name
Test status
Simulation time 97872809562 ps
CPU time 307.25 seconds
Started May 16 02:20:05 PM PDT 24
Finished May 16 02:25:14 PM PDT 24
Peak memory 256956 kb
Host smart-b8504502-4708-4e05-a90c-3b7675bab63b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332960283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.332960283
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1511003484
Short name T78
Test name
Test status
Simulation time 89969142248 ps
CPU time 1352.42 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:42:49 PM PDT 24
Peak memory 289364 kb
Host smart-2e8af545-7b2f-4303-8ea6-8c481ca57bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511003484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1511003484
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3502601573
Short name T431
Test name
Test status
Simulation time 1578494015 ps
CPU time 160.87 seconds
Started May 16 02:20:19 PM PDT 24
Finished May 16 02:23:01 PM PDT 24
Peak memory 256908 kb
Host smart-0192702b-46a4-41b8-bd74-df30c33b3b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
01573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3502601573
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3235975102
Short name T82
Test name
Test status
Simulation time 879697784 ps
CPU time 48.14 seconds
Started May 16 02:20:20 PM PDT 24
Finished May 16 02:21:10 PM PDT 24
Peak memory 255956 kb
Host smart-d5f92070-367c-4ec6-9648-611eff381704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359
75102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3235975102
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.343282268
Short name T659
Test name
Test status
Simulation time 94364884394 ps
CPU time 1403.56 seconds
Started May 16 02:20:18 PM PDT 24
Finished May 16 02:43:43 PM PDT 24
Peak memory 265200 kb
Host smart-f4bd0d6d-b5f3-43c8-82ce-3bf113d34716
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343282268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.343282268
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1172815951
Short name T655
Test name
Test status
Simulation time 26811907854 ps
CPU time 757.53 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:32:56 PM PDT 24
Peak memory 273332 kb
Host smart-445eea8a-6c0c-428a-a50d-82bd68a362d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172815951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1172815951
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4213261851
Short name T334
Test name
Test status
Simulation time 13756667090 ps
CPU time 566.97 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:29:46 PM PDT 24
Peak memory 248180 kb
Host smart-0de33710-bdd5-42cc-9ec5-9324acabc6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213261851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4213261851
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3807188188
Short name T426
Test name
Test status
Simulation time 671080250 ps
CPU time 17.3 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:20:36 PM PDT 24
Peak memory 248660 kb
Host smart-5fd6cba3-f986-4375-8534-1287f3889b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
88188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3807188188
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2944269531
Short name T557
Test name
Test status
Simulation time 230301188 ps
CPU time 24.12 seconds
Started May 16 02:20:18 PM PDT 24
Finished May 16 02:20:43 PM PDT 24
Peak memory 255080 kb
Host smart-8fb7cc1a-41f1-40ff-942f-d082d7b6f4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
69531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2944269531
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3709074741
Short name T215
Test name
Test status
Simulation time 4842665449 ps
CPU time 42.95 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:21:02 PM PDT 24
Peak memory 255604 kb
Host smart-d922eeaf-7cb9-4743-b19e-d738f91721c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
74741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3709074741
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2486126162
Short name T472
Test name
Test status
Simulation time 1312016736 ps
CPU time 24.79 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:20:42 PM PDT 24
Peak memory 256100 kb
Host smart-68e9a8e5-fd2d-4744-8a18-7e4d3ccf80dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
26162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2486126162
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4190787847
Short name T639
Test name
Test status
Simulation time 1130050917 ps
CPU time 46.05 seconds
Started May 16 02:20:19 PM PDT 24
Finished May 16 02:21:06 PM PDT 24
Peak memory 256940 kb
Host smart-1cd9083e-1149-42ab-bcc5-bde663872d89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190787847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4190787847
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.212250663
Short name T309
Test name
Test status
Simulation time 31576988054 ps
CPU time 2843.98 seconds
Started May 16 02:20:18 PM PDT 24
Finished May 16 03:07:43 PM PDT 24
Peak memory 322384 kb
Host smart-11d21c2a-e23e-4723-84f6-df2897f581dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212250663 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.212250663
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1474191698
Short name T101
Test name
Test status
Simulation time 18889188761 ps
CPU time 1182.05 seconds
Started May 16 02:20:20 PM PDT 24
Finished May 16 02:40:03 PM PDT 24
Peak memory 289224 kb
Host smart-3551f081-5c71-4431-b8fd-706bec46ef45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474191698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1474191698
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2101290533
Short name T488
Test name
Test status
Simulation time 58664239 ps
CPU time 4.89 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:20:23 PM PDT 24
Peak memory 239200 kb
Host smart-646f9391-0322-41bb-aae7-11948baa754a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
90533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2101290533
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1899195481
Short name T542
Test name
Test status
Simulation time 1666221246 ps
CPU time 52.04 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:21:10 PM PDT 24
Peak memory 248744 kb
Host smart-7f70d0f0-7129-4ea7-ba8a-691a51627933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
95481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1899195481
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2435864303
Short name T42
Test name
Test status
Simulation time 21723052006 ps
CPU time 1382.28 seconds
Started May 16 02:20:29 PM PDT 24
Finished May 16 02:43:33 PM PDT 24
Peak memory 271148 kb
Host smart-d0406ecb-b323-4730-865e-83d4da4741c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435864303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2435864303
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.984074468
Short name T6
Test name
Test status
Simulation time 6050581440 ps
CPU time 238.4 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:24:17 PM PDT 24
Peak memory 248332 kb
Host smart-0ad95e19-4569-4e3f-9ece-3f7b78ead077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984074468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.984074468
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1710639706
Short name T568
Test name
Test status
Simulation time 859339829 ps
CPU time 21.1 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:20:39 PM PDT 24
Peak memory 248756 kb
Host smart-fbc35f21-7cc4-40b8-a499-d3ecd8a03b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
39706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1710639706
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1391927425
Short name T307
Test name
Test status
Simulation time 276912739 ps
CPU time 25.38 seconds
Started May 16 02:20:17 PM PDT 24
Finished May 16 02:20:44 PM PDT 24
Peak memory 248736 kb
Host smart-1a34c644-1b0c-47a1-9d52-b160ef28c96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
27425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1391927425
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3247045899
Short name T408
Test name
Test status
Simulation time 313519432 ps
CPU time 11.36 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:20:29 PM PDT 24
Peak memory 247404 kb
Host smart-2d2456f0-c703-4c1b-aa0a-11ae6a26ac16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32470
45899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3247045899
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1479309635
Short name T396
Test name
Test status
Simulation time 4535965846 ps
CPU time 52.98 seconds
Started May 16 02:20:16 PM PDT 24
Finished May 16 02:21:10 PM PDT 24
Peak memory 256136 kb
Host smart-110ad338-b781-41d3-ac76-4ffc8c19d21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
09635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1479309635
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2603041546
Short name T436
Test name
Test status
Simulation time 46821913204 ps
CPU time 1482.74 seconds
Started May 16 02:20:29 PM PDT 24
Finished May 16 02:45:13 PM PDT 24
Peak memory 273248 kb
Host smart-123e1828-05c5-4e1f-839d-008ac1a376d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603041546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2603041546
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.289546470
Short name T143
Test name
Test status
Simulation time 775223358 ps
CPU time 28.75 seconds
Started May 16 02:20:27 PM PDT 24
Finished May 16 02:20:57 PM PDT 24
Peak memory 256168 kb
Host smart-a7dc9d5d-f152-4214-b8ae-3991d43b8a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28954
6470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.289546470
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2609576726
Short name T347
Test name
Test status
Simulation time 213974853967 ps
CPU time 1606.41 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 02:47:17 PM PDT 24
Peak memory 288968 kb
Host smart-b851f427-d4bb-4b8a-a1ca-d8213eb7e627
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609576726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2609576726
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3675303610
Short name T502
Test name
Test status
Simulation time 1403169417 ps
CPU time 60.38 seconds
Started May 16 02:20:27 PM PDT 24
Finished May 16 02:21:29 PM PDT 24
Peak memory 248040 kb
Host smart-781e0075-3ddf-418f-a259-1fffbbc4828a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675303610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3675303610
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1771384924
Short name T469
Test name
Test status
Simulation time 1249486871 ps
CPU time 74.51 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 02:21:45 PM PDT 24
Peak memory 255840 kb
Host smart-86adc841-5f05-4245-805e-200ed2b02ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17713
84924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1771384924
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2372041026
Short name T213
Test name
Test status
Simulation time 413333133 ps
CPU time 40.39 seconds
Started May 16 02:20:28 PM PDT 24
Finished May 16 02:21:10 PM PDT 24
Peak memory 255600 kb
Host smart-f0181065-b6af-4136-aceb-ca36e0ad4adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23720
41026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2372041026
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1507408236
Short name T212
Test name
Test status
Simulation time 172695797 ps
CPU time 12.27 seconds
Started May 16 02:20:27 PM PDT 24
Finished May 16 02:20:41 PM PDT 24
Peak memory 254044 kb
Host smart-48819a56-519c-422b-b00c-9a731ea7fce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15074
08236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1507408236
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3664601571
Short name T612
Test name
Test status
Simulation time 1218647331 ps
CPU time 30.77 seconds
Started May 16 02:20:29 PM PDT 24
Finished May 16 02:21:01 PM PDT 24
Peak memory 249056 kb
Host smart-a002befa-0a57-4fc1-b61f-3e96978853e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36646
01571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3664601571
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4252361662
Short name T1
Test name
Test status
Simulation time 19988831479 ps
CPU time 1782.96 seconds
Started May 16 02:20:42 PM PDT 24
Finished May 16 02:50:27 PM PDT 24
Peak memory 305516 kb
Host smart-b0107d04-7856-4a7f-bd13-aaef4c638933
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252361662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4252361662
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2158689171
Short name T628
Test name
Test status
Simulation time 50340243186 ps
CPU time 3626.17 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 298084 kb
Host smart-2401be68-004f-4a34-a6c9-a424a0ebde1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158689171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2158689171
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2108201048
Short name T516
Test name
Test status
Simulation time 267697075377 ps
CPU time 2388.53 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 03:00:32 PM PDT 24
Peak memory 289748 kb
Host smart-b69463b5-8a98-404e-b1d5-e531e5141b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108201048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2108201048
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1541350764
Short name T501
Test name
Test status
Simulation time 8357655062 ps
CPU time 109.34 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 02:22:33 PM PDT 24
Peak memory 256764 kb
Host smart-1217a37c-0ccc-431a-b34e-0fad981aeda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15413
50764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1541350764
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.198524389
Short name T66
Test name
Test status
Simulation time 831632877 ps
CPU time 18.27 seconds
Started May 16 02:20:42 PM PDT 24
Finished May 16 02:21:02 PM PDT 24
Peak memory 255884 kb
Host smart-bf763d15-bf6a-49d3-add4-666899ca2f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19852
4389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.198524389
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.412278480
Short name T298
Test name
Test status
Simulation time 79851934214 ps
CPU time 1689.63 seconds
Started May 16 02:20:42 PM PDT 24
Finished May 16 02:48:54 PM PDT 24
Peak memory 272776 kb
Host smart-7f82d73d-62ac-474e-8848-34bb4d73284d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412278480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.412278480
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2386286873
Short name T712
Test name
Test status
Simulation time 130149974165 ps
CPU time 2165.16 seconds
Started May 16 02:20:53 PM PDT 24
Finished May 16 02:56:59 PM PDT 24
Peak memory 288872 kb
Host smart-b347ef9f-c021-4249-855e-afbc46e0318d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386286873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2386286873
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3661356978
Short name T317
Test name
Test status
Simulation time 21282174178 ps
CPU time 158.68 seconds
Started May 16 02:20:40 PM PDT 24
Finished May 16 02:23:20 PM PDT 24
Peak memory 248220 kb
Host smart-869d7945-275f-4fb0-9ba9-eb84315772d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661356978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3661356978
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2255389132
Short name T562
Test name
Test status
Simulation time 652177871 ps
CPU time 37.01 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 02:21:20 PM PDT 24
Peak memory 248720 kb
Host smart-c302a08d-735f-4f77-9813-5502e945710f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
89132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2255389132
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2228540812
Short name T697
Test name
Test status
Simulation time 851491740 ps
CPU time 56 seconds
Started May 16 02:20:45 PM PDT 24
Finished May 16 02:21:42 PM PDT 24
Peak memory 254832 kb
Host smart-6d6a32d3-1303-4540-a0bd-ad0aba24ea0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
40812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2228540812
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3289165491
Short name T75
Test name
Test status
Simulation time 1395404687 ps
CPU time 48.43 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 02:21:31 PM PDT 24
Peak memory 255568 kb
Host smart-3d045b7a-041a-41e0-b8d0-8147366c1d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32891
65491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3289165491
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3295316644
Short name T463
Test name
Test status
Simulation time 626909707 ps
CPU time 30.48 seconds
Started May 16 02:20:41 PM PDT 24
Finished May 16 02:21:14 PM PDT 24
Peak memory 248752 kb
Host smart-36a0f22c-df62-461a-9da9-c7c239856800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
16644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3295316644
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2604040123
Short name T414
Test name
Test status
Simulation time 1811107611 ps
CPU time 96.74 seconds
Started May 16 02:20:53 PM PDT 24
Finished May 16 02:22:32 PM PDT 24
Peak memory 255404 kb
Host smart-424e76d6-eea0-4539-b61e-3a9c05633ad8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604040123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2604040123
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3050510471
Short name T462
Test name
Test status
Simulation time 30822129853 ps
CPU time 1682.59 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 02:49:00 PM PDT 24
Peak memory 288756 kb
Host smart-9a60d533-eac2-4fff-b973-35f1c2c1daea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050510471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3050510471
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3499463650
Short name T378
Test name
Test status
Simulation time 16351733852 ps
CPU time 249.67 seconds
Started May 16 02:20:55 PM PDT 24
Finished May 16 02:25:07 PM PDT 24
Peak memory 256968 kb
Host smart-9cc88043-14bd-4dc3-8daa-c3cc2e6cb366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34994
63650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3499463650
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2532985679
Short name T26
Test name
Test status
Simulation time 2705367240 ps
CPU time 21.9 seconds
Started May 16 02:20:53 PM PDT 24
Finished May 16 02:21:17 PM PDT 24
Peak memory 255520 kb
Host smart-9f7216d0-8634-4f0a-8739-480128210ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
85679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2532985679
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2612107108
Short name T545
Test name
Test status
Simulation time 24944730166 ps
CPU time 1715.69 seconds
Started May 16 02:20:55 PM PDT 24
Finished May 16 02:49:33 PM PDT 24
Peak memory 272900 kb
Host smart-1a56a289-aeb0-4664-a50c-f0cacbb9ac8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612107108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2612107108
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1845250379
Short name T328
Test name
Test status
Simulation time 24356641960 ps
CPU time 474.38 seconds
Started May 16 02:20:52 PM PDT 24
Finished May 16 02:28:48 PM PDT 24
Peak memory 247072 kb
Host smart-6d8c9b6a-27b8-47eb-950a-81ecd2b4e287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845250379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1845250379
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2231174502
Short name T456
Test name
Test status
Simulation time 1122861841 ps
CPU time 35.28 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 02:21:31 PM PDT 24
Peak memory 255884 kb
Host smart-8b11bedc-0c1a-4187-b661-d5c385bfa703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
74502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2231174502
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2222665253
Short name T581
Test name
Test status
Simulation time 455030366 ps
CPU time 26.66 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 02:21:23 PM PDT 24
Peak memory 248936 kb
Host smart-4e0ad928-efdb-49e4-99b1-917a99263f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
65253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2222665253
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1027072297
Short name T276
Test name
Test status
Simulation time 3217902755 ps
CPU time 50.53 seconds
Started May 16 02:20:53 PM PDT 24
Finished May 16 02:21:46 PM PDT 24
Peak memory 256896 kb
Host smart-db59475c-4ac4-4169-8f15-bbd53207c318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
72297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1027072297
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1238715426
Short name T621
Test name
Test status
Simulation time 620037539 ps
CPU time 36.57 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 02:21:33 PM PDT 24
Peak memory 248792 kb
Host smart-966e5217-b671-4902-8797-0191eaae2e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
15426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1238715426
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2452342189
Short name T598
Test name
Test status
Simulation time 290677255029 ps
CPU time 4031.42 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 03:28:09 PM PDT 24
Peak memory 297996 kb
Host smart-4e97e88f-1051-4462-ba81-8c255d37c085
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452342189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2452342189
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.4249088826
Short name T702
Test name
Test status
Simulation time 159397832186 ps
CPU time 2296.1 seconds
Started May 16 02:20:54 PM PDT 24
Finished May 16 02:59:13 PM PDT 24
Peak memory 289512 kb
Host smart-cf9a3327-62b7-4168-9f82-7043e266986e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249088826 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.4249088826
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4138799621
Short name T243
Test name
Test status
Simulation time 38141490 ps
CPU time 2.34 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 02:15:14 PM PDT 24
Peak memory 248900 kb
Host smart-4110a42d-1e90-4ad6-9333-b6863c5ca3b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4138799621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4138799621
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2909756277
Short name T54
Test name
Test status
Simulation time 69794431942 ps
CPU time 2237.47 seconds
Started May 16 02:15:11 PM PDT 24
Finished May 16 02:52:30 PM PDT 24
Peak memory 286156 kb
Host smart-b3f96cd7-2592-448a-af87-0b4f2328c0fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909756277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2909756277
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2254645122
Short name T696
Test name
Test status
Simulation time 296711328 ps
CPU time 9.41 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 02:15:21 PM PDT 24
Peak memory 240564 kb
Host smart-795b9ba7-c507-425e-aae9-8d3da503f743
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2254645122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2254645122
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4247734285
Short name T675
Test name
Test status
Simulation time 150338852 ps
CPU time 20.03 seconds
Started May 16 02:15:11 PM PDT 24
Finished May 16 02:15:33 PM PDT 24
Peak memory 255604 kb
Host smart-4e1f430f-b0aa-467b-a984-608329c1cf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
34285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4247734285
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1285887267
Short name T490
Test name
Test status
Simulation time 2937445634 ps
CPU time 41.19 seconds
Started May 16 02:14:58 PM PDT 24
Finished May 16 02:15:40 PM PDT 24
Peak memory 256180 kb
Host smart-0268cb2e-0e00-49b9-80f3-5162280e3022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12858
87267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1285887267
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2268399645
Short name T609
Test name
Test status
Simulation time 86147220869 ps
CPU time 1310.89 seconds
Started May 16 02:15:09 PM PDT 24
Finished May 16 02:37:02 PM PDT 24
Peak memory 289100 kb
Host smart-8702c56b-6db5-4b2d-8912-1b9058fb2590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268399645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2268399645
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2591096470
Short name T446
Test name
Test status
Simulation time 4230369579 ps
CPU time 171.1 seconds
Started May 16 02:15:12 PM PDT 24
Finished May 16 02:18:04 PM PDT 24
Peak memory 247872 kb
Host smart-20684a9d-8604-4db4-9d2b-c46ab553137d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591096470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2591096470
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.756894659
Short name T511
Test name
Test status
Simulation time 1077007649 ps
CPU time 29.65 seconds
Started May 16 02:15:00 PM PDT 24
Finished May 16 02:15:31 PM PDT 24
Peak memory 248748 kb
Host smart-34f54846-921b-4e02-8429-b87510e01701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75689
4659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.756894659
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2695126750
Short name T395
Test name
Test status
Simulation time 1310478566 ps
CPU time 39.4 seconds
Started May 16 02:14:59 PM PDT 24
Finished May 16 02:15:39 PM PDT 24
Peak memory 255936 kb
Host smart-270bcf5c-67ee-4ae6-a0cf-a3aa38c295d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26951
26750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2695126750
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.850937010
Short name T495
Test name
Test status
Simulation time 264852877 ps
CPU time 11.75 seconds
Started May 16 02:15:00 PM PDT 24
Finished May 16 02:15:13 PM PDT 24
Peak memory 248712 kb
Host smart-3613394e-b404-45a4-9b61-2f9e957a7ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85093
7010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.850937010
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.142605086
Short name T680
Test name
Test status
Simulation time 1490436625 ps
CPU time 29.81 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 02:15:41 PM PDT 24
Peak memory 248744 kb
Host smart-b80b45c4-78fa-4ce8-8d7d-7377bdc8d2b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142605086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.142605086
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.53047359
Short name T60
Test name
Test status
Simulation time 57762107750 ps
CPU time 5664.96 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 03:49:37 PM PDT 24
Peak memory 353544 kb
Host smart-804c2316-9603-4ed2-827a-ab5e4a35ea97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53047359 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.53047359
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1323547262
Short name T244
Test name
Test status
Simulation time 36029665 ps
CPU time 3.42 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:15:27 PM PDT 24
Peak memory 248868 kb
Host smart-fa918660-571e-458d-97ed-2aa984e305ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1323547262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1323547262
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3355809043
Short name T582
Test name
Test status
Simulation time 573717560 ps
CPU time 9.52 seconds
Started May 16 02:15:20 PM PDT 24
Finished May 16 02:15:32 PM PDT 24
Peak memory 248696 kb
Host smart-94f8577d-6d75-4c7c-8699-be10f787990b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3355809043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3355809043
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.27716860
Short name T49
Test name
Test status
Simulation time 6900215045 ps
CPU time 103.84 seconds
Started May 16 02:15:12 PM PDT 24
Finished May 16 02:16:57 PM PDT 24
Peak memory 248804 kb
Host smart-6f001d96-f265-4872-bde0-1f0594235f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.27716860
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1290288043
Short name T92
Test name
Test status
Simulation time 1145600755 ps
CPU time 18.28 seconds
Started May 16 02:15:08 PM PDT 24
Finished May 16 02:15:28 PM PDT 24
Peak memory 256092 kb
Host smart-519ad8ac-9dfd-4078-859b-f2803fccb1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
88043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1290288043
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.702124510
Short name T345
Test name
Test status
Simulation time 128190317744 ps
CPU time 1953.22 seconds
Started May 16 02:15:09 PM PDT 24
Finished May 16 02:47:45 PM PDT 24
Peak memory 273428 kb
Host smart-2da77d58-c435-4291-a225-058bf50254d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702124510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.702124510
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2312916491
Short name T565
Test name
Test status
Simulation time 32956557559 ps
CPU time 1964.27 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:48:08 PM PDT 24
Peak memory 273376 kb
Host smart-1dec7e40-bdf4-4ff8-8962-3e060c1a8c0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312916491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2312916491
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3264329875
Short name T586
Test name
Test status
Simulation time 8361263309 ps
CPU time 250.8 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 02:19:23 PM PDT 24
Peak memory 248124 kb
Host smart-1641590b-ee07-43bb-89c0-8d7da4f8e950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264329875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3264329875
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2704127756
Short name T599
Test name
Test status
Simulation time 1011089322 ps
CPU time 27.75 seconds
Started May 16 02:15:10 PM PDT 24
Finished May 16 02:15:39 PM PDT 24
Peak memory 248788 kb
Host smart-96f4443f-836f-478c-9c38-477326db5bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
27756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2704127756
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3156222141
Short name T128
Test name
Test status
Simulation time 706847922 ps
CPU time 9.59 seconds
Started May 16 02:15:12 PM PDT 24
Finished May 16 02:15:23 PM PDT 24
Peak memory 248736 kb
Host smart-515462a2-08e9-4ea0-961a-915d6abfd6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
22141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3156222141
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.967927320
Short name T93
Test name
Test status
Simulation time 400779436 ps
CPU time 14.84 seconds
Started May 16 02:15:11 PM PDT 24
Finished May 16 02:15:27 PM PDT 24
Peak memory 247424 kb
Host smart-4b8d9830-31b4-4bd0-ab64-190b41dcd39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96792
7320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.967927320
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1335589187
Short name T668
Test name
Test status
Simulation time 1603870602 ps
CPU time 31.62 seconds
Started May 16 02:15:09 PM PDT 24
Finished May 16 02:15:42 PM PDT 24
Peak memory 248932 kb
Host smart-179c7051-93d0-4fb2-aba5-5182f44eb3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
89187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1335589187
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2745892288
Short name T471
Test name
Test status
Simulation time 138614344 ps
CPU time 13.33 seconds
Started May 16 02:15:25 PM PDT 24
Finished May 16 02:15:40 PM PDT 24
Peak memory 255348 kb
Host smart-2d2581db-2f8d-4fc2-bbf0-ae6fd783d061
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745892288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2745892288
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2657155181
Short name T538
Test name
Test status
Simulation time 46127065279 ps
CPU time 1553.32 seconds
Started May 16 02:15:20 PM PDT 24
Finished May 16 02:41:16 PM PDT 24
Peak memory 281748 kb
Host smart-63c32424-f620-4b59-9576-106dca62e639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657155181 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2657155181
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1918929323
Short name T245
Test name
Test status
Simulation time 37096373 ps
CPU time 2.39 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:15:26 PM PDT 24
Peak memory 248816 kb
Host smart-923b95e6-0212-409e-b3bf-36df92cb071f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1918929323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1918929323
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2276114950
Short name T500
Test name
Test status
Simulation time 42420671456 ps
CPU time 1049.81 seconds
Started May 16 02:15:26 PM PDT 24
Finished May 16 02:32:58 PM PDT 24
Peak memory 273392 kb
Host smart-0c134a5e-7868-417a-8172-b9cd4bb7f321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276114950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2276114950
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1657531515
Short name T464
Test name
Test status
Simulation time 332519929 ps
CPU time 15.94 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:15:39 PM PDT 24
Peak memory 248764 kb
Host smart-9fe69b61-0407-4c23-88b3-4c1a7e93cedc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1657531515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1657531515
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3457429440
Short name T451
Test name
Test status
Simulation time 3275468628 ps
CPU time 186.51 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:18:29 PM PDT 24
Peak memory 256764 kb
Host smart-4231645a-a7d1-4802-9e4c-999ee9e663c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34574
29440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3457429440
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2464253587
Short name T504
Test name
Test status
Simulation time 14108220687 ps
CPU time 54.05 seconds
Started May 16 02:15:25 PM PDT 24
Finished May 16 02:16:21 PM PDT 24
Peak memory 256940 kb
Host smart-f3ee39ac-2485-4e9d-b2bf-a517a8a4b2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
53587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2464253587
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.923515840
Short name T272
Test name
Test status
Simulation time 120188168146 ps
CPU time 1683.6 seconds
Started May 16 02:15:25 PM PDT 24
Finished May 16 02:43:31 PM PDT 24
Peak memory 289260 kb
Host smart-32d27244-0abb-411a-abd5-c0f263c0e161
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923515840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.923515840
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2368396471
Short name T3
Test name
Test status
Simulation time 349348358 ps
CPU time 27.31 seconds
Started May 16 02:15:26 PM PDT 24
Finished May 16 02:15:55 PM PDT 24
Peak memory 248740 kb
Host smart-922c26cf-538d-47fa-98cf-511a49a55960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23683
96471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2368396471
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3622478817
Short name T686
Test name
Test status
Simulation time 277813637 ps
CPU time 22.02 seconds
Started May 16 02:15:25 PM PDT 24
Finished May 16 02:15:50 PM PDT 24
Peak memory 248716 kb
Host smart-5ec5d415-51c1-4477-b988-27d91a9302ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
78817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3622478817
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2024748803
Short name T29
Test name
Test status
Simulation time 1086940854 ps
CPU time 15.78 seconds
Started May 16 02:15:26 PM PDT 24
Finished May 16 02:15:44 PM PDT 24
Peak memory 253972 kb
Host smart-bbd7bf4a-1d4a-48f8-8492-bf845184792c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
48803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2024748803
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3191541600
Short name T537
Test name
Test status
Simulation time 1159597493 ps
CPU time 20.32 seconds
Started May 16 02:15:21 PM PDT 24
Finished May 16 02:15:44 PM PDT 24
Peak memory 248732 kb
Host smart-191b474a-55b7-41ab-aad2-921d1eb5b1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
41600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3191541600
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3574993876
Short name T232
Test name
Test status
Simulation time 34065587 ps
CPU time 2.19 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:15:38 PM PDT 24
Peak memory 248888 kb
Host smart-21ae3f62-59f7-45d3-9b77-90feef9311fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574993876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3574993876
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3815486912
Short name T714
Test name
Test status
Simulation time 26358939996 ps
CPU time 1092.13 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:33:47 PM PDT 24
Peak memory 281508 kb
Host smart-38036d71-c2b8-4912-9200-c3c5e80d5406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815486912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3815486912
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2702109768
Short name T412
Test name
Test status
Simulation time 2935290158 ps
CPU time 184.28 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 256948 kb
Host smart-5d322bde-d077-444f-a806-582ba6c3f0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
09768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2702109768
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.765034566
Short name T407
Test name
Test status
Simulation time 142244034 ps
CPU time 8.66 seconds
Started May 16 02:15:32 PM PDT 24
Finished May 16 02:15:42 PM PDT 24
Peak memory 248724 kb
Host smart-9e5d3148-3e3f-4dd9-ac4e-69cb9da45176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76503
4566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.765034566
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2347536244
Short name T473
Test name
Test status
Simulation time 26742976553 ps
CPU time 1474.23 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:40:10 PM PDT 24
Peak memory 266220 kb
Host smart-97b985cd-a217-4849-9ac4-4a0561760ced
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347536244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2347536244
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1971656489
Short name T585
Test name
Test status
Simulation time 41035762343 ps
CPU time 417.63 seconds
Started May 16 02:15:35 PM PDT 24
Finished May 16 02:22:35 PM PDT 24
Peak memory 247852 kb
Host smart-bbd8503a-1ef2-434d-b53c-05c132ce20f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971656489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1971656489
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.694344230
Short name T547
Test name
Test status
Simulation time 1958871054 ps
CPU time 14.41 seconds
Started May 16 02:15:35 PM PDT 24
Finished May 16 02:15:52 PM PDT 24
Peak memory 255532 kb
Host smart-9c930aa2-2d96-450a-bc23-c079fce30e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69434
4230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.694344230
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3073360098
Short name T251
Test name
Test status
Simulation time 482876519 ps
CPU time 33.3 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:16:10 PM PDT 24
Peak memory 248744 kb
Host smart-b0fdea58-628d-4d09-b5c9-882aaf4f9bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30733
60098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3073360098
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2494120282
Short name T455
Test name
Test status
Simulation time 489815754 ps
CPU time 19.77 seconds
Started May 16 02:15:32 PM PDT 24
Finished May 16 02:15:53 PM PDT 24
Peak memory 248704 kb
Host smart-f7790e1e-9bd4-4d36-a8eb-2004332cb1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24941
20282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2494120282
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3592474124
Short name T608
Test name
Test status
Simulation time 29770750667 ps
CPU time 1670.28 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:43:27 PM PDT 24
Peak memory 273084 kb
Host smart-9c3e5c37-a0f0-48a4-a847-ab9a59997591
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592474124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3592474124
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3121131512
Short name T487
Test name
Test status
Simulation time 209358682706 ps
CPU time 4680.01 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 03:33:37 PM PDT 24
Peak memory 305604 kb
Host smart-cd427226-9bc5-457c-8ec7-cc0bcb082032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121131512 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3121131512
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1213817796
Short name T236
Test name
Test status
Simulation time 163290447 ps
CPU time 3.76 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:15:51 PM PDT 24
Peak memory 248900 kb
Host smart-ce1aa686-2c6e-4477-95bd-7b5432102a18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1213817796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1213817796
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1813397524
Short name T625
Test name
Test status
Simulation time 8882308601 ps
CPU time 885.52 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 02:30:33 PM PDT 24
Peak memory 273440 kb
Host smart-eb667ebe-3e84-4146-9cf5-c0cb2c42064a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813397524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1813397524
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.57200433
Short name T227
Test name
Test status
Simulation time 3399061969 ps
CPU time 39.36 seconds
Started May 16 02:15:50 PM PDT 24
Finished May 16 02:16:31 PM PDT 24
Peak memory 248780 kb
Host smart-ce7f8a21-2f01-4474-9a41-ad27a9812e71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=57200433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.57200433
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.686042927
Short name T374
Test name
Test status
Simulation time 4900914603 ps
CPU time 108.19 seconds
Started May 16 02:15:32 PM PDT 24
Finished May 16 02:17:21 PM PDT 24
Peak memory 256916 kb
Host smart-e0f16f91-c32d-4210-bb26-d596f220e61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68604
2927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.686042927
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2855880871
Short name T90
Test name
Test status
Simulation time 748384686 ps
CPU time 25.35 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:16:01 PM PDT 24
Peak memory 248752 kb
Host smart-e2923615-70be-4bf2-ae7e-df1bfa990282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
80871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2855880871
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.60732854
Short name T348
Test name
Test status
Simulation time 76228476065 ps
CPU time 2490.61 seconds
Started May 16 02:15:46 PM PDT 24
Finished May 16 02:57:19 PM PDT 24
Peak memory 288080 kb
Host smart-bea4ca72-050d-401b-9b82-7a8305fb4d29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60732854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.60732854
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3962085499
Short name T522
Test name
Test status
Simulation time 167892796098 ps
CPU time 2724.28 seconds
Started May 16 02:15:44 PM PDT 24
Finished May 16 03:01:10 PM PDT 24
Peak memory 289476 kb
Host smart-38231bb0-499d-48e3-b346-e130f0da115e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962085499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3962085499
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3037904380
Short name T693
Test name
Test status
Simulation time 26210841654 ps
CPU time 272.83 seconds
Started May 16 02:15:46 PM PDT 24
Finished May 16 02:20:21 PM PDT 24
Peak memory 254772 kb
Host smart-f807534b-07dc-4d99-b81f-ba5c251aa07d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037904380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3037904380
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.525984995
Short name T308
Test name
Test status
Simulation time 1856225589 ps
CPU time 33.38 seconds
Started May 16 02:15:32 PM PDT 24
Finished May 16 02:16:07 PM PDT 24
Peak memory 248712 kb
Host smart-8f60377d-0599-40a4-86dc-bb01e4d3fe40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52598
4995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.525984995
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1393621887
Short name T593
Test name
Test status
Simulation time 546471124 ps
CPU time 13.71 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:15:49 PM PDT 24
Peak memory 248700 kb
Host smart-301e2ecc-e938-40d5-93f5-112dab936679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13936
21887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1393621887
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3848269648
Short name T262
Test name
Test status
Simulation time 86074312 ps
CPU time 11.69 seconds
Started May 16 02:15:34 PM PDT 24
Finished May 16 02:15:48 PM PDT 24
Peak memory 248744 kb
Host smart-98c2ee5c-7524-481a-be31-9b9031603604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38482
69648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3848269648
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2603939044
Short name T703
Test name
Test status
Simulation time 48295900 ps
CPU time 3.14 seconds
Started May 16 02:15:33 PM PDT 24
Finished May 16 02:15:38 PM PDT 24
Peak memory 240560 kb
Host smart-d1fc47fa-c08c-40ce-9b83-206b856bc26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
39044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2603939044
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2148979447
Short name T681
Test name
Test status
Simulation time 12222149961 ps
CPU time 136.27 seconds
Started May 16 02:15:46 PM PDT 24
Finished May 16 02:18:04 PM PDT 24
Peak memory 256996 kb
Host smart-29f077a8-8b46-43db-87d0-06dffb95d28f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148979447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2148979447
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1485602985
Short name T687
Test name
Test status
Simulation time 128312556908 ps
CPU time 3622.59 seconds
Started May 16 02:15:45 PM PDT 24
Finished May 16 03:16:10 PM PDT 24
Peak memory 306004 kb
Host smart-099dbd1f-a076-430d-b7d1-7e40058a12a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485602985 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1485602985
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%