Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64278330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31152760

1

T1

10547

T2

130134

T3

106237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14492876	1			T1	4166		T2	50424		T3	42028
values[0x0]	39498555	1			T1	14694		T2	179958		T3	148100
values[0x1]	41439659	1			T1	15070		T2	179924		T3	147716

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54913734	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40517356

1

T1

13418

T2

164224

T3

134734

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	274764	1			T1	134		T2	1637		T3	1225
valid_sources[0x01]	273898	1			T1	128		T2	1590		T3	1262
valid_sources[0x02]	280554	1			T1	116		T2	1576		T3	1268
valid_sources[0x03]	660250	1			T1	131		T2	1657		T3	1372
valid_sources[0x04]	273285	1			T1	140		T2	1634		T3	1432
valid_sources[0x05]	608031	1			T1	154		T2	1567		T3	1300
valid_sources[0x06]	440704	1			T1	141		T2	1541		T3	1361
valid_sources[0x07]	283045	1			T1	124		T2	1634		T3	1334
valid_sources[0x08]	274789	1			T1	130		T2	1723		T3	1231
valid_sources[0x09]	268769	1			T1	129		T2	1620		T3	1342
valid_sources[0x0a]	281970	1			T1	152		T2	1592		T3	1226
valid_sources[0x0b]	715997	1			T1	170		T2	1576		T3	1346
valid_sources[0x0c]	694693	1			T1	123		T2	1609		T3	1251
valid_sources[0x0d]	279383	1			T1	110		T2	1685		T3	1263
valid_sources[0x0e]	272396	1			T1	124		T2	1624		T3	1267
valid_sources[0x0f]	275271	1			T1	132		T2	1695		T3	1274
valid_sources[0x10]	286630	1			T1	137		T2	1686		T3	1349
valid_sources[0x11]	286378	1			T1	131		T2	1584		T3	1342
valid_sources[0x12]	282976	1			T1	136		T2	1625		T3	1217
valid_sources[0x13]	282093	1			T1	131		T2	1656		T3	1259
valid_sources[0x14]	280552	1			T1	137		T2	1557		T3	1244
valid_sources[0x15]	278285	1			T1	137		T2	1606		T3	1431
valid_sources[0x16]	613089	1			T1	118		T2	1632		T3	1386
valid_sources[0x17]	280109	1			T1	111		T2	1573		T3	1455
valid_sources[0x18]	277099	1			T1	144		T2	1581		T3	1244
valid_sources[0x19]	1041918	1			T1	124		T2	1639		T3	1263
valid_sources[0x1a]	272426	1			T1	128		T2	1578		T3	1237
valid_sources[0x1b]	276614	1			T1	121		T2	1552		T3	1327
valid_sources[0x1c]	283851	1			T1	120		T2	1677		T3	1302
valid_sources[0x1d]	279930	1			T1	119		T2	1633		T3	1373
valid_sources[0x1e]	640756	1			T1	138		T2	1660		T3	1330
valid_sources[0x1f]	300012	1			T1	123		T2	1616		T3	1312
valid_sources[0x20]	277481	1			T1	133		T2	1540		T3	1277
valid_sources[0x21]	285107	1			T1	150		T2	1548		T3	1341
valid_sources[0x22]	278310	1			T1	131		T2	1538		T3	1390
valid_sources[0x23]	621343	1			T1	113		T2	1646		T3	1297
valid_sources[0x24]	289038	1			T1	127		T2	1680		T3	1271
valid_sources[0x25]	284018	1			T1	118		T2	1565		T3	1288
valid_sources[0x26]	277411	1			T1	108		T2	1657		T3	1296
valid_sources[0x27]	282120	1			T1	122		T2	1534		T3	1442
valid_sources[0x28]	285746	1			T1	113		T2	1542		T3	1297
valid_sources[0x29]	286951	1			T1	164		T2	1590		T3	1338
valid_sources[0x2a]	1203290	1			T1	129		T2	1616		T3	1507
valid_sources[0x2b]	841703	1			T1	139		T2	1608		T3	1326
valid_sources[0x2c]	271426	1			T1	140		T2	1543		T3	1318
valid_sources[0x2d]	304761	1			T1	110		T2	1677		T3	1405
valid_sources[0x2e]	276682	1			T1	135		T2	1600		T3	1372
valid_sources[0x2f]	501011	1			T1	114		T2	1577		T3	1336
valid_sources[0x30]	275570	1			T1	138		T2	1562		T3	1317
valid_sources[0x31]	280800	1			T1	116		T2	1634		T3	1291
valid_sources[0x32]	862689	1			T1	143		T2	1681		T3	1273
valid_sources[0x33]	283208	1			T1	127		T2	1621		T3	1327
valid_sources[0x34]	281357	1			T1	126		T2	1653		T3	1366
valid_sources[0x35]	273645	1			T1	141		T2	1615		T3	1240
valid_sources[0x36]	524839	1			T1	142		T2	1650		T3	1331
valid_sources[0x37]	317978	1			T1	106		T2	1588		T3	1331
valid_sources[0x38]	742347	1			T1	144		T2	1532		T3	1303
valid_sources[0x39]	285678	1			T1	137		T2	1653		T3	1303
valid_sources[0x3a]	276739	1			T1	141		T2	1522		T3	1331
valid_sources[0x3b]	289445	1			T1	130		T2	1501		T3	1334
valid_sources[0x3c]	270996	1			T1	124		T2	1639		T3	1169
valid_sources[0x3d]	281548	1			T1	133		T2	1602		T3	1312
valid_sources[0x3e]	279900	1			T1	149		T2	1570		T3	1275
valid_sources[0x3f]	273493	1			T1	121		T2	1677		T3	1225
valid_sources[0x40]	297569	1			T1	132		T2	1571		T3	1282
valid_sources[0x41]	717761	1			T1	132		T2	1587		T3	1474
valid_sources[0x42]	277029	1			T1	119		T2	1684		T3	1314
valid_sources[0x43]	273721	1			T1	119		T2	1523		T3	1268
valid_sources[0x44]	287058	1			T1	137		T2	1528		T3	1290
valid_sources[0x45]	1031604	1			T1	136		T2	1556		T3	1236
valid_sources[0x46]	278522	1			T1	152		T2	1585		T3	1335
valid_sources[0x47]	276567	1			T1	142		T2	1676		T3	1339
valid_sources[0x48]	271029	1			T1	131		T2	1590		T3	1336
valid_sources[0x49]	275120	1			T1	125		T2	1580		T3	1375
valid_sources[0x4a]	279290	1			T1	126		T2	1585		T3	1295
valid_sources[0x4b]	277184	1			T1	127		T2	1648		T3	1246
valid_sources[0x4c]	275262	1			T1	124		T2	1528		T3	1271
valid_sources[0x4d]	280059	1			T1	146		T2	1584		T3	1487
valid_sources[0x4e]	284082	1			T1	135		T2	1626		T3	1368
valid_sources[0x4f]	277064	1			T1	114		T2	1582		T3	1487
valid_sources[0x50]	281880	1			T1	150		T2	1581		T3	1307
valid_sources[0x51]	277495	1			T1	136		T2	1659		T3	1366
valid_sources[0x52]	279899	1			T1	115		T2	1575		T3	1279
valid_sources[0x53]	274793	1			T1	108		T2	1665		T3	1292
valid_sources[0x54]	272871	1			T1	140		T2	1521		T3	1340
valid_sources[0x55]	276180	1			T1	114		T2	1568		T3	1506
valid_sources[0x56]	294497	1			T1	132		T2	1593		T3	1342
valid_sources[0x57]	268988	1			T1	128		T2	1715		T3	1219
valid_sources[0x58]	277283	1			T1	122		T2	1507		T3	1251
valid_sources[0x59]	678150	1			T1	118		T2	1549		T3	1306
valid_sources[0x5a]	282954	1			T1	119		T2	1491		T3	1285
valid_sources[0x5b]	282341	1			T1	123		T2	1548		T3	1335
valid_sources[0x5c]	279250	1			T1	137		T2	1589		T3	1417
valid_sources[0x5d]	276947	1			T1	133		T2	1669		T3	1330
valid_sources[0x5e]	283999	1			T1	144		T2	1622		T3	1305
valid_sources[0x5f]	275991	1			T1	150		T2	1594		T3	1245
valid_sources[0x60]	854339	1			T1	146		T2	1647		T3	1315
valid_sources[0x61]	272807	1			T1	113		T2	1617		T3	1413
valid_sources[0x62]	273269	1			T1	132		T2	1551		T3	1233
valid_sources[0x63]	273895	1			T1	145		T2	1525		T3	1315
valid_sources[0x64]	282856	1			T1	136		T2	1681		T3	1281
valid_sources[0x65]	279785	1			T1	112		T2	1555		T3	1295
valid_sources[0x66]	302210	1			T1	127		T2	1687		T3	1316
valid_sources[0x67]	279856	1			T1	139		T2	1609		T3	1322
valid_sources[0x68]	276157	1			T1	113		T2	1635		T3	1326
valid_sources[0x69]	271030	1			T1	126		T2	1583		T3	1309
valid_sources[0x6a]	487017	1			T1	127		T2	1649		T3	1304
valid_sources[0x6b]	296920	1			T1	125		T2	1600		T3	1244
valid_sources[0x6c]	279184	1			T1	128		T2	1631		T3	1200
valid_sources[0x6d]	272822	1			T1	144		T2	1705		T3	1357
valid_sources[0x6e]	272625	1			T1	139		T2	1600		T3	1390
valid_sources[0x6f]	733765	1			T1	137		T2	1707		T3	1329
valid_sources[0x70]	282922	1			T1	117		T2	1542		T3	1323
valid_sources[0x71]	283104	1			T1	160		T2	1533		T3	1501
valid_sources[0x72]	281495	1			T1	116		T2	1547		T3	1327
valid_sources[0x73]	668839	1			T1	132		T2	1598		T3	1286
valid_sources[0x74]	281207	1			T1	149		T2	1599		T3	1280
valid_sources[0x75]	294504	1			T1	137		T2	1610		T3	1372
valid_sources[0x76]	295741	1			T1	130		T2	1622		T3	1246
valid_sources[0x77]	619026	1			T1	133		T2	1593		T3	1314
valid_sources[0x78]	291457	1			T1	130		T2	1572		T3	1375
valid_sources[0x79]	279659	1			T1	130		T2	1553		T3	1298
valid_sources[0x7a]	273247	1			T1	124		T2	1524		T3	1304
valid_sources[0x7b]	281282	1			T1	147		T2	1576		T3	1391
valid_sources[0x7c]	612369	1			T1	134		T2	1544		T3	1410
valid_sources[0x7d]	1033010	1			T1	150		T2	1595		T3	1338
valid_sources[0x7e]	745916	1			T1	134		T2	1497		T3	1297
valid_sources[0x7f]	274397	1			T1	138		T2	1578		T3	1284
valid_sources[0x80]	300329	1			T1	141		T2	1559		T3	1354

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7196666

1

T1

2049

T2

25168

T3

20969

values[0x0]

all_enables

biggest_size

15122266

1

T1

5495

T2

66790

T3

54647

values[0x1]

all_enables

biggest_size

8833828

1

T1

3003

T2

38176

T3

30621