Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T205,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14100	0	0
DisabledNoTrigBkwd_A	2147483647	851807	0	0
DisabledNoTrigFwd_A	2147483647	1560680371	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14100	0	0
T22	160826	0	0	0
T49	0	864	0	0
T62	254634	0	0	0
T63	74273	0	0	0
T68	0	439	0	0
T108	141847	0	0	0
T205	0	579	0	0
T206	0	344	0	0
T207	3106	764	0	0
T208	2913	589	0	0
T209	3596	1233	0	0
T210	0	635	0	0
T211	0	330	0	0
T212	0	1912	0	0
T213	0	216	0	0
T214	0	522	0	0
T215	0	678	0	0
T216	0	565	0	0
T217	0	486	0	0
T218	0	478	0	0
T219	0	366	0	0
T220	0	902	0	0
T221	0	1339	0	0
T222	0	859	0	0
T223	166018	0	0	0
T224	475354	0	0	0
T225	131450	0	0	0
T226	119766	0	0	0
T227	566280	0	0	0
T228	355587	0	0	0
T229	36694	0	0	0
T230	101453	0	0	0
T231	1190	0	0	0
T232	18092	0	0	0
T233	285912	0	0	0
T234	113145	0	0	0
T235	294764	0	0	0
T236	64786	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	851807	0	0
T1	625502	282	0	0
T2	1044372	807	0	0
T3	1286922	2824	0	0
T4	542264	17	0	0
T5	1056256	5462	0	0
T6	1482292	913	0	0
T13	2683088	9639	0	0
T14	451664	12138	0	0
T17	0	1	0	0
T18	291348	38	0	0
T19	1001100	106	0	0
T20	191716	4	0	0
T21	22730	7	0	0
T38	0	31	0	0
T44	66709	2	0	0
T45	0	103	0	0
T46	0	131	0	0
T47	0	4	0	0
T48	0	2705	0	0
T49	3768	0	0	0
T74	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1560680371	0	0
T1	1251004	642963	0	0
T2	1392496	697024	0	0
T3	1715896	864438	0	0
T4	542264	413489	0	0
T5	1056256	968401	0	0
T6	1482292	744729	0	0
T13	2683088	1583918	0	0
T18	388464	255566	0	0
T19	1001100	538792	0	0
T20	191716	126345	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T217
1	1	Covered	T1,T18,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696589930	1075	0	0
DisabledNoTrigBkwd_A	696589930	270887	0	0
DisabledNoTrigFwd_A	696589930	359214434	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1075	0	0
T208	2913	589	0	0
T217	0	486	0	0
T228	355587	0	0	0
T229	36694	0	0	0
T230	101453	0	0	0
T231	1190	0	0	0
T232	18092	0	0	0
T233	285912	0	0	0
T234	113145	0	0	0
T235	294764	0	0	0
T236	64786	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	270887	0	0
T1	312751	184	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	561	0	0
T6	370573	1	0	0
T13	670772	1836	0	0
T14	0	2290	0	0
T18	97116	12	0	0
T19	250275	0	0	0
T20	47929	3	0	0
T21	0	7	0	0
T44	0	2	0	0
T45	0	50	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	359214434	0	0
T1	312751	15542	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	108189	0	0
T5	264064	202319	0	0
T6	370573	370119	0	0
T13	670772	462608	0	0
T18	97116	63148	0	0
T19	250275	240001	0	0
T20	47929	15258	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T4
1	0	Covered	T1,T3,T18
1	1	Covered	T18,T4,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T222
1	1	Covered	T18,T4,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696589930	1623	0	0
DisabledNoTrigBkwd_A	696589930	195914	0	0
DisabledNoTrigFwd_A	696589930	401776977	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1623	0	0
T22	160826	0	0	0
T62	254634	0	0	0
T63	74273	0	0	0
T108	141847	0	0	0
T207	3106	764	0	0
T222	0	859	0	0
T223	166018	0	0	0
T224	475354	0	0	0
T225	131450	0	0	0
T226	119766	0	0	0
T227	566280	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	195914	0	0
T4	135566	12	0	0
T5	264064	23	0	0
T6	370573	0	0	0
T13	670772	2885	0	0
T14	451664	4121	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T38	0	31	0	0
T44	66709	0	0	0
T46	0	131	0	0
T47	0	4	0	0
T48	0	2705	0	0
T49	3768	0	0	0
T74	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	401776977	0	0
T1	312751	312671	0	0
T2	348124	344988	0	0
T3	428974	428966	0	0
T4	135566	87119	0	0
T5	264064	261359	0	0
T6	370573	370567	0	0
T13	670772	320183	0	0
T18	97116	92462	0	0
T19	250275	245102	0	0
T20	47929	28389	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T18,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T213,T215
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696589930	4846	0	0
DisabledNoTrigBkwd_A	696589930	190268	0	0
DisabledNoTrigFwd_A	696589930	389206465	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	4846	0	0
T92	121365	0	0	0
T115	281463	0	0	0
T209	3596	1233	0	0
T213	0	216	0	0
T215	0	678	0	0
T218	0	478	0	0
T220	0	902	0	0
T221	0	1339	0	0
T237	32136	0	0	0
T238	63337	0	0	0
T239	435506	0	0	0
T240	42899	0	0	0
T241	616481	0	0	0
T242	257643	0	0	0
T243	125932	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	190268	0	0
T2	348124	388	0	0
T3	428974	1292	0	0
T4	135566	4	0	0
T5	264064	1711	0	0
T6	370573	477	0	0
T13	670772	725	0	0
T14	0	4260	0	0
T18	97116	0	0	0
T19	250275	90	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	53	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	389206465	0	0
T1	312751	312671	0	0
T2	348124	1948	0	0
T3	428974	3235	0	0
T4	135566	111674	0	0
T5	264064	77449	0	0
T6	370573	2011	0	0
T13	670772	558474	0	0
T18	97116	97023	0	0
T19	250275	50524	0	0
T20	47929	34858	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T205,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696589930	6556	0	0
DisabledNoTrigBkwd_A	696589930	194738	0	0
DisabledNoTrigFwd_A	696589930	410482495	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	6556	0	0
T7	503370	0	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T17	930808	0	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T46	161435	0	0	0
T49	3768	864	0	0
T50	8014	0	0	0
T66	85019	0	0	0
T68	0	439	0	0
T205	0	579	0	0
T206	0	344	0	0
T210	0	635	0	0
T211	0	330	0	0
T212	0	1912	0	0
T214	0	522	0	0
T216	0	565	0	0
T219	0	366	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	194738	0	0
T1	312751	98	0	0
T2	348124	419	0	0
T3	428974	1532	0	0
T4	135566	1	0	0
T5	264064	3167	0	0
T6	370573	435	0	0
T13	670772	4193	0	0
T14	0	1467	0	0
T18	97116	26	0	0
T19	250275	16	0	0
T20	47929	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	410482495	0	0
T1	312751	2079	0	0
T2	348124	1969	0	0
T3	428974	3271	0	0
T4	135566	106507	0	0
T5	264064	427274	0	0
T6	370573	2032	0	0
T13	670772	242653	0	0
T18	97116	2933	0	0
T19	250275	3165	0	0
T20	47929	47840	0	0