Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T4,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T18,T4,T20
1	1	1	Covered	T4,T20,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T20,T13,T14
1	0	Covered	T20,T21,T14

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T20,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T20,T21,T14

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T22,T23,T24
1	1	Covered	T20,T13,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T3,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T4,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T4,T20,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T4,T20,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T13,T25,T26
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T17,T26,T27
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T13,T21,T28
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T13,T29,T26
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T4,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T4,T20,T5
TimeoutSt->Phase0St	172	Covered	T20,T13,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T27,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T21,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T29,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1075	0	0
CheckAccumTrig0_A	2147483647	2362	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1132	0	0
CheckEn_A	2147483647	1233641586	0	0
CheckPhase0_A	2147483647	2718	0	0
CheckPhase1_A	2147483647	2684	0	0
CheckPhase2_A	2147483647	2641	0	0
CheckPhase3_A	2147483647	2589	0	0
CheckTimeout0_A	2147483647	4144	0	0
CheckTimeoutSt1_A	2147483647	483682	0	0
CheckTimeoutSt2_A	2147483647	3721	0	0
CheckTimeoutStTrig_A	2147483647	294	0	0
ErrorStAllEscAsserted_A	2147483647	5837	0	0
ErrorStIsTerminal_A	2147483647	4877	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1075	0	0
T10	137456	275	0	0
T11	192156	113	0	0
T12	0	256	0	0
T34	0	167	0	0
T35	0	264	0	0
T36	60280	0	0	0
T37	271128	0	0	0
T38	123512	0	0	0
T39	405940	0	0	0
T40	104600	0	0	0
T41	1233300	0	0	0
T42	120208	0	0	0
T43	120536	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2362	0	0
T1	625502	1	0	0
T2	1044372	1	0	0
T3	1286922	1	0	0
T4	542264	3	0	0
T5	1056256	10	0	0
T6	1482292	3	0	0
T13	2683088	24	0	0
T14	451664	23	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	291348	1	0	0
T19	1001100	1	0	0
T20	191716	1	0	0
T21	22730	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	66709	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T7	503370	0	0	0
T13	670772	0	0	0
T14	903328	1	0	0
T15	650236	0	0	0
T16	261299	0	0	0
T20	47929	1	0	0
T21	11365	1	0	0
T23	0	1	0	0
T31	0	2	0	0
T44	133418	0	0	0
T45	137466	0	0	0
T46	161435	0	0	0
T49	7536	0	0	0
T50	8014	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	115502	1	0	0
T56	221005	1	0	0
T57	742709	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	85019	0	0	0
T67	25027	0	0	0
T68	1253	0	0	0
T69	134462	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1132	0	0
T2	348124	2	0	0
T3	428974	0	0	0
T4	271132	2	0	0
T5	1056256	2	0	0
T6	1482292	1	0	0
T13	2683088	20	0	0
T14	1354992	15	0	0
T15	650236	0	0	0
T17	0	3	0	0
T18	97116	0	0	0
T19	500550	1	0	0
T20	191716	3	0	0
T21	45460	2	0	0
T26	0	2	0	0
T39	0	3	0	0
T44	200127	2	0	0
T45	137466	0	0	0
T48	0	4	0	0
T49	11304	0	0	0
T50	0	2	0	0
T53	0	3	0	0
T66	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1233641586	0	0
T1	1251004	642961	0	0
T2	1392496	697024	0	0
T3	1715896	864438	0	0
T4	542264	364096	0	0
T5	1056256	1489838	0	0
T6	1482292	376590	0	0
T13	2683088	1192350	0	0
T18	388464	195282	0	0
T19	1001100	538790	0	0
T20	191716	126342	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2718	0	0
T1	625502	2	0	0
T2	1044372	4	0	0
T3	1286922	2	0	0
T4	542264	4	0	0
T5	1056256	12	0	0
T6	1482292	4	0	0
T13	2683088	38	0	0
T14	451664	31	0	0
T17	0	1	0	0
T18	291348	2	0	0
T19	1001100	3	0	0
T20	191716	4	0	0
T21	22730	3	0	0
T44	66709	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2684	0	0
T1	625502	2	0	0
T2	1044372	4	0	0
T3	1286922	2	0	0
T4	542264	4	0	0
T5	1056256	12	0	0
T6	1482292	4	0	0
T13	2683088	38	0	0
T14	451664	31	0	0
T17	0	1	0	0
T18	291348	2	0	0
T19	1001100	3	0	0
T20	191716	4	0	0
T21	22730	3	0	0
T44	66709	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T1	625502	2	0	0
T2	1044372	4	0	0
T3	1286922	2	0	0
T4	542264	4	0	0
T5	1056256	12	0	0
T6	1482292	4	0	0
T13	2683088	36	0	0
T14	451664	31	0	0
T17	0	1	0	0
T18	291348	2	0	0
T19	1001100	2	0	0
T20	191716	4	0	0
T21	22730	2	0	0
T44	66709	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2589	0	0
T1	625502	2	0	0
T2	1044372	4	0	0
T3	1286922	2	0	0
T4	542264	4	0	0
T5	1056256	12	0	0
T6	1482292	4	0	0
T13	2683088	33	0	0
T14	451664	31	0	0
T17	0	1	0	0
T18	291348	2	0	0
T19	1001100	2	0	0
T20	191716	4	0	0
T21	22730	2	0	0
T44	66709	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4144	0	0
T4	542264	6	0	0
T5	1056256	27	0	0
T6	1482292	0	0	0
T13	2683088	27	0	0
T14	1806656	80	0	0
T19	1001100	0	0	0
T20	191716	5	0	0
T21	45460	1	0	0
T39	0	1	0	0
T44	266836	1	0	0
T49	15072	0	0	0
T50	0	1	0	0
T70	0	12	0	0
T71	0	6	0	0
T74	0	5	0	0
T75	0	18	0	0
T76	0	8	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	483682	0	0
T4	542264	620	0	0
T5	1056256	2558	0	0
T6	1482292	0	0	0
T13	2683088	2965	0	0
T14	1806656	7969	0	0
T19	1001100	0	0	0
T20	191716	850	0	0
T21	45460	0	0	0
T36	0	109	0	0
T39	0	296	0	0
T44	266836	120	0	0
T49	15072	0	0	0
T70	0	2240	0	0
T71	0	414	0	0
T74	0	2488	0	0
T75	0	3808	0	0
T76	0	1282	0	0
T77	0	527	0	0
T78	0	144	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3721	0	0
T4	406698	3	0	0
T5	1056256	27	0	0
T6	1482292	0	0	0
T13	2683088	23	0	0
T14	1806656	75	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T19	750825	0	0	0
T20	143787	2	0	0
T21	45460	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T44	266836	1	0	0
T45	68733	0	0	0
T49	15072	0	0	0
T70	0	9	0	0
T71	0	6	0	0
T74	0	1	0	0
T75	0	18	0	0
T76	0	7	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	5	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	294	0	0
T5	528128	0	0	0
T6	741146	0	0	0
T7	1006740	0	0	0
T13	2683088	2	0	0
T14	1806656	2	0	0
T15	1300472	0	0	0
T16	522598	0	0	0
T20	95858	2	0	0
T21	45460	0	0	0
T26	0	5	0	0
T27	0	1	0	0
T30	0	4	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	266836	0	0	0
T45	274932	0	0	0
T49	15072	0	0	0
T50	16028	0	0	0
T53	0	2	0	0
T70	0	3	0	0
T73	0	1	0	0
T74	0	3	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5837	0	0
T10	137456	1450	0	0
T11	192156	740	0	0
T12	0	1425	0	0
T34	0	762	0	0
T35	0	1460	0	0
T36	60280	0	0	0
T37	271128	0	0	0
T38	123512	0	0	0
T39	405940	0	0	0
T40	104600	0	0	0
T41	1233300	0	0	0
T42	120208	0	0	0
T43	120536	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4877	0	0
T10	137456	1210	0	0
T11	192156	620	0	0
T12	0	1185	0	0
T34	0	642	0	0
T35	0	1220	0	0
T36	60280	0	0	0
T37	271128	0	0	0
T38	123512	0	0	0
T39	405940	0	0	0
T40	104600	0	0	0
T41	1233300	0	0	0
T42	120208	0	0	0
T43	120536	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1251004	1250684	0	0
T2	1392496	1392476	0	0
T3	1715896	1715864	0	0
T4	542264	541744	0	0
T5	1056256	1056112	0	0
T6	1482292	1482268	0	0
T13	2683088	2683032	0	0
T18	388464	388092	0	0
T19	1001100	1000804	0	0
T20	191716	191360	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1251004	1250684	0	0
T2	1392496	1392476	0	0
T3	1715896	1715864	0	0
T4	542264	541744	0	0
T5	1056256	1056112	0	0
T6	1482292	1482268	0	0
T13	2683088	2683032	0	0
T18	388464	388092	0	0
T19	1001100	1000804	0	0
T20	191716	191360	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T18,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T20,T5
1	0	1	Covered	T1,T4,T19
1	1	0	Covered	T4,T5,T13
1	1	1	Covered	T4,T20,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T20,T13,T14
1	0	Covered	T20,T21,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T20,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T21,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Not Covered
1	1	Covered	T20,T13,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T20,T5
1	Covered	T1,T13,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T20
1	Covered	T13,T14,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T5
1	Covered	T20,T5,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T5
1	Covered	T18,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T18,T13,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T18,T20
Phase1St	198	Covered	T1,T18,T20
Phase2St	215	Covered	T1,T18,T20
Phase3St	233	Covered	T1,T18,T20
TerminalSt	249	Covered	T1,T18,T20
TimeoutSt	159	Covered	T4,T20,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T18,T5
IdleSt->TimeoutSt	159	Covered	T4,T20,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T13,T60,T87
Phase0St->Phase1St	198	Covered	T1,T18,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T26,T31
Phase1St->Phase2St	215	Covered	T1,T18,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T13,T21,T28
Phase2St->Phase3St	233	Covered	T1,T18,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T33,T57
Phase3St->TerminalSt	249	Covered	T1,T18,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T5,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T20,T5
TimeoutSt->Phase0St	172	Covered	T20,T13,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T87,T88,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T18,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T18,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T31,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T18,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T18,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T21,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T18,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T18,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T33,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T18,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T18,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T5,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T18,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696589930	281	0	0
CheckAccumTrig0_A	696589930	802	0	0
CheckAccumTrig1_A	696589930	47	0	0
CheckClr_A	696589930	391	0	0
CheckEn_A	696415667	260232029	0	0
CheckPhase0_A	696589930	917	0	0
CheckPhase1_A	696589930	904	0	0
CheckPhase2_A	696589930	890	0	0
CheckPhase3_A	696589930	871	0	0
CheckTimeout0_A	696589930	1317	0	0
CheckTimeoutSt1_A	696589930	152753	0	0
CheckTimeoutSt2_A	696589930	1178	0	0
CheckTimeoutStTrig_A	696589930	88	0	0
ErrorStAllEscAsserted_A	696589930	1474	0	0
ErrorStIsTerminal_A	696589930	1234	0	0
EscStateOut_A	696414353	696341981	0	0
u_state_regs_A	696589930	696415233	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	281	0	0
T10	34364	75	0	0
T11	48039	21	0	0
T12	0	88	0	0
T34	0	41	0	0
T35	0	56	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	802	0	0
T1	312751	1	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	4	0	0
T6	370573	1	0	0
T13	670772	10	0	0
T14	0	5	0	0
T15	0	1	0	0
T18	97116	1	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	47	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	0	0	0
T14	451664	0	0	0
T15	325118	0	0	0
T20	47929	1	0	0
T21	11365	1	0	0
T31	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T50	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	391	0	0
T5	264064	2	0	0
T6	370573	0	0	0
T13	670772	4	0	0
T14	451664	3	0	0
T15	325118	0	0	0
T17	0	1	0	0
T20	47929	1	0	0
T21	11365	2	0	0
T39	0	1	0	0
T44	66709	1	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T50	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696415667	260232029	0	0
T1	312751	15542	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	108185	0	0
T5	264064	399277	0	0
T6	370573	1980	0	0
T13	670772	276223	0	0
T18	97116	2866	0	0
T19	250275	240000	0	0
T20	47929	15258	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	917	0	0
T1	312751	1	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	4	0	0
T6	370573	1	0	0
T13	670772	10	0	0
T14	0	7	0	0
T18	97116	1	0	0
T19	250275	0	0	0
T20	47929	2	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	904	0	0
T1	312751	1	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	4	0	0
T6	370573	1	0	0
T13	670772	10	0	0
T14	0	7	0	0
T18	97116	1	0	0
T19	250275	0	0	0
T20	47929	2	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	890	0	0
T1	312751	1	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	4	0	0
T6	370573	1	0	0
T13	670772	9	0	0
T14	0	7	0	0
T18	97116	1	0	0
T19	250275	0	0	0
T20	47929	2	0	0
T21	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	871	0	0
T1	312751	1	0	0
T2	348124	0	0	0
T3	428974	0	0	0
T4	135566	0	0	0
T5	264064	4	0	0
T6	370573	1	0	0
T13	670772	9	0	0
T14	0	7	0	0
T18	97116	1	0	0
T19	250275	0	0	0
T20	47929	2	0	0
T21	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1317	0	0
T4	135566	2	0	0
T5	264064	20	0	0
T6	370573	0	0	0
T13	670772	12	0	0
T14	451664	6	0	0
T19	250275	0	0	0
T20	47929	3	0	0
T21	11365	1	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T50	0	1	0	0
T70	0	7	0	0
T74	0	1	0	0
T75	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	152753	0	0
T4	135566	256	0	0
T5	264064	1875	0	0
T6	370573	0	0	0
T13	670772	1239	0	0
T14	451664	1565	0	0
T19	250275	0	0	0
T20	47929	421	0	0
T21	11365	0	0	0
T36	0	109	0	0
T39	0	165	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T70	0	1351	0	0
T74	0	921	0	0
T75	0	924	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1178	0	0
T4	135566	1	0	0
T5	264064	20	0	0
T6	370573	0	0	0
T13	670772	11	0	0
T14	451664	4	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T70	0	7	0	0
T71	0	1	0	0
T75	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	88	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	1	0	0
T14	451664	2	0	0
T15	325118	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T26	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T74	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1474	0	0
T10	34364	341	0	0
T11	48039	183	0	0
T12	0	370	0	0
T34	0	205	0	0
T35	0	375	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1234	0	0
T10	34364	281	0	0
T11	48039	153	0	0
T12	0	310	0	0
T34	0	175	0	0
T35	0	315	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696414353	696341981	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	696415233	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T13
1	0	1	Covered	T1,T3,T19
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T5,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T13
0	1	Covered	T13,T14,T74
1	0	Covered	T13,T71,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T71,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Not Covered
1	1	Covered	T13,T14,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T5,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T2,T3,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T1,T4,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T4,T5,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T4,T5,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T91,T92,T93
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T76,T94,T91
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T13,T95
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T17,T57
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T13
TimeoutSt->Phase0St	172	Covered	T13,T14,T74

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T74
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T92,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T76,T94,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T13,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T17,T57
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696589930	263	0	0
CheckAccumTrig0_A	696589930	516	0	0
CheckAccumTrig1_A	696589930	26	0	0
CheckClr_A	696589930	248	0	0
CheckEn_A	696415667	330701256	0	0
CheckPhase0_A	696589930	602	0	0
CheckPhase1_A	696589930	593	0	0
CheckPhase2_A	696589930	581	0	0
CheckPhase3_A	696589930	566	0	0
CheckTimeout0_A	696589930	1089	0	0
CheckTimeoutSt1_A	696589930	114439	0	0
CheckTimeoutSt2_A	696589930	993	0	0
CheckTimeoutStTrig_A	696589930	66	0	0
ErrorStAllEscAsserted_A	696589930	1423	0	0
ErrorStIsTerminal_A	696589930	1183	0	0
EscStateOut_A	696414353	696341981	0	0
u_state_regs_A	696589930	696415233	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	263	0	0
T10	34364	64	0	0
T11	48039	24	0	0
T12	0	63	0	0
T34	0	40	0	0
T35	0	72	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	516	0	0
T1	312751	1	0	0
T2	348124	3	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	2	0	0
T6	370573	1	0	0
T13	670772	11	0	0
T14	0	3	0	0
T18	97116	1	0	0
T19	250275	2	0	0
T20	47929	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	26	0	0
T7	503370	0	0	0
T13	670772	1	0	0
T14	451664	0	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T21	11365	0	0	0
T31	0	3	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T50	8014	0	0	0
T61	0	1	0	0
T71	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	6	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	248	0	0
T2	348124	2	0	0
T3	428974	0	0	0
T4	135566	1	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	9	0	0
T17	0	1	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T44	0	1	0	0
T50	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696415667	330701256	0	0
T1	312751	2079	0	0
T2	348124	1969	0	0
T3	428974	3271	0	0
T4	135566	106503	0	0
T5	264064	427272	0	0
T6	370573	2032	0	0
T13	670772	240404	0	0
T18	97116	2933	0	0
T19	250275	3165	0	0
T20	47929	47839	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	602	0	0
T1	312751	1	0	0
T2	348124	3	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	2	0	0
T6	370573	1	0	0
T13	670772	13	0	0
T14	0	5	0	0
T18	97116	1	0	0
T19	250275	2	0	0
T20	47929	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	593	0	0
T1	312751	1	0	0
T2	348124	3	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	2	0	0
T6	370573	1	0	0
T13	670772	13	0	0
T14	0	5	0	0
T18	97116	1	0	0
T19	250275	2	0	0
T20	47929	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	581	0	0
T1	312751	1	0	0
T2	348124	3	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	2	0	0
T6	370573	1	0	0
T13	670772	12	0	0
T14	0	5	0	0
T18	97116	1	0	0
T19	250275	1	0	0
T20	47929	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	566	0	0
T1	312751	1	0	0
T2	348124	3	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	2	0	0
T6	370573	1	0	0
T13	670772	10	0	0
T14	0	5	0	0
T18	97116	1	0	0
T19	250275	1	0	0
T20	47929	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1089	0	0
T4	135566	2	0	0
T5	264064	4	0	0
T6	370573	0	0	0
T13	670772	6	0	0
T14	451664	56	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T71	0	2	0	0
T74	0	2	0	0
T75	0	7	0	0
T76	0	6	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	114439	0	0
T4	135566	255	0	0
T5	264064	363	0	0
T6	370573	0	0	0
T13	670772	779	0	0
T14	451664	4229	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T71	0	119	0	0
T74	0	108	0	0
T75	0	1446	0	0
T76	0	967	0	0
T77	0	235	0	0
T78	0	144	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	993	0	0
T4	135566	1	0	0
T5	264064	4	0	0
T6	370573	0	0	0
T13	670772	4	0	0
T14	451664	54	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T26	0	1	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T75	0	7	0	0
T76	0	6	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	66	0	0
T7	503370	0	0	0
T13	670772	1	0	0
T14	451664	2	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T21	11365	0	0	0
T26	0	3	0	0
T30	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T50	8014	0	0	0
T53	0	2	0	0
T56	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T77	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1423	0	0
T10	34364	367	0	0
T11	48039	191	0	0
T12	0	331	0	0
T34	0	186	0	0
T35	0	348	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1183	0	0
T10	34364	307	0	0
T11	48039	161	0	0
T12	0	271	0	0
T34	0	156	0	0
T35	0	288	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696414353	696341981	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	696415233	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T18,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T18,T4,T20
1	0	1	Covered	T4,T19,T5
1	1	0	Covered	T18,T4,T20
1	1	1	Covered	T4,T20,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T13
0	1	Covered	T20,T74,T76
1	0	Covered	T14,T52,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T20,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T52,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T13
1	0	Covered	T22,T102
1	1	Covered	T20,T74,T76

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T20,T5,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T5,T13,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T4,T5,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T4,T13,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T20,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T13,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T20,T5
Phase1St	198	Covered	T4,T20,T5
Phase2St	215	Covered	T4,T20,T5
Phase3St	233	Covered	T4,T20,T5
TerminalSt	249	Covered	T4,T20,T5
TimeoutSt	159	Covered	T4,T20,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T4,T5,T13
IdleSt->TimeoutSt	159	Covered	T4,T20,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T31,T103
Phase0St->Phase1St	198	Covered	T4,T20,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T104,T105,T92
Phase1St->Phase2St	215	Covered	T4,T20,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T58,T106,T107
Phase2St->Phase3St	233	Covered	T4,T20,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T57,T106,T60
Phase3St->TerminalSt	249	Covered	T4,T20,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T20,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T20,T13
TimeoutSt->Phase0St	172	Covered	T20,T14,T74

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T14,T74
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T103,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T20,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T20,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T104,T105,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T20,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T20,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T58,T106,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T20,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T20,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T57,T106,T60
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T20,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T20,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T20,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T20,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696589930	267	0	0
CheckAccumTrig0_A	696589930	518	0	0
CheckAccumTrig1_A	696589930	18	0	0
CheckClr_A	696589930	251	0	0
CheckEn_A	696415667	329307575	0	0
CheckPhase0_A	696589930	589	0	0
CheckPhase1_A	696589930	581	0	0
CheckPhase2_A	696589930	574	0	0
CheckPhase3_A	696589930	564	0	0
CheckTimeout0_A	696589930	1087	0	0
CheckTimeoutSt1_A	696589930	132742	0	0
CheckTimeoutSt2_A	696589930	999	0	0
CheckTimeoutStTrig_A	696589930	68	0	0
ErrorStAllEscAsserted_A	696589930	1493	0	0
ErrorStIsTerminal_A	696589930	1253	0	0
EscStateOut_A	696414353	696341981	0	0
u_state_regs_A	696589930	696415233	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	267	0	0
T10	34364	76	0	0
T11	48039	27	0	0
T12	0	37	0	0
T34	0	50	0	0
T35	0	77	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	518	0	0
T4	135566	2	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	8	0	0
T14	451664	14	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	66709	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	18	0	0
T7	503370	0	0	0
T14	451664	1	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T23	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T46	161435	0	0	0
T49	3768	0	0	0
T50	8014	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	85019	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	251	0	0
T4	135566	1	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	3	0	0
T14	451664	10	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T26	0	1	0	0
T39	0	1	0	0
T44	66709	0	0	0
T48	0	1	0	0
T49	3768	0	0	0
T53	0	3	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696415667	329307575	0	0
T1	312751	312670	0	0
T2	348124	344988	0	0
T3	428974	428966	0	0
T4	135566	87115	0	0
T5	264064	616421	0	0
T6	370573	370567	0	0
T13	670772	320183	0	0
T18	97116	92461	0	0
T19	250275	245101	0	0
T20	47929	28388	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	589	0	0
T4	135566	2	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	8	0	0
T14	451664	15	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	581	0	0
T4	135566	2	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	8	0	0
T14	451664	15	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	574	0	0
T4	135566	2	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	8	0	0
T14	451664	15	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	564	0	0
T4	135566	2	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	8	0	0
T14	451664	15	0	0
T17	0	1	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	3768	0	0	0
T74	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1087	0	0
T4	135566	1	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	6	0	0
T14	451664	13	0	0
T19	250275	0	0	0
T20	47929	2	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T75	0	6	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	132742	0	0
T4	135566	34	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	738	0	0
T14	451664	1844	0	0
T19	250275	0	0	0
T20	47929	429	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T70	0	178	0	0
T71	0	50	0	0
T74	0	628	0	0
T75	0	1438	0	0
T76	0	113	0	0
T77	0	292	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	999	0	0
T4	135566	1	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	6	0	0
T14	451664	12	0	0
T19	250275	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T44	66709	0	0	0
T49	3768	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T75	0	6	0	0
T77	0	1	0	0
T79	0	5	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	68	0	0
T5	264064	0	0	0
T6	370573	0	0	0
T13	670772	0	0	0
T14	451664	0	0	0
T15	325118	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T26	0	2	0	0
T30	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1493	0	0
T10	34364	370	0	0
T11	48039	182	0	0
T12	0	360	0	0
T34	0	179	0	0
T35	0	402	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1253	0	0
T10	34364	310	0	0
T11	48039	152	0	0
T12	0	300	0	0
T34	0	149	0	0
T35	0	342	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696414353	696341981	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	696415233	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T20,T5
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T20,T5,T13
1	1	1	Covered	T4,T5,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T13
0	1	Covered	T13,T70,T74
1	0	Covered	T14,T39,T55

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T39,T55

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T23,T24
1	1	Covered	T13,T70,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T3,T20,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T20
1	Covered	T2,T4,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T5,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T5,T13,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T4,T5,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T4,T5,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T30,T31
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T109,T110
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T86,T31,T111
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T26,T112
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T20,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T13
TimeoutSt->Phase0St	172	Covered	T13,T70,T74

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T70
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T109,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T86,T31,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T112,T113
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T6,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696589930	264	0	0
CheckAccumTrig0_A	696589930	526	0	0
CheckAccumTrig1_A	696589930	26	0	0
CheckClr_A	696589930	242	0	0
CheckEn_A	696415667	313400726	0	0
CheckPhase0_A	696589930	610	0	0
CheckPhase1_A	696589930	606	0	0
CheckPhase2_A	696589930	596	0	0
CheckPhase3_A	696589930	588	0	0
CheckTimeout0_A	696589930	651	0	0
CheckTimeoutSt1_A	696589930	83748	0	0
CheckTimeoutSt2_A	696589930	551	0	0
CheckTimeoutStTrig_A	696589930	72	0	0
ErrorStAllEscAsserted_A	696589930	1447	0	0
ErrorStIsTerminal_A	696589930	1207	0	0
EscStateOut_A	696414353	696341981	0	0
u_state_regs_A	696589930	696415233	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	264	0	0
T10	34364	60	0	0
T11	48039	41	0	0
T12	0	68	0	0
T34	0	36	0	0
T35	0	59	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	526	0	0
T2	348124	1	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	2	0	0
T13	670772	6	0	0
T14	0	4	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	26	0	0
T31	0	1	0	0
T32	0	1	0	0
T55	115502	1	0	0
T56	221005	1	0	0
T57	742709	1	0	0
T67	25027	0	0	0
T68	1253	0	0	0
T69	134462	0	0	0
T92	0	1	0	0
T103	0	1	0	0
T112	0	3	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	126748	0	0	0
T117	62485	0	0	0
T118	170281	0	0	0
T119	13278	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	242	0	0
T5	264064	0	0	0
T6	370573	1	0	0
T13	670772	4	0	0
T14	451664	2	0	0
T15	325118	0	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T26	0	1	0	0
T39	0	1	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T48	0	3	0	0
T49	3768	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696415667	313400726	0	0
T1	312751	312670	0	0
T2	348124	1948	0	0
T3	428974	3235	0	0
T4	135566	62293	0	0
T5	264064	46868	0	0
T6	370573	2011	0	0
T13	670772	355540	0	0
T18	97116	97022	0	0
T19	250275	50524	0	0
T20	47929	34857	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	610	0	0
T2	348124	1	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	2	0	0
T13	670772	7	0	0
T14	0	4	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	606	0	0
T2	348124	1	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	2	0	0
T13	670772	7	0	0
T14	0	4	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	596	0	0
T2	348124	1	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	2	0	0
T13	670772	7	0	0
T14	0	4	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	588	0	0
T2	348124	1	0	0
T3	428974	1	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	2	0	0
T13	670772	6	0	0
T14	0	4	0	0
T18	97116	0	0	0
T19	250275	1	0	0
T20	47929	1	0	0
T21	11365	0	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	651	0	0
T4	135566	1	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	3	0	0
T14	451664	5	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T39	0	1	0	0
T44	66709	1	0	0
T49	3768	0	0	0
T70	0	4	0	0
T71	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	83748	0	0
T4	135566	75	0	0
T5	264064	320	0	0
T6	370573	0	0	0
T13	670772	209	0	0
T14	451664	331	0	0
T19	250275	0	0	0
T20	47929	0	0	0
T21	11365	0	0	0
T39	0	131	0	0
T44	66709	120	0	0
T49	3768	0	0	0
T70	0	711	0	0
T71	0	245	0	0
T74	0	831	0	0
T76	0	202	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	551	0	0
T5	264064	3	0	0
T6	370573	0	0	0
T13	670772	2	0	0
T14	451664	5	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T21	11365	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T44	66709	1	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T70	0	1	0	0
T71	0	3	0	0
T76	0	1	0	0
T77	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	72	0	0
T7	503370	0	0	0
T13	670772	1	0	0
T14	451664	0	0	0
T15	325118	0	0	0
T16	261299	0	0	0
T21	11365	0	0	0
T26	0	2	0	0
T27	0	1	0	0
T30	0	3	0	0
T44	66709	0	0	0
T45	68733	0	0	0
T49	3768	0	0	0
T50	8014	0	0	0
T53	0	2	0	0
T57	0	2	0	0
T70	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T120	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1447	0	0
T10	34364	372	0	0
T11	48039	184	0	0
T12	0	364	0	0
T34	0	192	0	0
T35	0	335	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	1207	0	0
T10	34364	312	0	0
T11	48039	154	0	0
T12	0	304	0	0
T34	0	162	0	0
T35	0	275	0	0
T36	15070	0	0	0
T37	67782	0	0	0
T38	30878	0	0	0
T39	101485	0	0	0
T40	26150	0	0	0
T41	308325	0	0	0
T42	30052	0	0	0
T43	30134	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696414353	696341981	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696589930	696415233	0	0
T1	312751	312671	0	0
T2	348124	348119	0	0
T3	428974	428966	0	0
T4	135566	135436	0	0
T5	264064	264028	0	0
T6	370573	370567	0	0
T13	670772	670758	0	0
T18	97116	97023	0	0
T19	250275	250201	0	0
T20	47929	47840	0	0