Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	65831	1			T8	5		T15	3194		T9	2
class_i[0x1]	56511	1			T17	375		T19	44		T7	3
class_i[0x2]	84786	1			T12	6		T8	9		T13	8
class_i[0x3]	45784	1			T17	4		T12	4		T7	9

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63682	1			T17	4		T19	16		T7	5
alert[0x1]	63290	1			T17	9		T19	3		T7	3
alert[0x2]	61666	1			T17	1		T19	5		T12	7
alert[0x3]	64274	1			T17	365		T19	20		T12	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

252629

1

T17

379

T19

44

T12

10

esc_ping_fail

283

1

T7

4

T8

5

T9

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63598	1			T17	4		T19	16		T7	3
esc_integrity_fail	alert[0x1]	63221	1			T17	9		T19	3		T7	2
esc_integrity_fail	alert[0x2]	61597	1			T17	1		T19	5		T12	7
esc_integrity_fail	alert[0x3]	64213	1			T17	365		T19	20		T12	3
esc_ping_fail	alert[0x0]	84	1			T7	2		T8	2		T9	1
esc_ping_fail	alert[0x1]	69	1			T7	1		T8	1		T9	4
esc_ping_fail	alert[0x2]	69	1			T8	1		T9	2		T291	1
esc_ping_fail	alert[0x3]	61	1			T7	1		T8	1		T9	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	65747	1			T15	3194		T32	440		T292	12
esc_integrity_fail	class_i[0x1]	56448	1			T17	375		T19	44		T24	92
esc_integrity_fail	class_i[0x2]	84724	1			T12	6		T8	9		T13	8
esc_integrity_fail	class_i[0x3]	45710	1			T17	4		T12	4		T7	8
esc_ping_fail	class_i[0x0]	84	1			T8	5		T9	2		T209	1
esc_ping_fail	class_i[0x1]	63	1			T7	3		T9	1		T303	6
esc_ping_fail	class_i[0x2]	62	1			T9	2		T303	1		T209	1
esc_ping_fail	class_i[0x3]	74	1			T7	1		T9	6		T291	3