Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	710213091	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	710213091	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	710213091	710029849	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	710213091	710029849	0	0
tb.dut.EdnKnownO_A	0	0	710213091	710029849	0	0
tb.dut.EscPKnownO_A	0	0	710213091	710029849	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	710213091	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	710213091	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	710213091	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	710213091	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	710213091	90	0	0
tb.dut.IrqAKnownO_A	0	0	710213091	710029849	0	0
tb.dut.IrqBKnownO_A	0	0	710213091	710029849	0	0
tb.dut.IrqCKnownO_A	0	0	710213091	710029849	0	0
tb.dut.IrqDKnownO_A	0	0	710213091	710029849	0	0
tb.dut.TlAReadyKnownO_A	0	0	710213091	710029849	0	0
tb.dut.TlDValidKnownO_A	0	0	710213091	710029849	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	731516868	3200978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	731516868	9797	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	731516868	9550	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	731516868	9663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	731516868	9681	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	731516868	9669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	731516868	9765	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	731516868	9601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	731516868	9754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	731516868	9587	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	731516868	9744	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	731516868	9594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	731516868	9676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	731516868	9666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	731516868	9725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	731516868	9878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	731516868	9865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	731516868	9644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	731516868	9821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	731516868	10028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	731516868	9777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	731516868	10113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	731516868	9637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	731516868	9602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	731516868	9938	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	731516868	9957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	731516868	10022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	731516868	9617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	731516868	9664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	731516868	9780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	731516868	9881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	731516868	9745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	731516868	9562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	731516868	9721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	731516868	9610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	731516868	10084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	731516868	9726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	731516868	9743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	731516868	9592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	731516868	9889	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	731516868	9951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	731516868	9915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	731516868	9973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	731516868	9918	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	731516868	9862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	731516868	9999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	731516868	9730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	731516868	9981	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	731516868	9809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	731516868	9720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	731516868	9811	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	731516868	9726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	731516868	9839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	731516868	9957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	731516868	9842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	731516868	9469	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	731516868	9683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	731516868	9996	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	731516868	9615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	731516868	9706	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	731516868	9838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	731516868	9631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	731516868	9926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	731516868	9686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	731516868	9849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	731516868	9722	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	731516868	9809	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	731516868	9741	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	731516868	9668	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	731516868	9772	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	731516868	19691	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	731516868	9734	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	731516868	9888	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	731516868	10026	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	731516868	9309	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	731516868	9760	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	731516868	9771	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	731516868	9692	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	731516868	9808	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	710213091	1844	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	710213091	214606	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	710213091	370835945	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	710213091	282	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	710213091	802	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	710213091	49	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	710213091	429	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	709862634	271929342	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	710213091	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	710213091	879	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	710213091	857	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	710213091	829	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	710213091	1158	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	710213091	140727	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	710213091	1048	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	710213091	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	710213091	1574	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	710213091	1304	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	709861016	709792939	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	710213091	710029849	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	710213091	4319	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	710213091	144221	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	710213091	412145554	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	710213091	337	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	710213091	479	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	710213091	18	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	710213091	185	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	709862634	323056327	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	710213091	531	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	710213091	523	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	710213091	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	710213091	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	710213091	710	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	710213091	119815	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	710213091	645	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	710213091	47	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	710213091	1566	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	710213091	1296	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	709861016	709792939	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	710213091	710029849	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	710213091	7063	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	710213091	186539	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	710213091	408066747	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	710213091	355	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	710213091	465	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	710213091	25	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	710213091	191	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	709862634	309777568	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	710213091	531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	710213091	522	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	710213091	513	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	710213091	507	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	710213091	679	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	710213091	86334	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	710213091	605	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	710213091	49	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	710213091	1664	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	710213091	1394	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	709861016	709792939	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	710213091	710029849	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	710213091	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	710213091	3243	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	710213091	214595	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	710213091	428023993	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	710213091	348	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	710213091	450	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	710213091	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	710213091	196	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	709862634	333651587	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	710213091	518	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	710213091	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	710213091	499	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	710213091	485	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	710213091	654	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	710213091	66763	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	710213091	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	710213091	49	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	710213091	1547	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	710213091	1277	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	709861016	709792939	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	710213091	710029849	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	731516868	132516872	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	731516868	730843798	0	0
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