Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	144	1			T1	1		T2	1		T19	1
index[0x1]	165	1			T4	1		T19	1		T22	1
index[0x2]	195	1			T3	1		T19	1		T31	2
index[0x3]	139	1			T17	1		T12	1		T95	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	208	1			T3	1		T19	1		T12	1
lens_less_than_1000[1]	106	1			T19	1		T95	1		T38	1
lens_less_than_1000[2]	88	1			T1	1		T38	1		T31	1
lens_less_than_1000[3]	86	1			T2	1		T17	1		T13	1
lens_less_than_1000[4]	55	1			T4	1		T13	1		T58	1
lens_less_than_1000[5]	29	1			T22	1		T26	1		T87	1
lens_less_than_1000[6]	33	1			T19	1		T14	1		T26	1
lens_less_than_1000[7]	19	1			T22	1		T24	1		T32	1
lens_less_than_1000[8]	8	1			T32	1		T264	1		T265	2
lens_less_than_1000[9]	4	1			T23	1		T44	1		T266	1
len_2	7	1			T26	1		T49	1		T105	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	37	1			T19	1		T60	1		T26	2
index[0x0]	lens_less_than_1000[1]	21	1			T32	1		T30	1		T81	1
index[0x0]	lens_less_than_1000[2]	22	1			T1	1		T32	10		T44	1
index[0x0]	lens_less_than_1000[3]	25	1			T2	1		T13	1		T30	1
index[0x0]	lens_less_than_1000[4]	8	1			T66	1		T267	1		T268	1
index[0x0]	lens_less_than_1000[5]	8	1			T254	1		T242	1		T269	1
index[0x0]	lens_less_than_1000[6]	13	1			T33	1		T77	2		T270	1
index[0x0]	lens_less_than_1000[7]	3	1			T22	1		T32	1		T271	1
index[0x0]	lens_less_than_1000[8]	4	1			T32	1		T264	1		T272	1
index[0x0]	lens_less_than_1000[9]	2	1			T266	1		T273	1		-	-
index[0x0]	len_2	1	1			T180	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	56	1			T31	1		T40	1		T32	1
index[0x1]	lens_less_than_1000[1]	23	1			T60	1		T26	1		T66	1
index[0x1]	lens_less_than_1000[2]	13	1			T38	1		T40	1		T274	1
index[0x1]	lens_less_than_1000[3]	26	1			T26	1		T66	1		T33	6
index[0x1]	lens_less_than_1000[4]	19	1			T4	1		T58	1		T43	1
index[0x1]	lens_less_than_1000[5]	9	1			T22	1		T87	1		T94	2
index[0x1]	lens_less_than_1000[6]	7	1			T19	1		T14	1		T26	1
index[0x1]	lens_less_than_1000[7]	9	1			T26	1		T44	1		T275	1
index[0x1]	lens_less_than_1000[8]	1	1			T276	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T23	1		-	-		-	-
index[0x1]	len_2	1	1			T26	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	73	1			T3	1		T31	1		T32	1
index[0x2]	lens_less_than_1000[1]	38	1			T19	1		T24	1		T32	2
index[0x2]	lens_less_than_1000[2]	21	1			T31	1		T9	1		T87	1
index[0x2]	lens_less_than_1000[3]	19	1			T32	1		T80	1		T277	1
index[0x2]	lens_less_than_1000[4]	20	1			T13	1		T67	1		T29	1
index[0x2]	lens_less_than_1000[5]	7	1			T278	1		T279	1		T56	1
index[0x2]	lens_less_than_1000[6]	9	1			T30	1		T33	1		T46	2
index[0x2]	lens_less_than_1000[7]	5	1			T24	1		T92	1		T280	1
index[0x2]	lens_less_than_1000[8]	1	1			T281	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T44	1		-	-		-	-
index[0x2]	len_2	1	1			T282	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	42	1			T12	1		T32	1		T68	1
index[0x3]	lens_less_than_1000[1]	24	1			T95	1		T38	1		T26	2
index[0x3]	lens_less_than_1000[2]	32	1			T26	1		T80	1		T217	1
index[0x3]	lens_less_than_1000[3]	16	1			T17	1		T66	1		T30	1
index[0x3]	lens_less_than_1000[4]	8	1			T26	1		T280	1		T283	1
index[0x3]	lens_less_than_1000[5]	5	1			T26	1		T94	1		T272	1
index[0x3]	lens_less_than_1000[6]	4	1			T284	1		T245	1		T285	1
index[0x3]	lens_less_than_1000[7]	2	1			T26	1		T232	1		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T265	2		-	-		-	-
index[0x3]	len_2	4	1			T49	1		T105	1		T272	1