Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T29	2		T33	2		T80	1
class_index[0x1]	47	1			T24	4		T25	1		T26	1
class_index[0x2]	49	1			T23	1		T25	1		T60	1
class_index[0x3]	49	1			T60	1		T26	3		T29	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	88	1			T23	1		T25	1		T60	1
intr_timeout_cnt[1]	35	1			T25	1		T26	3		T78	2
intr_timeout_cnt[2]	20	1			T44	1		T243	2		T102	1
intr_timeout_cnt[3]	11	1			T60	1		T77	2		T244	1
intr_timeout_cnt[4]	9	1			T80	2		T81	1		T176	1
intr_timeout_cnt[5]	14	1			T24	4		T33	1		T84	1
intr_timeout_cnt[6]	6	1			T29	1		T75	1		T245	1
intr_timeout_cnt[7]	8	1			T75	1		T51	1		T225	1
intr_timeout_cnt[8]	6	1			T29	1		T225	1		T246	1
intr_timeout_cnt[9]	9	1			T81	2		T247	1		T243	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	38	1			T29	1		T33	2		T77	1
class_index[0x0]	intr_timeout_cnt[1]	7	1			T44	1		T248	1		T249	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T243	1		T55	1		T250	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T80	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T57	1		T251	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T29	1		T242	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T225	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T81	2		T247	1		T252	1
class_index[0x1]	intr_timeout_cnt[0]	18	1			T25	1		T26	1		T33	1
class_index[0x1]	intr_timeout_cnt[1]	5	1			T80	1		T83	1		T253	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T232	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	2	1			T77	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T109	1		T254	1		T255	1
class_index[0x1]	intr_timeout_cnt[5]	7	1			T24	4		T98	1		T256	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T245	1		T232	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T75	1		T246	1		T257	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T248	1		T56	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T243	1		T258	1		T232	1
class_index[0x2]	intr_timeout_cnt[0]	16	1			T23	1		T60	1		T86	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T25	1		T78	2		T223	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T102	1		T242	1		T259	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T244	1		T102	2		T232	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T80	1		T81	1		T176	1
class_index[0x2]	intr_timeout_cnt[5]	5	1			T33	1		T84	1		T257	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T75	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T51	1		T260	1		T261	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T248	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T92	1		T33	1		T100	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T26	3		T80	2		T51	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T44	1		T243	1		T56	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T60	1		T262	1		T56	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T250	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T258	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T29	1		T225	1		T246	1
class_index[0x3]	intr_timeout_cnt[9]	2	1			T263	1		T232	1		-	-