Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347624	1			T1	31		T2	9		T3	1205
all_values[1]	347624	1			T1	31		T2	9		T3	1205
all_values[2]	347624	1			T1	31		T2	9		T3	1205
all_values[3]	347624	1			T1	31		T2	9		T3	1205

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691739

1

T1

70

T2

23

T3

2564

auto[1]

698757

1

T1

54

T2

13

T3

2256

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

838133

1

T1

64

T2

20

T3

2419

auto[1]

552363

1

T1

60

T2

16

T3

2401

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100329	1			T1	8		T2	5		T3	295
all_values[0]	auto[0]	auto[1]	72783	1			T1	8		T2	4		T3	293
all_values[0]	auto[1]	auto[0]	101469	1			T1	8		T3	309		T4	779
all_values[0]	auto[1]	auto[1]	73043	1			T1	7		T3	308		T4	1
all_values[1]	auto[0]	auto[0]	106253	1			T1	8		T2	2		T3	336
all_values[1]	auto[0]	auto[1]	66704	1			T1	8		T2	1		T3	336
all_values[1]	auto[1]	auto[0]	107847	1			T1	8		T2	3		T3	267
all_values[1]	auto[1]	auto[1]	66820	1			T1	7		T2	3		T3	266
all_values[2]	auto[0]	auto[0]	104829	1			T1	10		T2	4		T3	348
all_values[2]	auto[0]	auto[1]	67458	1			T1	9		T2	3		T3	339
all_values[2]	auto[1]	auto[0]	107494	1			T1	6		T2	1		T3	261
all_values[2]	auto[1]	auto[1]	67843	1			T1	6		T2	1		T3	257
all_values[3]	auto[0]	auto[0]	104624	1			T1	10		T2	2		T3	309
all_values[3]	auto[0]	auto[1]	68759	1			T1	9		T2	2		T3	308
all_values[3]	auto[1]	auto[0]	105288	1			T1	6		T2	3		T3	294
all_values[3]	auto[1]	auto[1]	68953	1			T1	6		T2	2		T3	294