Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347624	1			T1	31		T2	9		T3	1205
all_pins[1]	347624	1			T1	31		T2	9		T3	1205
all_pins[2]	347624	1			T1	31		T2	9		T3	1205
all_pins[3]	347624	1			T1	31		T2	9		T3	1205

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1113837	1			T1	98		T2	30		T3	3695
values[0x1]	276659	1			T1	26		T2	6		T3	1125
transitions[0x0=>0x1]	184783	1			T1	21		T2	5		T3	754
transitions[0x1=>0x0]	185035	1			T1	21		T2	5		T3	754

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274581	1			T1	24		T2	9		T3	897
all_pins[0]	values[0x1]	73043	1			T1	7		T3	308		T4	1
all_pins[0]	transitions[0x0=>0x1]	72491	1			T1	7		T3	308		T4	1
all_pins[0]	transitions[0x1=>0x0]	68653	1			T1	6		T2	2		T3	294
all_pins[1]	values[0x0]	280804	1			T1	24		T2	6		T3	939
all_pins[1]	values[0x1]	66820	1			T1	7		T2	3		T3	266
all_pins[1]	transitions[0x0=>0x1]	36512	1			T1	5		T2	3		T3	128
all_pins[1]	transitions[0x1=>0x0]	42735	1			T1	5		T3	170		T4	1
all_pins[2]	values[0x0]	279781	1			T1	25		T2	8		T3	948
all_pins[2]	values[0x1]	67843	1			T1	6		T2	1		T3	257
all_pins[2]	transitions[0x0=>0x1]	37629	1			T1	3		T3	148		T4	1
all_pins[2]	transitions[0x1=>0x0]	36606	1			T1	4		T2	2		T3	157
all_pins[3]	values[0x0]	278671	1			T1	25		T2	7		T3	911
all_pins[3]	values[0x1]	68953	1			T1	6		T2	2		T3	294
all_pins[3]	transitions[0x0=>0x1]	38151	1			T1	6		T2	2		T3	170
all_pins[3]	transitions[0x1=>0x0]	37041	1			T1	6		T2	1		T3	133