Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88150	1			T3	1137		T6	461		T12	362
accum_cnt_1000	214182	1			T3	1393		T4	970		T17	2
accum_cnt_100	25793	1			T3	89		T4	80		T6	37
accum_cnt_50	68847	1			T3	64		T4	48		T6	29
accum_cnt_10	184903	1			T1	70		T2	9		T3	23
accum_cnt_0	404176	1			T1	14		T2	11		T3	914

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256288	1			T1	21		T2	5		T3	905
class_index[0x1]	256288	1			T1	21		T2	5		T3	905
class_index[0x2]	256288	1			T1	21		T2	5		T3	905
class_index[0x3]	256288	1			T1	21		T2	5		T3	905

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25938	1			T3	362		T13	477		T73	727
class_index[0x0]	accum_cnt_1000	60467	1			T3	484		T36	13		T13	436
class_index[0x0]	accum_cnt_100	8060	1			T3	29		T36	16		T13	23
class_index[0x0]	accum_cnt_50	19821	1			T3	23		T18	5		T36	13
class_index[0x0]	accum_cnt_10	43743	1			T1	19		T3	6		T17	2
class_index[0x0]	accum_cnt_0	86992	1			T1	2		T2	5		T3	1
class_index[0x1]	accum_cnt_2000	20065	1			T3	438		T6	461		T15	133
class_index[0x1]	accum_cnt_1000	48854	1			T3	414		T17	2		T6	603
class_index[0x1]	accum_cnt_100	5615	1			T3	26		T6	37		T12	47
class_index[0x1]	accum_cnt_50	19687	1			T3	16		T6	29		T19	11
class_index[0x1]	accum_cnt_10	43660	1			T1	20		T2	5		T3	7
class_index[0x1]	accum_cnt_0	111633	1			T1	1		T3	4		T4	2
class_index[0x2]	accum_cnt_2000	20640	1			T3	337		T12	121		T40	41
class_index[0x2]	accum_cnt_1000	57836	1			T3	495		T12	565		T14	808
class_index[0x2]	accum_cnt_100	5403	1			T3	34		T12	34		T14	78
class_index[0x2]	accum_cnt_50	16091	1			T3	25		T12	24		T39	3
class_index[0x2]	accum_cnt_10	48414	1			T1	20		T2	4		T3	10
class_index[0x2]	accum_cnt_0	98802	1			T1	1		T2	1		T3	4
class_index[0x3]	accum_cnt_2000	21507	1			T12	241		T73	564		T87	224
class_index[0x3]	accum_cnt_1000	47025	1			T4	970		T12	450		T32	14
class_index[0x3]	accum_cnt_100	6715	1			T4	80		T12	24		T32	8
class_index[0x3]	accum_cnt_50	13248	1			T4	48		T19	11		T12	24
class_index[0x3]	accum_cnt_10	49086	1			T1	11		T4	23		T19	5
class_index[0x3]	accum_cnt_0	106749	1			T1	10		T2	5		T3	905