Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6078	1			T13	424		T15	188		T88	8
alert[0x1]	1665	1			T19	4		T12	9		T13	55
alert[0x2]	6068	1			T8	1		T13	3		T15	10
alert[0x3]	4839	1			T7	1		T9	1		T96	22
alert[0x4]	3092	1			T17	2		T12	45		T24	1
alert[0x5]	4121	1			T19	4		T12	10		T24	11
alert[0x6]	12216	1			T12	60		T8	1		T15	1
alert[0x7]	3710	1			T12	297		T13	82		T15	38
alert[0x8]	1790	1			T13	251		T15	32		T26	9
alert[0x9]	5902	1			T12	27		T88	6		T96	2234
alert[0xa]	6497	1			T15	63		T9	1		T30	23
alert[0xb]	2729	1			T15	131		T291	1		T79	70
alert[0xc]	4110	1			T7	1		T13	506		T32	117
alert[0xd]	7206	1			T13	57		T72	2		T33	16
alert[0xe]	4677	1			T13	991		T15	30		T9	1
alert[0xf]	7589	1			T12	81		T32	17		T26	110
alert[0x10]	6838	1			T13	26		T15	430		T9	1
alert[0x11]	3185	1			T12	87		T32	1		T26	944
alert[0x12]	5935	1			T32	2		T292	1		T29	1
alert[0x13]	8358	1			T8	1		T13	14		T9	1
alert[0x14]	7738	1			T12	82		T13	22		T15	19
alert[0x15]	3371	1			T13	28		T26	17		T33	920
alert[0x16]	3602	1			T8	1		T32	14		T30	1
alert[0x17]	10197	1			T12	48		T8	1		T13	11
alert[0x18]	6143	1			T13	66		T26	3		T72	12
alert[0x19]	3617	1			T12	19		T13	62		T60	1
alert[0x1a]	6824	1			T12	15		T15	15		T9	1
alert[0x1b]	13647	1			T15	47		T9	1		T88	7
alert[0x1c]	2759	1			T32	79		T26	310		T33	99
alert[0x1d]	6490	1			T13	38		T96	131		T293	1
alert[0x1e]	10608	1			T15	22		T32	29		T26	2300
alert[0x1f]	12083	1			T12	49		T15	49		T60	1
alert[0x20]	19272	1			T13	278		T60	2		T32	17
alert[0x21]	5143	1			T12	28		T13	142		T15	54
alert[0x22]	8422	1			T12	4		T15	57		T289	1
alert[0x23]	8845	1			T12	60		T7	1		T13	72
alert[0x24]	3431	1			T13	263		T32	1		T26	177
alert[0x25]	3178	1			T8	1		T15	112		T9	1
alert[0x26]	14100	1			T15	872		T9	1		T32	1
alert[0x27]	6685	1			T12	56		T15	620		T32	164
alert[0x28]	10797	1			T12	345		T15	498		T60	23
alert[0x29]	2980	1			T13	428		T32	1		T26	184
alert[0x2a]	2691	1			T12	97		T15	29		T32	1
alert[0x2b]	5514	1			T7	1		T13	131		T9	1
alert[0x2c]	4438	1			T12	23		T15	4		T9	1
alert[0x2d]	18174	1			T12	1		T38	4		T32	2
alert[0x2e]	3441	1			T12	84		T60	4		T26	41
alert[0x2f]	5890	1			T12	3		T13	114		T88	3
alert[0x30]	12618	1			T7	1		T60	11		T29	2
alert[0x31]	3678	1			T12	14		T13	386		T32	137
alert[0x32]	7598	1			T12	166		T13	609		T32	18
alert[0x33]	2647	1			T12	12		T26	3		T29	1
alert[0x34]	9545	1			T8	1		T29	1		T99	610
alert[0x35]	4877	1			T13	22		T26	1048		T72	3
alert[0x36]	3166	1			T60	14		T42	1		T79	34
alert[0x37]	4211	1			T12	112		T13	91		T60	3
alert[0x38]	3139	1			T32	119		T79	52		T80	145
alert[0x39]	7648	1			T12	239		T13	3		T24	6
alert[0x3a]	2885	1			T12	48		T13	25		T292	1
alert[0x3b]	16811	1			T19	2		T12	459		T7	1
alert[0x3c]	4515	1			T15	864		T33	138		T79	493
alert[0x3d]	4795	1			T13	75		T32	4		T96	59
alert[0x3e]	6631	1			T13	165		T15	18		T9	1
alert[0x3f]	5610	1			T12	23		T7	1		T9	1
alert[0x40]	8720	1			T12	106		T13	4		T15	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	138019	1			T17	2		T12	2704		T38	4
class_i[0x1]	39650	1			T7	7		T8	2		T13	5430
class_i[0x2]	67367	1			T19	4		T12	2		T13	4
class_i[0x3]	180743	1			T19	6		T12	3		T8	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

425057

1

T17

2

T19

10

T12

2709

alert_ping_fail

722

1

T7

7

T8

9

T9

20

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6070	1			T13	424		T15	188		T88	8
alert_integrity_fail	alert[0x1]	1648	1			T19	4		T12	9		T13	55
alert_integrity_fail	alert[0x2]	6060	1			T13	3		T15	10		T32	60
alert_integrity_fail	alert[0x3]	4828	1			T96	22		T44	63		T99	31
alert_integrity_fail	alert[0x4]	3079	1			T17	2		T12	45		T24	1
alert_integrity_fail	alert[0x5]	4111	1			T19	4		T12	10		T24	11
alert_integrity_fail	alert[0x6]	12202	1			T12	60		T15	1		T32	34
alert_integrity_fail	alert[0x7]	3702	1			T12	297		T13	82		T15	38
alert_integrity_fail	alert[0x8]	1778	1			T13	251		T15	32		T26	9
alert_integrity_fail	alert[0x9]	5895	1			T12	27		T88	6		T96	2234
alert_integrity_fail	alert[0xa]	6479	1			T15	63		T30	23		T80	57
alert_integrity_fail	alert[0xb]	2716	1			T15	131		T79	70		T80	170
alert_integrity_fail	alert[0xc]	4097	1			T13	506		T32	117		T79	309
alert_integrity_fail	alert[0xd]	7200	1			T13	57		T72	2		T33	16
alert_integrity_fail	alert[0xe]	4666	1			T13	991		T15	30		T72	3
alert_integrity_fail	alert[0xf]	7579	1			T12	81		T32	17		T26	110
alert_integrity_fail	alert[0x10]	6828	1			T13	26		T15	430		T79	69
alert_integrity_fail	alert[0x11]	3174	1			T12	87		T32	1		T26	944
alert_integrity_fail	alert[0x12]	5921	1			T32	2		T292	1		T29	1
alert_integrity_fail	alert[0x13]	8345	1			T13	14		T26	41		T79	363
alert_integrity_fail	alert[0x14]	7719	1			T12	82		T13	22		T15	19
alert_integrity_fail	alert[0x15]	3355	1			T13	28		T26	17		T33	920
alert_integrity_fail	alert[0x16]	3586	1			T32	14		T30	1		T33	10
alert_integrity_fail	alert[0x17]	10186	1			T12	48		T13	11		T26	1288
alert_integrity_fail	alert[0x18]	6129	1			T13	66		T26	3		T72	12
alert_integrity_fail	alert[0x19]	3608	1			T12	19		T13	62		T60	1
alert_integrity_fail	alert[0x1a]	6810	1			T12	15		T15	15		T96	60
alert_integrity_fail	alert[0x1b]	13628	1			T15	47		T88	7		T33	228
alert_integrity_fail	alert[0x1c]	2751	1			T32	79		T26	310		T33	99
alert_integrity_fail	alert[0x1d]	6478	1			T13	38		T96	131		T79	2504
alert_integrity_fail	alert[0x1e]	10597	1			T15	22		T32	29		T26	2300
alert_integrity_fail	alert[0x1f]	12070	1			T12	49		T15	49		T60	1
alert_integrity_fail	alert[0x20]	19266	1			T13	278		T60	2		T32	17
alert_integrity_fail	alert[0x21]	5132	1			T12	28		T13	142		T15	54
alert_integrity_fail	alert[0x22]	8414	1			T12	4		T15	57		T79	775
alert_integrity_fail	alert[0x23]	8834	1			T12	60		T13	72		T15	82
alert_integrity_fail	alert[0x24]	3420	1			T13	263		T32	1		T26	177
alert_integrity_fail	alert[0x25]	3167	1			T15	112		T32	9		T30	3
alert_integrity_fail	alert[0x26]	14086	1			T15	872		T32	1		T33	15
alert_integrity_fail	alert[0x27]	6677	1			T12	56		T15	620		T32	164
alert_integrity_fail	alert[0x28]	10787	1			T12	345		T15	498		T60	23
alert_integrity_fail	alert[0x29]	2973	1			T13	428		T32	1		T26	184
alert_integrity_fail	alert[0x2a]	2684	1			T12	97		T15	29		T32	1
alert_integrity_fail	alert[0x2b]	5505	1			T13	131		T30	1		T88	2
alert_integrity_fail	alert[0x2c]	4423	1			T12	23		T15	4		T96	44
alert_integrity_fail	alert[0x2d]	18156	1			T12	1		T38	4		T32	2
alert_integrity_fail	alert[0x2e]	3429	1			T12	84		T60	4		T26	41
alert_integrity_fail	alert[0x2f]	5875	1			T12	3		T13	114		T88	3
alert_integrity_fail	alert[0x30]	12610	1			T60	11		T29	2		T33	59
alert_integrity_fail	alert[0x31]	3667	1			T12	14		T13	386		T32	137
alert_integrity_fail	alert[0x32]	7590	1			T12	166		T13	609		T32	18
alert_integrity_fail	alert[0x33]	2638	1			T12	12		T26	3		T29	1
alert_integrity_fail	alert[0x34]	9534	1			T29	1		T99	610		T100	165
alert_integrity_fail	alert[0x35]	4862	1			T13	22		T26	1048		T72	3
alert_integrity_fail	alert[0x36]	3154	1			T60	14		T42	1		T79	34
alert_integrity_fail	alert[0x37]	4205	1			T12	112		T13	91		T60	3
alert_integrity_fail	alert[0x38]	3131	1			T32	119		T79	52		T80	145
alert_integrity_fail	alert[0x39]	7640	1			T12	239		T13	3		T24	6
alert_integrity_fail	alert[0x3a]	2878	1			T12	48		T13	25		T292	1
alert_integrity_fail	alert[0x3b]	16798	1			T19	2		T12	459		T60	17
alert_integrity_fail	alert[0x3c]	4501	1			T15	864		T33	138		T79	493
alert_integrity_fail	alert[0x3d]	4789	1			T13	75		T32	4		T96	59
alert_integrity_fail	alert[0x3e]	6621	1			T13	165		T15	18		T33	183
alert_integrity_fail	alert[0x3f]	5603	1			T12	23		T32	16		T26	53
alert_integrity_fail	alert[0x40]	8713	1			T12	106		T13	4		T15	1
alert_ping_fail	alert[0x0]	8	1			T291	2		T215	1		T294	1
alert_ping_fail	alert[0x1]	17	1			T215	1		T294	2		T295	2
alert_ping_fail	alert[0x2]	8	1			T8	1		T9	1		T296	1
alert_ping_fail	alert[0x3]	11	1			T7	1		T9	1		T297	1
alert_ping_fail	alert[0x4]	13	1			T294	1		T295	1		T298	1
alert_ping_fail	alert[0x5]	10	1			T9	1		T297	1		T299	1
alert_ping_fail	alert[0x6]	14	1			T8	1		T295	1		T300	2
alert_ping_fail	alert[0x7]	8	1			T286	1		T215	1		T301	1
alert_ping_fail	alert[0x8]	12	1			T291	2		T302	1		T299	1
alert_ping_fail	alert[0x9]	7	1			T303	1		T215	1		T302	1
alert_ping_fail	alert[0xa]	18	1			T9	1		T304	1		T295	2
alert_ping_fail	alert[0xb]	13	1			T291	1		T303	1		T295	1
alert_ping_fail	alert[0xc]	13	1			T7	1		T291	1		T305	1
alert_ping_fail	alert[0xd]	6	1			T304	1		T305	1		T299	1
alert_ping_fail	alert[0xe]	11	1			T9	1		T303	1		T296	1
alert_ping_fail	alert[0xf]	10	1			T293	1		T303	1		T284	1
alert_ping_fail	alert[0x10]	10	1			T9	1		T215	1		T294	1
alert_ping_fail	alert[0x11]	11	1			T293	1		T303	1		T283	1
alert_ping_fail	alert[0x12]	14	1			T304	1		T295	1		T296	1
alert_ping_fail	alert[0x13]	13	1			T8	1		T9	1		T289	1
alert_ping_fail	alert[0x14]	19	1			T9	1		T294	1		T304	1
alert_ping_fail	alert[0x15]	16	1			T293	1		T215	1		T284	1
alert_ping_fail	alert[0x16]	16	1			T8	1		T306	1		T283	1
alert_ping_fail	alert[0x17]	11	1			T8	1		T9	1		T291	1
alert_ping_fail	alert[0x18]	14	1			T209	1		T215	1		T295	2
alert_ping_fail	alert[0x19]	9	1			T294	1		T299	1		T307	1
alert_ping_fail	alert[0x1a]	14	1			T9	1		T305	1		T284	1
alert_ping_fail	alert[0x1b]	19	1			T9	1		T300	1		T302	1
alert_ping_fail	alert[0x1c]	8	1			T288	1		T303	1		T304	1
alert_ping_fail	alert[0x1d]	12	1			T293	1		T303	1		T297	1
alert_ping_fail	alert[0x1e]	11	1			T299	1		T306	1		T283	1
alert_ping_fail	alert[0x1f]	13	1			T286	1		T291	1		T303	1
alert_ping_fail	alert[0x20]	6	1			T209	1		T308	1		T309	1
alert_ping_fail	alert[0x21]	11	1			T310	1		T304	1		T284	1
alert_ping_fail	alert[0x22]	8	1			T289	1		T295	1		T296	1
alert_ping_fail	alert[0x23]	11	1			T7	1		T294	1		T295	1
alert_ping_fail	alert[0x24]	11	1			T303	1		T296	1		T300	1
alert_ping_fail	alert[0x25]	11	1			T8	1		T9	1		T304	1
alert_ping_fail	alert[0x26]	14	1			T9	1		T291	2		T209	1
alert_ping_fail	alert[0x27]	8	1			T291	1		T209	1		T307	1
alert_ping_fail	alert[0x28]	10	1			T294	1		T295	1		T299	1
alert_ping_fail	alert[0x29]	7	1			T293	1		T300	1		T297	1
alert_ping_fail	alert[0x2a]	7	1			T286	2		T303	1		T305	1
alert_ping_fail	alert[0x2b]	9	1			T7	1		T9	1		T304	1
alert_ping_fail	alert[0x2c]	15	1			T9	1		T215	1		T294	1
alert_ping_fail	alert[0x2d]	18	1			T293	1		T291	1		T294	1
alert_ping_fail	alert[0x2e]	12	1			T286	3		T215	1		T296	1
alert_ping_fail	alert[0x2f]	15	1			T291	1		T304	3		T295	2
alert_ping_fail	alert[0x30]	8	1			T7	1		T293	1		T215	1
alert_ping_fail	alert[0x31]	11	1			T291	1		T304	1		T300	1
alert_ping_fail	alert[0x32]	8	1			T291	1		T296	1		T311	1
alert_ping_fail	alert[0x33]	9	1			T293	1		T303	1		T284	1
alert_ping_fail	alert[0x34]	11	1			T8	1		T304	1		T297	2
alert_ping_fail	alert[0x35]	15	1			T215	1		T304	2		T284	2
alert_ping_fail	alert[0x36]	12	1			T304	1		T295	1		T296	1
alert_ping_fail	alert[0x37]	6	1			T294	1		T312	2		T313	1
alert_ping_fail	alert[0x38]	8	1			T313	1		T314	1		T308	2
alert_ping_fail	alert[0x39]	8	1			T9	1		T303	1		T300	2
alert_ping_fail	alert[0x3a]	7	1			T291	1		T304	1		T296	1
alert_ping_fail	alert[0x3b]	13	1			T7	1		T8	2		T9	2
alert_ping_fail	alert[0x3c]	14	1			T294	1		T305	1		T284	1
alert_ping_fail	alert[0x3d]	6	1			T300	1		T302	1		T301	1
alert_ping_fail	alert[0x3e]	10	1			T9	1		T303	1		T315	1
alert_ping_fail	alert[0x3f]	7	1			T7	1		T9	1		T316	1
alert_ping_fail	alert[0x40]	7	1			T295	1		T305	2		T317	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	137927	1			T17	2		T12	2704		T38	4
alert_integrity_fail	class_i[0x1]	39422	1			T13	5430		T15	1		T60	4
alert_integrity_fail	class_i[0x2]	67126	1			T19	4		T12	2		T13	4
alert_integrity_fail	class_i[0x3]	180582	1			T19	6		T12	3		T13	10
alert_ping_fail	class_i[0x0]	92	1			T293	2		T209	1		T294	1
alert_ping_fail	class_i[0x1]	228	1			T7	7		T8	2		T9	20
alert_ping_fail	class_i[0x2]	241	1			T286	7		T293	3		T289	2
alert_ping_fail	class_i[0x3]	161	1			T8	7		T293	1		T304	1