Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.38 99.56


Total test records in report: 829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1429292947 May 21 02:38:12 PM PDT 24 May 21 02:38:34 PM PDT 24 10727634 ps
T773 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1262101685 May 21 02:38:29 PM PDT 24 May 21 02:39:20 PM PDT 24 220643290 ps
T774 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2005155093 May 21 02:38:22 PM PDT 24 May 21 02:38:55 PM PDT 24 226995093 ps
T174 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1030776484 May 21 02:37:52 PM PDT 24 May 21 02:38:12 PM PDT 24 24008779 ps
T775 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2236938393 May 21 02:38:02 PM PDT 24 May 21 02:38:21 PM PDT 24 24150945 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.462333526 May 21 02:37:52 PM PDT 24 May 21 02:42:02 PM PDT 24 3415609759 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.311807888 May 21 02:38:07 PM PDT 24 May 21 02:38:29 PM PDT 24 20371495 ps
T778 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3034896923 May 21 02:37:59 PM PDT 24 May 21 02:38:41 PM PDT 24 1353735445 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.884792402 May 21 02:38:27 PM PDT 24 May 21 02:38:59 PM PDT 24 125416159 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1511982691 May 21 02:37:38 PM PDT 24 May 21 02:40:42 PM PDT 24 1708740674 ps
T781 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1910827112 May 21 02:38:22 PM PDT 24 May 21 02:38:52 PM PDT 24 74938450 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2519120190 May 21 02:37:39 PM PDT 24 May 21 02:38:03 PM PDT 24 105945481 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.478658042 May 21 02:37:39 PM PDT 24 May 21 02:38:03 PM PDT 24 654712895 ps
T784 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2762532094 May 21 02:38:33 PM PDT 24 May 21 02:39:06 PM PDT 24 8071726 ps
T785 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1798454525 May 21 02:37:50 PM PDT 24 May 21 02:41:04 PM PDT 24 2861661121 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2351474380 May 21 02:37:40 PM PDT 24 May 21 02:42:09 PM PDT 24 3387014946 ps
T787 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3581251151 May 21 02:38:06 PM PDT 24 May 21 02:38:30 PM PDT 24 26095803 ps
T140 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4173056186 May 21 02:38:00 PM PDT 24 May 21 02:43:32 PM PDT 24 4320433261 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.728607831 May 21 02:37:40 PM PDT 24 May 21 02:38:23 PM PDT 24 336384367 ps
T789 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2706114941 May 21 02:38:00 PM PDT 24 May 21 02:38:20 PM PDT 24 7702086 ps
T790 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3808777179 May 21 02:38:28 PM PDT 24 May 21 02:38:55 PM PDT 24 10109863 ps
T143 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1534675809 May 21 02:38:00 PM PDT 24 May 21 02:40:42 PM PDT 24 2177178688 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.784955350 May 21 02:37:52 PM PDT 24 May 21 02:38:23 PM PDT 24 754552626 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1393533070 May 21 02:37:50 PM PDT 24 May 21 02:38:11 PM PDT 24 21444087 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3620205262 May 21 02:38:19 PM PDT 24 May 21 02:38:46 PM PDT 24 62812062 ps
T794 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2683817385 May 21 02:38:12 PM PDT 24 May 21 02:38:42 PM PDT 24 513485883 ps
T795 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1740905072 May 21 02:38:05 PM PDT 24 May 21 02:38:26 PM PDT 24 13671293 ps
T147 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.86742281 May 21 02:37:40 PM PDT 24 May 21 02:53:28 PM PDT 24 48463438572 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.876735317 May 21 02:38:03 PM PDT 24 May 21 02:38:22 PM PDT 24 8467670 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.833902865 May 21 02:37:50 PM PDT 24 May 21 02:38:09 PM PDT 24 10327084 ps
T126 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1744550181 May 21 02:38:23 PM PDT 24 May 21 02:41:36 PM PDT 24 3806596942 ps
T138 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3165452762 May 21 02:38:18 PM PDT 24 May 21 02:44:28 PM PDT 24 10813912174 ps
T166 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3238486199 May 21 02:38:09 PM PDT 24 May 21 02:38:32 PM PDT 24 123871577 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.552640459 May 21 02:37:59 PM PDT 24 May 21 02:38:30 PM PDT 24 157836523 ps
T162 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.24512983 May 21 02:38:00 PM PDT 24 May 21 02:38:21 PM PDT 24 194402770 ps
T799 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1233725182 May 21 02:37:55 PM PDT 24 May 21 02:38:17 PM PDT 24 26771338 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4220440769 May 21 02:37:40 PM PDT 24 May 21 02:39:19 PM PDT 24 10442412107 ps
T801 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3778391722 May 21 02:38:29 PM PDT 24 May 21 02:38:57 PM PDT 24 21091852 ps
T802 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.331377567 May 21 02:38:27 PM PDT 24 May 21 02:38:54 PM PDT 24 10267872 ps
T803 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1060720565 May 21 02:38:16 PM PDT 24 May 21 02:39:00 PM PDT 24 1272189464 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3976058938 May 21 02:38:01 PM PDT 24 May 21 02:38:22 PM PDT 24 109094613 ps
T804 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3383386659 May 21 02:37:45 PM PDT 24 May 21 02:39:03 PM PDT 24 1131181609 ps
T805 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1354658543 May 21 02:38:27 PM PDT 24 May 21 02:38:54 PM PDT 24 9331101 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1064674585 May 21 02:38:00 PM PDT 24 May 21 02:38:41 PM PDT 24 328978882 ps
T807 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1264355256 May 21 02:38:33 PM PDT 24 May 21 02:39:06 PM PDT 24 9555730 ps
T146 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.557856217 May 21 02:37:48 PM PDT 24 May 21 02:42:44 PM PDT 24 4159999536 ps
T135 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2753031431 May 21 02:37:40 PM PDT 24 May 21 02:39:29 PM PDT 24 2143853975 ps
T136 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1756319087 May 21 02:37:58 PM PDT 24 May 21 02:45:45 PM PDT 24 7487161552 ps
T808 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1040422152 May 21 02:38:11 PM PDT 24 May 21 02:38:52 PM PDT 24 455820128 ps
T161 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1774757261 May 21 02:38:16 PM PDT 24 May 21 02:38:40 PM PDT 24 70956421 ps
T809 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1555874812 May 21 02:38:33 PM PDT 24 May 21 02:39:05 PM PDT 24 12258310 ps
T810 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3668813240 May 21 02:38:22 PM PDT 24 May 21 02:39:06 PM PDT 24 2411440194 ps
T811 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3737257724 May 21 02:38:34 PM PDT 24 May 21 02:39:06 PM PDT 24 27201756 ps
T812 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2471405979 May 21 02:38:05 PM PDT 24 May 21 02:38:45 PM PDT 24 1890703867 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2307739159 May 21 02:38:12 PM PDT 24 May 21 02:39:16 PM PDT 24 6083163132 ps
T148 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1081912205 May 21 02:38:05 PM PDT 24 May 21 02:43:44 PM PDT 24 17632071185 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3608021173 May 21 02:38:08 PM PDT 24 May 21 02:39:18 PM PDT 24 681609181 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.115683306 May 21 02:37:46 PM PDT 24 May 21 02:38:23 PM PDT 24 672564457 ps
T165 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2226457481 May 21 02:37:50 PM PDT 24 May 21 02:38:12 PM PDT 24 157273347 ps
T816 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4030032754 May 21 02:37:58 PM PDT 24 May 21 02:38:22 PM PDT 24 149131092 ps
T168 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2749710306 May 21 02:38:22 PM PDT 24 May 21 02:39:23 PM PDT 24 548270860 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.413660270 May 21 02:37:39 PM PDT 24 May 21 02:38:04 PM PDT 24 314345109 ps
T818 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3286424948 May 21 02:38:09 PM PDT 24 May 21 02:43:59 PM PDT 24 8637148956 ps
T169 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2293463662 May 21 02:38:11 PM PDT 24 May 21 02:38:59 PM PDT 24 183205647 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2119225266 May 21 02:38:10 PM PDT 24 May 21 02:38:57 PM PDT 24 2044581139 ps
T150 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4007543274 May 21 02:38:03 PM PDT 24 May 21 02:43:28 PM PDT 24 9013746142 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2674127581 May 21 02:38:06 PM PDT 24 May 21 02:38:39 PM PDT 24 178545778 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3730952716 May 21 02:38:15 PM PDT 24 May 21 02:38:45 PM PDT 24 110650925 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2800964643 May 21 02:38:11 PM PDT 24 May 21 02:38:40 PM PDT 24 92076119 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.566185044 May 21 02:38:06 PM PDT 24 May 21 02:38:31 PM PDT 24 255763778 ps
T175 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3554159544 May 21 02:38:05 PM PDT 24 May 21 02:38:28 PM PDT 24 298415967 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2279844925 May 21 02:38:21 PM PDT 24 May 21 02:38:47 PM PDT 24 9719717 ps
T825 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.861147829 May 21 02:37:43 PM PDT 24 May 21 02:41:34 PM PDT 24 3710869512 ps
T826 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4234390768 May 21 02:38:01 PM PDT 24 May 21 02:38:23 PM PDT 24 19407999 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1721660578 May 21 02:38:21 PM PDT 24 May 21 02:46:55 PM PDT 24 6422648549 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2095354610 May 21 02:37:53 PM PDT 24 May 21 02:38:15 PM PDT 24 215928173 ps
T828 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.336686689 May 21 02:37:44 PM PDT 24 May 21 02:38:12 PM PDT 24 145094685 ps
T149 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1115084199 May 21 02:37:55 PM PDT 24 May 21 02:41:40 PM PDT 24 3349872450 ps
T829 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1837146958 May 21 02:38:17 PM PDT 24 May 21 02:38:40 PM PDT 24 47661661 ps

Test location /workspace/coverage/default/49.alert_handler_random_classes.1086120627
Short name T1
Test name
Test status
Simulation time 3275084865 ps
CPU time 50.9 seconds
Started May 21 03:11:43 PM PDT 24
Finished May 21 03:12:34 PM PDT 24
Peak memory 256504 kb
Host smart-930e8e73-da17-4a0e-80d1-5508dcbf3e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
20627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1086120627
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1568351969
Short name T32
Test name
Test status
Simulation time 50196601295 ps
CPU time 3429.74 seconds
Started May 21 03:04:47 PM PDT 24
Finished May 21 04:02:00 PM PDT 24
Peak memory 300600 kb
Host smart-147de76a-b374-4bf5-bc46-a294365cd9c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568351969 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1568351969
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3449143000
Short name T5
Test name
Test status
Simulation time 431864811 ps
CPU time 23.44 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:05:11 PM PDT 24
Peak memory 270324 kb
Host smart-09405b5d-7edb-40e9-b86b-812accdbbd33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3449143000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3449143000
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2042496585
Short name T12
Test name
Test status
Simulation time 59584893750 ps
CPU time 1807.17 seconds
Started May 21 03:05:50 PM PDT 24
Finished May 21 03:35:59 PM PDT 24
Peak memory 273348 kb
Host smart-730dab44-1535-4381-ae23-2e00bc83275d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042496585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2042496585
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2118466289
Short name T115
Test name
Test status
Simulation time 116309550623 ps
CPU time 1119.29 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 265084 kb
Host smart-861be4a3-2135-4f40-8cbc-1568a9944dcf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118466289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2118466289
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2103123082
Short name T33
Test name
Test status
Simulation time 11524618877 ps
CPU time 1125.72 seconds
Started May 21 03:08:04 PM PDT 24
Finished May 21 03:26:51 PM PDT 24
Peak memory 289096 kb
Host smart-72fc173e-041f-454c-bcad-546f72a1245d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103123082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2103123082
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1739062461
Short name T15
Test name
Test status
Simulation time 13008813944 ps
CPU time 1183.49 seconds
Started May 21 03:08:41 PM PDT 24
Finished May 21 03:28:26 PM PDT 24
Peak memory 289264 kb
Host smart-db7cd562-3143-4335-86a2-ff36d1e39ded
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739062461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1739062461
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3210190658
Short name T127
Test name
Test status
Simulation time 17483539140 ps
CPU time 602.67 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 264972 kb
Host smart-3ee5a86a-05a6-43ca-9641-0514d313fe70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210190658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3210190658
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1364348094
Short name T96
Test name
Test status
Simulation time 147657006368 ps
CPU time 2166.23 seconds
Started May 21 03:08:16 PM PDT 24
Finished May 21 03:44:24 PM PDT 24
Peak memory 289288 kb
Host smart-6d433dd4-56c4-4232-b9dd-0e308c80a6a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364348094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1364348094
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.413851719
Short name T117
Test name
Test status
Simulation time 3040337570 ps
CPU time 171.69 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:41:16 PM PDT 24
Peak memory 271400 kb
Host smart-d100cd7c-fe0a-4ef8-8055-5e6f3ff2ec02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=413851719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.413851719
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.814844473
Short name T99
Test name
Test status
Simulation time 70851010094 ps
CPU time 2269.31 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:42:20 PM PDT 24
Peak memory 289024 kb
Host smart-55ade6a0-0da3-4c24-86b1-818cf2518657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814844473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.814844473
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.143082308
Short name T14
Test name
Test status
Simulation time 12330421166 ps
CPU time 959.99 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:20:45 PM PDT 24
Peak memory 273376 kb
Host smart-392fc3b9-f54d-4547-951d-bfe97abf15e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143082308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.143082308
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2625594769
Short name T421
Test name
Test status
Simulation time 76576589093 ps
CPU time 2106.05 seconds
Started May 21 03:11:41 PM PDT 24
Finished May 21 03:46:47 PM PDT 24
Peak memory 289560 kb
Host smart-88de3331-e454-44e0-a958-3799ab16dd4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625594769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2625594769
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2089365614
Short name T129
Test name
Test status
Simulation time 17040076449 ps
CPU time 606.22 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:48:32 PM PDT 24
Peak memory 265088 kb
Host smart-6ce339f3-7ec9-41ee-871f-c22d7374c5f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089365614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2089365614
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1632653410
Short name T125
Test name
Test status
Simulation time 1825357901 ps
CPU time 182.36 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:41:48 PM PDT 24
Peak memory 272292 kb
Host smart-38f29aae-5a5f-4bd2-a7b1-ed8a30165d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632653410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1632653410
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4069620437
Short name T9
Test name
Test status
Simulation time 68595685505 ps
CPU time 506.53 seconds
Started May 21 03:07:59 PM PDT 24
Finished May 21 03:16:26 PM PDT 24
Peak memory 248124 kb
Host smart-b33aebfe-6071-47a8-bbf9-b6aff059ced6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069620437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4069620437
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2232068636
Short name T114
Test name
Test status
Simulation time 5497848384 ps
CPU time 621.64 seconds
Started May 21 02:38:02 PM PDT 24
Finished May 21 02:48:42 PM PDT 24
Peak memory 273256 kb
Host smart-1046b562-4525-4e4e-b01c-75844f0d0b44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232068636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2232068636
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.915965017
Short name T286
Test name
Test status
Simulation time 46663444721 ps
CPU time 2689.61 seconds
Started May 21 03:07:47 PM PDT 24
Finished May 21 03:52:37 PM PDT 24
Peak memory 289260 kb
Host smart-39feb02f-f509-4df1-a10d-176e27189309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915965017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.915965017
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3175327336
Short name T341
Test name
Test status
Simulation time 21530348 ps
CPU time 1.42 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235628 kb
Host smart-8ebff138-9be9-46fe-a33d-1acfcfb8ad6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175327336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3175327336
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1630912660
Short name T62
Test name
Test status
Simulation time 1098071651 ps
CPU time 17.78 seconds
Started May 21 03:05:33 PM PDT 24
Finished May 21 03:05:53 PM PDT 24
Peak memory 248776 kb
Host smart-c59b4eb2-c2df-48ce-baa0-848071999023
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1630912660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1630912660
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1902288307
Short name T226
Test name
Test status
Simulation time 140883349728 ps
CPU time 2182.53 seconds
Started May 21 03:06:43 PM PDT 24
Finished May 21 03:43:07 PM PDT 24
Peak memory 270508 kb
Host smart-b62bc7e4-22d8-4664-b16e-80cc83ad3ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902288307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1902288307
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2921658079
Short name T346
Test name
Test status
Simulation time 949749652 ps
CPU time 8.07 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:38:33 PM PDT 24
Peak memory 239304 kb
Host smart-0bd32d14-2d71-4b6e-a027-e2f9829a7519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921658079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2921658079
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4173056186
Short name T140
Test name
Test status
Simulation time 4320433261 ps
CPU time 313.82 seconds
Started May 21 02:38:00 PM PDT 24
Finished May 21 02:43:32 PM PDT 24
Peak memory 265088 kb
Host smart-338bd241-5677-40b4-acc6-041db4a22df0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4173056186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4173056186
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1734791500
Short name T26
Test name
Test status
Simulation time 185197633178 ps
CPU time 4056.35 seconds
Started May 21 03:06:05 PM PDT 24
Finished May 21 04:13:43 PM PDT 24
Peak memory 297732 kb
Host smart-c5dc6e2d-8898-4b40-94aa-6b56e7e8a26b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734791500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1734791500
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3525766459
Short name T295
Test name
Test status
Simulation time 22095220647 ps
CPU time 459.18 seconds
Started May 21 03:07:17 PM PDT 24
Finished May 21 03:14:57 PM PDT 24
Peak memory 248192 kb
Host smart-d1165621-38a5-4ab3-a590-21f72b6ca114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525766459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3525766459
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2386364033
Short name T330
Test name
Test status
Simulation time 64968762051 ps
CPU time 1827.39 seconds
Started May 21 03:07:31 PM PDT 24
Finished May 21 03:37:59 PM PDT 24
Peak memory 270484 kb
Host smart-f7327e8a-4668-4a2a-afe5-a5d4c99852e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386364033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2386364033
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3349555240
Short name T130
Test name
Test status
Simulation time 4892036129 ps
CPU time 639.55 seconds
Started May 21 02:37:51 PM PDT 24
Finished May 21 02:48:48 PM PDT 24
Peak memory 265096 kb
Host smart-fa7150ad-bc3f-4cba-b165-de79d7a5e2a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349555240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3349555240
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.699298200
Short name T232
Test name
Test status
Simulation time 150318496489 ps
CPU time 7783.28 seconds
Started May 21 03:07:42 PM PDT 24
Finished May 21 05:18:21 PM PDT 24
Peak memory 338692 kb
Host smart-2b789bd9-c563-4654-9b52-ab58d631690c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699298200 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.699298200
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1396146239
Short name T163
Test name
Test status
Simulation time 447570429 ps
CPU time 3.03 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:16 PM PDT 24
Peak memory 236400 kb
Host smart-cdb629c7-8b62-44f1-a6fd-91538529934c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1396146239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1396146239
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3450084505
Short name T511
Test name
Test status
Simulation time 28146914496 ps
CPU time 582.93 seconds
Started May 21 03:05:10 PM PDT 24
Finished May 21 03:14:55 PM PDT 24
Peak memory 248196 kb
Host smart-cd1125cb-309e-4a54-9a21-898f9d37830f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450084505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3450084505
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3722567011
Short name T44
Test name
Test status
Simulation time 198845360701 ps
CPU time 3504.54 seconds
Started May 21 03:07:50 PM PDT 24
Finished May 21 04:06:16 PM PDT 24
Peak memory 304664 kb
Host smart-6bc3da33-d095-4744-944d-bace73279f68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722567011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3722567011
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.868700849
Short name T284
Test name
Test status
Simulation time 60019564959 ps
CPU time 531.48 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:13:37 PM PDT 24
Peak memory 248128 kb
Host smart-daf68854-0563-4ce2-9f37-b78c85ee13df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868700849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.868700849
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1746860733
Short name T53
Test name
Test status
Simulation time 631452320148 ps
CPU time 9416.32 seconds
Started May 21 03:05:54 PM PDT 24
Finished May 21 05:43:51 PM PDT 24
Peak memory 336152 kb
Host smart-9467878a-135d-4aba-b5b4-e1360282906b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746860733 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1746860733
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1252233156
Short name T2
Test name
Test status
Simulation time 996044863 ps
CPU time 17 seconds
Started May 21 03:10:30 PM PDT 24
Finished May 21 03:10:48 PM PDT 24
Peak memory 248816 kb
Host smart-99d4dce5-6ff1-4c99-bd85-202c9345eb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522
33156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1252233156
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.469407294
Short name T156
Test name
Test status
Simulation time 18121622 ps
CPU time 1.4 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235592 kb
Host smart-2ddc7dcf-69fe-471f-b08a-3c07d4bd9e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469407294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.469407294
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3515682967
Short name T308
Test name
Test status
Simulation time 12509001193 ps
CPU time 471.47 seconds
Started May 21 03:05:36 PM PDT 24
Finished May 21 03:13:29 PM PDT 24
Peak memory 247892 kb
Host smart-0273707a-7be8-485e-8d39-ee46baf56531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515682967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3515682967
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1662951839
Short name T339
Test name
Test status
Simulation time 144092000838 ps
CPU time 2352.42 seconds
Started May 21 03:09:47 PM PDT 24
Finished May 21 03:49:00 PM PDT 24
Peak memory 289084 kb
Host smart-fa80de7b-6b9a-4464-a06a-ecf362cac8f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662951839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1662951839
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2991743913
Short name T128
Test name
Test status
Simulation time 2135762130 ps
CPU time 151.62 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:41:27 PM PDT 24
Peak memory 256720 kb
Host smart-db271a3d-7a39-4fa7-b06a-f2bf594dffa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2991743913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2991743913
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.485311889
Short name T325
Test name
Test status
Simulation time 82743455020 ps
CPU time 1217.4 seconds
Started May 21 03:10:58 PM PDT 24
Finished May 21 03:31:17 PM PDT 24
Peak memory 266288 kb
Host smart-4b6443b8-67b4-47c6-9aa8-bf685ff7c1ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485311889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.485311889
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.557856217
Short name T146
Test name
Test status
Simulation time 4159999536 ps
CPU time 277.87 seconds
Started May 21 02:37:48 PM PDT 24
Finished May 21 02:42:44 PM PDT 24
Peak memory 265108 kb
Host smart-a6126bc2-6415-4cea-8ce5-1b9aa44664ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=557856217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.557856217
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.603391739
Short name T299
Test name
Test status
Simulation time 14724726567 ps
CPU time 482.71 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:12:49 PM PDT 24
Peak memory 248136 kb
Host smart-54b74d48-34e2-4fc7-9947-b441c4fa5e58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603391739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.603391739
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2428173728
Short name T80
Test name
Test status
Simulation time 96175654185 ps
CPU time 6590.14 seconds
Started May 21 03:10:41 PM PDT 24
Finished May 21 05:01:22 PM PDT 24
Peak memory 338448 kb
Host smart-a5d98131-12f7-40f3-a518-1e98cb61c5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428173728 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2428173728
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3383322847
Short name T170
Test name
Test status
Simulation time 272960809 ps
CPU time 4.83 seconds
Started May 21 02:38:26 PM PDT 24
Finished May 21 02:38:56 PM PDT 24
Peak memory 236508 kb
Host smart-38899482-dbd5-4e28-bfdc-68a788e2f889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3383322847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3383322847
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.477375304
Short name T248
Test name
Test status
Simulation time 335722797648 ps
CPU time 2728.65 seconds
Started May 21 03:06:32 PM PDT 24
Finished May 21 03:52:03 PM PDT 24
Peak memory 289724 kb
Host smart-7fe752eb-2fdd-46e0-b0b6-3444dd3b39f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477375304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.477375304
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.232115597
Short name T328
Test name
Test status
Simulation time 37822325732 ps
CPU time 2233.74 seconds
Started May 21 03:07:14 PM PDT 24
Finished May 21 03:44:29 PM PDT 24
Peak memory 273444 kb
Host smart-59a0e506-fefe-4cfb-a7cf-9fdce8e37d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232115597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.232115597
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1612682249
Short name T555
Test name
Test status
Simulation time 224926590977 ps
CPU time 3402.32 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 04:01:29 PM PDT 24
Peak memory 289320 kb
Host smart-6ce89f83-6e59-4fff-9f92-46dddac51939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612682249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1612682249
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3568934469
Short name T242
Test name
Test status
Simulation time 51911538659 ps
CPU time 3575.3 seconds
Started May 21 03:04:47 PM PDT 24
Finished May 21 04:04:25 PM PDT 24
Peak memory 298764 kb
Host smart-a1579e0b-1cc6-4cec-9d63-1a0a55797ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568934469 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3568934469
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.527852271
Short name T133
Test name
Test status
Simulation time 15784604480 ps
CPU time 1024.17 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 272488 kb
Host smart-e3f8520e-96e9-4402-ae7e-03ee6a217bc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527852271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.527852271
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4001151233
Short name T123
Test name
Test status
Simulation time 2189311268 ps
CPU time 269.03 seconds
Started May 21 02:38:20 PM PDT 24
Finished May 21 02:43:12 PM PDT 24
Peak memory 265064 kb
Host smart-d1a54a09-8dbf-402a-bfd7-3a9e32d0582d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001151233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4001151233
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.545873105
Short name T192
Test name
Test status
Simulation time 104087895 ps
CPU time 3.72 seconds
Started May 21 03:04:36 PM PDT 24
Finished May 21 03:04:42 PM PDT 24
Peak memory 248916 kb
Host smart-54334837-6eb4-4900-acf3-3d52c23dd44f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=545873105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.545873105
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1008342179
Short name T199
Test name
Test status
Simulation time 15175887 ps
CPU time 2.37 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:04:42 PM PDT 24
Peak memory 248964 kb
Host smart-ff41c05b-d1cf-4237-8245-127e5762a09d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1008342179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1008342179
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3989367786
Short name T208
Test name
Test status
Simulation time 146069728 ps
CPU time 3.84 seconds
Started May 21 03:05:40 PM PDT 24
Finished May 21 03:05:46 PM PDT 24
Peak memory 248932 kb
Host smart-1e7f608a-8f34-4f6e-918d-8d243856f905
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3989367786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3989367786
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1232278844
Short name T194
Test name
Test status
Simulation time 117408014 ps
CPU time 4.65 seconds
Started May 21 03:04:47 PM PDT 24
Finished May 21 03:04:54 PM PDT 24
Peak memory 248936 kb
Host smart-d293c41a-7ef0-4f63-93a6-ec9d2832a59b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1232278844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1232278844
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1115084199
Short name T149
Test name
Test status
Simulation time 3349872450 ps
CPU time 206.84 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:41:40 PM PDT 24
Peak memory 265068 kb
Host smart-51302bad-0155-465f-99d5-ec945cfb8713
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1115084199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1115084199
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3415565594
Short name T258
Test name
Test status
Simulation time 71423974805 ps
CPU time 4524.56 seconds
Started May 21 03:05:34 PM PDT 24
Finished May 21 04:21:49 PM PDT 24
Peak memory 298056 kb
Host smart-9e850c1e-3fab-496e-9461-774f1c1b9430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415565594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3415565594
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2157242590
Short name T278
Test name
Test status
Simulation time 17687809716 ps
CPU time 1433.92 seconds
Started May 21 03:05:38 PM PDT 24
Finished May 21 03:29:34 PM PDT 24
Peak memory 288696 kb
Host smart-00cfa95d-b3c2-404c-9eb3-d9944e104ea3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157242590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2157242590
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1459718642
Short name T260
Test name
Test status
Simulation time 181597810 ps
CPU time 13.59 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:06:00 PM PDT 24
Peak memory 254004 kb
Host smart-e8115ea5-9264-49b9-afec-da6cf29a05fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
18642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1459718642
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3294728041
Short name T266
Test name
Test status
Simulation time 253946179 ps
CPU time 13.01 seconds
Started May 21 03:05:58 PM PDT 24
Finished May 21 03:06:12 PM PDT 24
Peak memory 254632 kb
Host smart-d05a980e-4ca3-4578-8ca9-29375e7e50b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
28041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3294728041
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3787785551
Short name T225
Test name
Test status
Simulation time 145148293 ps
CPU time 9.62 seconds
Started May 21 03:06:44 PM PDT 24
Finished May 21 03:06:55 PM PDT 24
Peak memory 252864 kb
Host smart-eee19f4b-4c98-4956-90b5-8715d93279e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37877
85551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3787785551
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2241544056
Short name T250
Test name
Test status
Simulation time 440057635801 ps
CPU time 2115.55 seconds
Started May 21 03:07:47 PM PDT 24
Finished May 21 03:43:04 PM PDT 24
Peak memory 288948 kb
Host smart-ffa34c9b-b60d-44cf-9d81-bdc0e735797b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241544056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2241544056
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3195350831
Short name T160
Test name
Test status
Simulation time 614146024 ps
CPU time 39.55 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:39:25 PM PDT 24
Peak memory 240076 kb
Host smart-2d6fc46c-6a65-479e-9585-71f21eb6c723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3195350831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3195350831
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3677396350
Short name T154
Test name
Test status
Simulation time 205905387 ps
CPU time 9.6 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:42 PM PDT 24
Peak memory 236608 kb
Host smart-98c22a48-1892-499a-94c6-f25f7bf42e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3677396350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3677396350
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2771019577
Short name T23
Test name
Test status
Simulation time 357687510 ps
CPU time 14.8 seconds
Started May 21 03:06:13 PM PDT 24
Finished May 21 03:06:29 PM PDT 24
Peak memory 248800 kb
Host smart-90017077-42d5-4479-92d6-55dcdc37510b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
19577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2771019577
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.27710304
Short name T17
Test name
Test status
Simulation time 129014941 ps
CPU time 6.26 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:37 PM PDT 24
Peak memory 248780 kb
Host smart-c6dcadd0-a6dd-4554-b80c-fabaddc1e60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.27710304
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.943045944
Short name T122
Test name
Test status
Simulation time 12489116967 ps
CPU time 767.92 seconds
Started May 21 02:38:09 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 265260 kb
Host smart-6590c8cb-5a16-4a25-99a1-c02e8c216722
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943045944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.943045944
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.233732647
Short name T132
Test name
Test status
Simulation time 64270525320 ps
CPU time 937.77 seconds
Started May 21 02:38:23 PM PDT 24
Finished May 21 02:54:24 PM PDT 24
Peak memory 271356 kb
Host smart-3302113b-ed12-4932-a3a9-8e43172ffa1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233732647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.233732647
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.308210496
Short name T343
Test name
Test status
Simulation time 8066549 ps
CPU time 1.45 seconds
Started May 21 02:37:46 PM PDT 24
Finished May 21 02:38:05 PM PDT 24
Peak memory 235580 kb
Host smart-6d62165a-fd55-4306-b045-d3f5d9150e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=308210496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.308210496
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3311096743
Short name T75
Test name
Test status
Simulation time 3674932515 ps
CPU time 44.18 seconds
Started May 21 03:04:35 PM PDT 24
Finished May 21 03:05:21 PM PDT 24
Peak memory 247480 kb
Host smart-9cd5de4a-2d6e-4fa0-942b-6290fc90643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33110
96743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3311096743
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2156518340
Short name T77
Test name
Test status
Simulation time 561999073367 ps
CPU time 4287.72 seconds
Started May 21 03:04:35 PM PDT 24
Finished May 21 04:16:04 PM PDT 24
Peak memory 306288 kb
Host smart-f4f39a50-7c78-452f-b338-f98640a9f5bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156518340 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2156518340
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.610365351
Short name T306
Test name
Test status
Simulation time 32665712283 ps
CPU time 2171.73 seconds
Started May 21 03:05:19 PM PDT 24
Finished May 21 03:41:34 PM PDT 24
Peak memory 286724 kb
Host smart-e48a77ac-a516-4835-9159-d2df80b1a640
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610365351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.610365351
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1578119940
Short name T294
Test name
Test status
Simulation time 50541542389 ps
CPU time 422.13 seconds
Started May 21 03:05:21 PM PDT 24
Finished May 21 03:12:26 PM PDT 24
Peak memory 248232 kb
Host smart-71ec675e-aa0b-432f-b044-40b8c206140a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578119940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1578119940
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3387127886
Short name T627
Test name
Test status
Simulation time 25243279599 ps
CPU time 258.37 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:10:06 PM PDT 24
Peak memory 248204 kb
Host smart-4ed40e5e-92aa-4abb-9e59-b00273062958
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387127886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3387127886
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4092197717
Short name T24
Test name
Test status
Simulation time 2534167166 ps
CPU time 64.05 seconds
Started May 21 03:06:31 PM PDT 24
Finished May 21 03:07:37 PM PDT 24
Peak memory 255604 kb
Host smart-be65b720-9457-4a7a-8d31-8dd39c1ca125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
97717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4092197717
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.84821620
Short name T180
Test name
Test status
Simulation time 362436151 ps
CPU time 11.3 seconds
Started May 21 03:07:27 PM PDT 24
Finished May 21 03:07:39 PM PDT 24
Peak memory 256996 kb
Host smart-c8b0fb93-4ff4-4c54-87ce-484ff63695f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84821
620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.84821620
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.384107946
Short name T109
Test name
Test status
Simulation time 70915647843 ps
CPU time 6199.41 seconds
Started May 21 03:07:48 PM PDT 24
Finished May 21 04:51:09 PM PDT 24
Peak memory 348104 kb
Host smart-eb11013a-b185-4236-b445-d143299b1504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384107946 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.384107946
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2361198291
Short name T57
Test name
Test status
Simulation time 138420018503 ps
CPU time 982.1 seconds
Started May 21 03:08:14 PM PDT 24
Finished May 21 03:24:38 PM PDT 24
Peak memory 273360 kb
Host smart-5a1cf883-e64a-416e-b0bd-5b0f88d95ca0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361198291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2361198291
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.230452162
Short name T81
Test name
Test status
Simulation time 225281288337 ps
CPU time 2750.58 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:54:36 PM PDT 24
Peak memory 288792 kb
Host smart-a48e98f5-e02e-48bf-a73a-e7018f050731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230452162 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.230452162
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2489728538
Short name T276
Test name
Test status
Simulation time 30799172781 ps
CPU time 1830.79 seconds
Started May 21 03:09:42 PM PDT 24
Finished May 21 03:40:14 PM PDT 24
Peak memory 289180 kb
Host smart-9fe54329-4176-49c3-a558-539745e81de8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489728538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2489728538
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.776259954
Short name T281
Test name
Test status
Simulation time 42691846039 ps
CPU time 3025.2 seconds
Started May 21 03:09:43 PM PDT 24
Finished May 21 04:00:09 PM PDT 24
Peak memory 289964 kb
Host smart-677faa2a-da7e-41c4-a0bf-0db3f8b4a66a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776259954 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.776259954
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.9458492
Short name T265
Test name
Test status
Simulation time 1065118456 ps
CPU time 32.19 seconds
Started May 21 03:10:30 PM PDT 24
Finished May 21 03:11:04 PM PDT 24
Peak memory 247440 kb
Host smart-f198d39f-2622-47b9-b8ed-26eb1bb8c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94584
92 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.9458492
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2511399194
Short name T282
Test name
Test status
Simulation time 22091096406 ps
CPU time 1157.96 seconds
Started May 21 03:10:58 PM PDT 24
Finished May 21 03:30:17 PM PDT 24
Peak memory 266280 kb
Host smart-1d733135-8f85-4997-8be1-6c26d88c64e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511399194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2511399194
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.186672584
Short name T139
Test name
Test status
Simulation time 16825414545 ps
CPU time 324.13 seconds
Started May 21 02:38:14 PM PDT 24
Finished May 21 02:43:59 PM PDT 24
Peak memory 273164 kb
Host smart-b31a0d25-724a-4a29-9395-cfda14954e92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=186672584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.186672584
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2395886673
Short name T19
Test name
Test status
Simulation time 1043699476 ps
CPU time 23.09 seconds
Started May 21 03:11:38 PM PDT 24
Finished May 21 03:12:02 PM PDT 24
Peak memory 256024 kb
Host smart-76906a9c-0f8b-45a1-8715-a4a276c10a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
86673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2395886673
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.294223519
Short name T158
Test name
Test status
Simulation time 164082998 ps
CPU time 21.49 seconds
Started May 21 02:37:41 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 236936 kb
Host smart-78499ca9-b0fb-441a-a706-5fb19326dfb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=294223519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.294223519
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.24512983
Short name T162
Test name
Test status
Simulation time 194402770 ps
CPU time 3.04 seconds
Started May 21 02:38:00 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 236784 kb
Host smart-624879bd-e61a-4936-bfd3-ca5eab77e05b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=24512983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.24512983
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3300671071
Short name T131
Test name
Test status
Simulation time 3763743128 ps
CPU time 115.86 seconds
Started May 21 02:38:03 PM PDT 24
Finished May 21 02:40:18 PM PDT 24
Peak memory 265172 kb
Host smart-1b68e076-abd6-48ae-9086-34722a956e58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3300671071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3300671071
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2293463662
Short name T169
Test name
Test status
Simulation time 183205647 ps
CPU time 26.87 seconds
Started May 21 02:38:11 PM PDT 24
Finished May 21 02:38:59 PM PDT 24
Peak memory 240044 kb
Host smart-02aefc20-e527-48a9-a5da-6f0b7c726464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2293463662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2293463662
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1297332899
Short name T137
Test name
Test status
Simulation time 37346626199 ps
CPU time 321.32 seconds
Started May 21 02:38:11 PM PDT 24
Finished May 21 02:43:53 PM PDT 24
Peak memory 265080 kb
Host smart-f178e1df-a575-41d7-bfef-904617dcff13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1297332899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1297332899
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1241920039
Short name T152
Test name
Test status
Simulation time 33141700 ps
CPU time 2.33 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 236872 kb
Host smart-74c91457-ce72-46cb-b1e2-903f62113f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1241920039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1241920039
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1390935605
Short name T164
Test name
Test status
Simulation time 100114266 ps
CPU time 2.84 seconds
Started May 21 02:37:45 PM PDT 24
Finished May 21 02:38:05 PM PDT 24
Peak memory 236540 kb
Host smart-3e2c8847-177e-473f-8f8e-57ed46abb4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1390935605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1390935605
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3238486199
Short name T166
Test name
Test status
Simulation time 123871577 ps
CPU time 2.38 seconds
Started May 21 02:38:09 PM PDT 24
Finished May 21 02:38:32 PM PDT 24
Peak memory 236540 kb
Host smart-5acf8cdd-246a-49b6-839c-1ec5b4ba43c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3238486199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3238486199
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3382005627
Short name T153
Test name
Test status
Simulation time 23166897 ps
CPU time 2.51 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:38:28 PM PDT 24
Peak memory 235576 kb
Host smart-e8510e38-4b32-41d3-a0a4-7a6fd8136264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3382005627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3382005627
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.696229802
Short name T725
Test name
Test status
Simulation time 178197994 ps
CPU time 7.51 seconds
Started May 21 02:38:13 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 240056 kb
Host smart-b196cde7-2a70-47e4-9f9c-b5993287bde5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=696229802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.696229802
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1774757261
Short name T161
Test name
Test status
Simulation time 70956421 ps
CPU time 2.74 seconds
Started May 21 02:38:16 PM PDT 24
Finished May 21 02:38:40 PM PDT 24
Peak memory 236540 kb
Host smart-5bf1e7cb-2b00-4cf4-994b-96cc2d8077f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1774757261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1774757261
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.410248138
Short name T159
Test name
Test status
Simulation time 36402469 ps
CPU time 2.17 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 236852 kb
Host smart-e2d97de4-c6fe-4d18-a3ec-f055d0a1cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=410248138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.410248138
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2749710306
Short name T168
Test name
Test status
Simulation time 548270860 ps
CPU time 37.5 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:39:23 PM PDT 24
Peak memory 236912 kb
Host smart-62ff290b-907b-483a-94a5-20510705fe86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2749710306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2749710306
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1030776484
Short name T174
Test name
Test status
Simulation time 24008779 ps
CPU time 2.62 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:38:12 PM PDT 24
Peak memory 236652 kb
Host smart-1b10527c-b000-4f47-a72d-d64fbcff62d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1030776484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1030776484
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2226457481
Short name T165
Test name
Test status
Simulation time 157273347 ps
CPU time 3.85 seconds
Started May 21 02:37:50 PM PDT 24
Finished May 21 02:38:12 PM PDT 24
Peak memory 236508 kb
Host smart-3614f065-81c0-4258-af8a-e5a7ac77e377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2226457481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2226457481
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3554159544
Short name T175
Test name
Test status
Simulation time 298415967 ps
CPU time 2.78 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:38:28 PM PDT 24
Peak memory 236376 kb
Host smart-9b5d7565-b76f-40f4-ad56-d57fdf3401f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3554159544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3554159544
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3669092669
Short name T28
Test name
Test status
Simulation time 38649303967 ps
CPU time 1347.42 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:28:24 PM PDT 24
Peak memory 273400 kb
Host smart-2cae64af-9940-4854-98c7-bbbc7d6fc15b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669092669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3669092669
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2296380105
Short name T27
Test name
Test status
Simulation time 66145485475 ps
CPU time 5572.93 seconds
Started May 21 03:07:26 PM PDT 24
Finished May 21 04:40:22 PM PDT 24
Peak memory 321712 kb
Host smart-2d1515af-a174-42a5-bc03-d00350e494d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296380105 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2296380105
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1137670079
Short name T25
Test name
Test status
Simulation time 1534684065 ps
CPU time 43.74 seconds
Started May 21 03:07:39 PM PDT 24
Finished May 21 03:08:23 PM PDT 24
Peak memory 255964 kb
Host smart-f7b3024c-b015-4a8c-a556-4de4a810c34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
70079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1137670079
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2034122386
Short name T188
Test name
Test status
Simulation time 6980081492 ps
CPU time 108.33 seconds
Started May 21 02:37:39 PM PDT 24
Finished May 21 02:39:46 PM PDT 24
Peak memory 236688 kb
Host smart-588bf80a-e54f-44e0-b1b8-eb612ab67ecb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2034122386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2034122386
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.861147829
Short name T825
Test name
Test status
Simulation time 3710869512 ps
CPU time 212.86 seconds
Started May 21 02:37:43 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 235668 kb
Host smart-10ff9a83-e7ec-4ce1-8c4b-a5cae801f550
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=861147829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.861147829
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2292785430
Short name T759
Test name
Test status
Simulation time 126861476 ps
CPU time 10.61 seconds
Started May 21 02:37:41 PM PDT 24
Finished May 21 02:38:11 PM PDT 24
Peak memory 240040 kb
Host smart-7625b1ac-e948-4345-844d-f39ebb5c4d42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2292785430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2292785430
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4017907736
Short name T752
Test name
Test status
Simulation time 135285615 ps
CPU time 6.23 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:05 PM PDT 24
Peak memory 236616 kb
Host smart-0af83ae2-f982-4d0b-9144-b69d172fb18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017907736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4017907736
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.413660270
Short name T817
Test name
Test status
Simulation time 314345109 ps
CPU time 6.13 seconds
Started May 21 02:37:39 PM PDT 24
Finished May 21 02:38:04 PM PDT 24
Peak memory 240044 kb
Host smart-dbd876bf-4714-4c9c-ba23-5d99ab833780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=413660270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.413660270
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.553568341
Short name T754
Test name
Test status
Simulation time 8008703 ps
CPU time 1.53 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:00 PM PDT 24
Peak memory 234560 kb
Host smart-d4c48138-3613-48f9-b17d-01cbc85dcb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=553568341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.553568341
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.728607831
Short name T788
Test name
Test status
Simulation time 336384367 ps
CPU time 23.94 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:23 PM PDT 24
Peak memory 244692 kb
Host smart-abacec42-20a6-4b75-8523-5632caec5834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=728607831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.728607831
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2753031431
Short name T135
Test name
Test status
Simulation time 2143853975 ps
CPU time 89.74 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:39:29 PM PDT 24
Peak memory 256836 kb
Host smart-bb745a69-15f3-4190-b577-2c934873fcd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2753031431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2753031431
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3058728169
Short name T145
Test name
Test status
Simulation time 11020894816 ps
CPU time 342.85 seconds
Started May 21 02:37:41 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 265072 kb
Host smart-a1659776-989d-4e9c-a15c-d89f24395086
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058728169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3058728169
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1536135327
Short name T767
Test name
Test status
Simulation time 256943817 ps
CPU time 13.96 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:12 PM PDT 24
Peak memory 248336 kb
Host smart-e0455f0f-09c2-490f-b5a5-0aa5aa4af426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1536135327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1536135327
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4220440769
Short name T800
Test name
Test status
Simulation time 10442412107 ps
CPU time 79.62 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:39:19 PM PDT 24
Peak memory 239424 kb
Host smart-4ebdfab7-8ba4-4d81-b18e-82cf9b55f3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4220440769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4220440769
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2351474380
Short name T786
Test name
Test status
Simulation time 3387014946 ps
CPU time 250.25 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:42:09 PM PDT 24
Peak memory 240144 kb
Host smart-c5da5192-3813-41e6-918b-f9951c64fc15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2351474380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2351474380
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1511982691
Short name T780
Test name
Test status
Simulation time 1708740674 ps
CPU time 165.39 seconds
Started May 21 02:37:38 PM PDT 24
Finished May 21 02:40:42 PM PDT 24
Peak memory 235604 kb
Host smart-9421b72f-9da3-4a5a-82be-5914d375ed93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1511982691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1511982691
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.478658042
Short name T783
Test name
Test status
Simulation time 654712895 ps
CPU time 5.39 seconds
Started May 21 02:37:39 PM PDT 24
Finished May 21 02:38:03 PM PDT 24
Peak memory 240072 kb
Host smart-14dc85f3-3ff2-4f23-a76b-8e096b2e9d33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=478658042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.478658042
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.336686689
Short name T828
Test name
Test status
Simulation time 145094685 ps
CPU time 10.49 seconds
Started May 21 02:37:44 PM PDT 24
Finished May 21 02:38:12 PM PDT 24
Peak memory 248308 kb
Host smart-f1b44df0-ccdd-4512-a969-c3810bb3e7ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336686689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.336686689
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2519120190
Short name T782
Test name
Test status
Simulation time 105945481 ps
CPU time 5.11 seconds
Started May 21 02:37:39 PM PDT 24
Finished May 21 02:38:03 PM PDT 24
Peak memory 238424 kb
Host smart-89761c1b-541b-4dff-ab04-6f228ed92d06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2519120190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2519120190
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2661338681
Short name T733
Test name
Test status
Simulation time 13342170 ps
CPU time 1.3 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:00 PM PDT 24
Peak memory 236516 kb
Host smart-6429a15b-233a-4831-8c79-b15217fb729b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661338681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2661338681
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.115683306
Short name T815
Test name
Test status
Simulation time 672564457 ps
CPU time 19.65 seconds
Started May 21 02:37:46 PM PDT 24
Finished May 21 02:38:23 PM PDT 24
Peak memory 243756 kb
Host smart-48f945a0-ad6e-4688-a62c-8a460baebc71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=115683306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.115683306
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3896049534
Short name T113
Test name
Test status
Simulation time 2368267389 ps
CPU time 155.69 seconds
Started May 21 02:37:42 PM PDT 24
Finished May 21 02:40:36 PM PDT 24
Peak memory 264496 kb
Host smart-bc37cc83-35ba-450c-87b9-d48f8177fb9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3896049534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3896049534
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.86742281
Short name T147
Test name
Test status
Simulation time 48463438572 ps
CPU time 929.06 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:53:28 PM PDT 24
Peak memory 265136 kb
Host smart-47d2d927-f67f-4bf8-b097-dfbadef7da46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86742281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.86742281
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3841906926
Short name T742
Test name
Test status
Simulation time 597258970 ps
CPU time 15.59 seconds
Started May 21 02:37:40 PM PDT 24
Finished May 21 02:38:14 PM PDT 24
Peak memory 251480 kb
Host smart-cf8b76f1-4199-408c-b824-7c4b006a6147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3841906926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3841906926
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3819145177
Short name T770
Test name
Test status
Simulation time 95812173 ps
CPU time 8.81 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 239956 kb
Host smart-be0b19db-5645-4a23-84eb-436e99b665b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3819145177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3819145177
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1740905072
Short name T795
Test name
Test status
Simulation time 13671293 ps
CPU time 1.24 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:38:26 PM PDT 24
Peak memory 234560 kb
Host smart-c88507e5-7cc3-4f1d-9aa3-71b1f9a0d06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1740905072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1740905072
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2471405979
Short name T812
Test name
Test status
Simulation time 1890703867 ps
CPU time 21.34 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:38:45 PM PDT 24
Peak memory 244744 kb
Host smart-c2a64b6c-8881-451b-a948-1706101ebb2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2471405979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2471405979
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1308753210
Short name T236
Test name
Test status
Simulation time 153890946 ps
CPU time 10.55 seconds
Started May 21 02:38:07 PM PDT 24
Finished May 21 02:38:37 PM PDT 24
Peak memory 254244 kb
Host smart-4ede22d5-4b90-4f31-aa47-f6744f768919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1308753210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1308753210
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2306426592
Short name T738
Test name
Test status
Simulation time 201475453 ps
CPU time 4.82 seconds
Started May 21 02:38:07 PM PDT 24
Finished May 21 02:38:31 PM PDT 24
Peak memory 238556 kb
Host smart-fa35e733-a631-45a9-bffb-5bc84eb9a8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306426592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2306426592
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.311807888
Short name T777
Test name
Test status
Simulation time 20371495 ps
CPU time 3.62 seconds
Started May 21 02:38:07 PM PDT 24
Finished May 21 02:38:29 PM PDT 24
Peak memory 235584 kb
Host smart-5f44475c-e977-4bca-8cea-aeb7d82d5e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=311807888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.311807888
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1491899675
Short name T717
Test name
Test status
Simulation time 16214959 ps
CPU time 1.49 seconds
Started May 21 02:38:09 PM PDT 24
Finished May 21 02:38:30 PM PDT 24
Peak memory 234588 kb
Host smart-8733467c-f966-4fbc-bb2c-3840db0900bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1491899675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1491899675
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2307739159
Short name T813
Test name
Test status
Simulation time 6083163132 ps
CPU time 43.75 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:39:16 PM PDT 24
Peak memory 244696 kb
Host smart-73871d9f-6a46-4ebd-8b90-0fb4279c3e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2307739159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2307739159
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3637411584
Short name T124
Test name
Test status
Simulation time 83256362957 ps
CPU time 537.15 seconds
Started May 21 02:38:04 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 268524 kb
Host smart-1e501ad8-1f8f-4b08-8e42-3fa36d3b4396
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637411584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3637411584
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2674127581
Short name T820
Test name
Test status
Simulation time 178545778 ps
CPU time 13.49 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:38:39 PM PDT 24
Peak memory 247924 kb
Host smart-c6a415dd-2ad6-4321-9136-643b6c72e907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2674127581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2674127581
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3730952716
Short name T821
Test name
Test status
Simulation time 110650925 ps
CPU time 8.63 seconds
Started May 21 02:38:15 PM PDT 24
Finished May 21 02:38:45 PM PDT 24
Peak memory 240448 kb
Host smart-a7a1de86-b501-4d2f-98a2-60b42e662a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730952716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3730952716
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1696640970
Short name T751
Test name
Test status
Simulation time 13288853 ps
CPU time 1.69 seconds
Started May 21 02:38:10 PM PDT 24
Finished May 21 02:38:33 PM PDT 24
Peak memory 236524 kb
Host smart-c99661ea-4d46-49cc-95f7-08483b44c81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696640970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1696640970
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1040422152
Short name T808
Test name
Test status
Simulation time 455820128 ps
CPU time 19.44 seconds
Started May 21 02:38:11 PM PDT 24
Finished May 21 02:38:52 PM PDT 24
Peak memory 248484 kb
Host smart-f3ad1999-d8f1-40cf-9293-4fb72ba81760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1040422152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1040422152
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.960858013
Short name T141
Test name
Test status
Simulation time 4633236672 ps
CPU time 163.8 seconds
Started May 21 02:38:09 PM PDT 24
Finished May 21 02:41:13 PM PDT 24
Peak memory 265072 kb
Host smart-0b0fa924-7a39-468b-be0d-c3626ea1d055
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=960858013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.960858013
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1591727880
Short name T142
Test name
Test status
Simulation time 2288707078 ps
CPU time 329.09 seconds
Started May 21 02:38:11 PM PDT 24
Finished May 21 02:44:01 PM PDT 24
Peak memory 265080 kb
Host smart-49bec605-9d12-4a64-b9b7-b98dac394a82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591727880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1591727880
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2683817385
Short name T794
Test name
Test status
Simulation time 513485883 ps
CPU time 9.43 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:42 PM PDT 24
Peak memory 248244 kb
Host smart-b92f66e3-df59-433d-bf1f-a90f435be14b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2683817385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2683817385
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.20104053
Short name T348
Test name
Test status
Simulation time 220533873 ps
CPU time 5.37 seconds
Started May 21 02:38:13 PM PDT 24
Finished May 21 02:38:39 PM PDT 24
Peak memory 248328 kb
Host smart-3359b658-a63f-4bb6-8d34-466e2b825249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.alert_handler_csr_mem_rw_with_rand_reset.20104053
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2800964643
Short name T822
Test name
Test status
Simulation time 92076119 ps
CPU time 8.07 seconds
Started May 21 02:38:11 PM PDT 24
Finished May 21 02:38:40 PM PDT 24
Peak memory 236472 kb
Host smart-d2effe7b-09e1-465f-a825-400f5a58e46d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2800964643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2800964643
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1429292947
Short name T772
Test name
Test status
Simulation time 10727634 ps
CPU time 1.31 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:34 PM PDT 24
Peak memory 234788 kb
Host smart-7fad0574-3640-4af7-a7c9-73c306313b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1429292947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1429292947
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2373736799
Short name T761
Test name
Test status
Simulation time 1143983282 ps
CPU time 19.2 seconds
Started May 21 02:38:10 PM PDT 24
Finished May 21 02:38:50 PM PDT 24
Peak memory 248252 kb
Host smart-4bec39cc-2152-4c06-af1a-2bb9417c1735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2373736799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2373736799
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2119225266
Short name T819
Test name
Test status
Simulation time 2044581139 ps
CPU time 25.42 seconds
Started May 21 02:38:10 PM PDT 24
Finished May 21 02:38:57 PM PDT 24
Peak memory 248376 kb
Host smart-8aa9bf48-8daf-4c3c-9c02-173bce11911b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119225266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2119225266
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2384488225
Short name T749
Test name
Test status
Simulation time 115796751 ps
CPU time 8.19 seconds
Started May 21 02:38:15 PM PDT 24
Finished May 21 02:38:45 PM PDT 24
Peak memory 243704 kb
Host smart-b25bcddb-2a56-41c7-b048-d13c9eddf495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384488225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2384488225
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1161014944
Short name T233
Test name
Test status
Simulation time 68658024 ps
CPU time 5.28 seconds
Started May 21 02:38:16 PM PDT 24
Finished May 21 02:38:43 PM PDT 24
Peak memory 236472 kb
Host smart-5aa00db3-f66a-4bd5-93df-514a856287b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1161014944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1161014944
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1837146958
Short name T829
Test name
Test status
Simulation time 47661661 ps
CPU time 1.57 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:38:40 PM PDT 24
Peak memory 235612 kb
Host smart-6421b7e8-faea-41ac-86cd-62b0349ecb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1837146958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1837146958
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2905774512
Short name T716
Test name
Test status
Simulation time 1030679575 ps
CPU time 32.67 seconds
Started May 21 02:38:15 PM PDT 24
Finished May 21 02:39:10 PM PDT 24
Peak memory 243788 kb
Host smart-f7613174-f13f-4137-9903-16969ceb3d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2905774512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2905774512
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3286424948
Short name T818
Test name
Test status
Simulation time 8637148956 ps
CPU time 329.61 seconds
Started May 21 02:38:09 PM PDT 24
Finished May 21 02:43:59 PM PDT 24
Peak memory 265272 kb
Host smart-050f2c3d-a73c-44ed-b3eb-7e83356ff846
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286424948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3286424948
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.977153185
Short name T768
Test name
Test status
Simulation time 238882053 ps
CPU time 15.87 seconds
Started May 21 02:38:15 PM PDT 24
Finished May 21 02:38:53 PM PDT 24
Peak memory 248340 kb
Host smart-6a7bdd6b-3be5-47b7-a8f4-7ab5f82b1402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977153185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.977153185
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1705328290
Short name T727
Test name
Test status
Simulation time 127132660 ps
CPU time 9.37 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:38:48 PM PDT 24
Peak memory 256520 kb
Host smart-66e24595-b57d-4074-b04a-e9ea9522c96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705328290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1705328290
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3620205262
Short name T793
Test name
Test status
Simulation time 62812062 ps
CPU time 5.39 seconds
Started May 21 02:38:19 PM PDT 24
Finished May 21 02:38:46 PM PDT 24
Peak memory 236508 kb
Host smart-ea392c51-4866-43f6-873f-9804def71b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3620205262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3620205262
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.441745751
Short name T764
Test name
Test status
Simulation time 8694289 ps
CPU time 1.37 seconds
Started May 21 02:38:16 PM PDT 24
Finished May 21 02:38:39 PM PDT 24
Peak memory 235608 kb
Host smart-3cd45a46-a87b-4702-ac82-2080f17cc304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441745751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.441745751
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1751260858
Short name T171
Test name
Test status
Simulation time 699922766 ps
CPU time 13.23 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:38:52 PM PDT 24
Peak memory 244696 kb
Host smart-aee80a0a-115b-4294-98ae-62977743056e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1751260858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1751260858
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2900459
Short name T121
Test name
Test status
Simulation time 3561136854 ps
CPU time 121.13 seconds
Started May 21 02:38:17 PM PDT 24
Finished May 21 02:40:40 PM PDT 24
Peak memory 265000 kb
Host smart-5dbc8d81-a46a-49f5-9f49-34f3b021eaa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2900459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2900459
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1060720565
Short name T803
Test name
Test status
Simulation time 1272189464 ps
CPU time 22.11 seconds
Started May 21 02:38:16 PM PDT 24
Finished May 21 02:39:00 PM PDT 24
Peak memory 252168 kb
Host smart-93fe42dc-0074-44d9-8ebd-5425e3266bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1060720565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1060720565
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1910827112
Short name T781
Test name
Test status
Simulation time 74938450 ps
CPU time 6.01 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:38:52 PM PDT 24
Peak memory 238996 kb
Host smart-6a8bc35a-49c6-4872-a5d0-3ca3c0bda1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910827112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1910827112
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4003313393
Short name T344
Test name
Test status
Simulation time 91940978 ps
CPU time 4.44 seconds
Started May 21 02:38:21 PM PDT 24
Finished May 21 02:38:49 PM PDT 24
Peak memory 235560 kb
Host smart-d4513780-75c9-4b87-a39d-1e02526df6f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4003313393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4003313393
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2279844925
Short name T824
Test name
Test status
Simulation time 9719717 ps
CPU time 1.37 seconds
Started May 21 02:38:21 PM PDT 24
Finished May 21 02:38:47 PM PDT 24
Peak memory 234628 kb
Host smart-f41cb0d1-e5cb-43ca-bf71-adb63f6affc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2279844925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2279844925
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1071699300
Short name T732
Test name
Test status
Simulation time 322687819 ps
CPU time 12.22 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:38:58 PM PDT 24
Peak memory 244720 kb
Host smart-89faa250-732b-4393-a609-0bddea759f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071699300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1071699300
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3165452762
Short name T138
Test name
Test status
Simulation time 10813912174 ps
CPU time 348.72 seconds
Started May 21 02:38:18 PM PDT 24
Finished May 21 02:44:28 PM PDT 24
Peak memory 265080 kb
Host smart-941175c6-2a71-4cb9-80a0-4f3fd5786745
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3165452762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3165452762
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1721660578
Short name T151
Test name
Test status
Simulation time 6422648549 ps
CPU time 490.03 seconds
Started May 21 02:38:21 PM PDT 24
Finished May 21 02:46:55 PM PDT 24
Peak memory 265080 kb
Host smart-3fa254d9-8c69-451d-9004-9878da7586fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721660578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1721660578
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2620113087
Short name T771
Test name
Test status
Simulation time 58673588 ps
CPU time 7.21 seconds
Started May 21 02:38:18 PM PDT 24
Finished May 21 02:38:46 PM PDT 24
Peak memory 248240 kb
Host smart-8fadcef2-23a0-41b9-a538-b83221f923c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2620113087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2620113087
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2005155093
Short name T774
Test name
Test status
Simulation time 226995093 ps
CPU time 9.27 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 251892 kb
Host smart-724e2066-0d27-4ee6-992e-fa6a00b8f593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005155093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2005155093
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2865883799
Short name T748
Test name
Test status
Simulation time 9741085 ps
CPU time 1.54 seconds
Started May 21 02:38:26 PM PDT 24
Finished May 21 02:38:52 PM PDT 24
Peak memory 236556 kb
Host smart-bf9ac359-296c-4535-a863-2a0aaa463d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865883799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2865883799
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.262542475
Short name T726
Test name
Test status
Simulation time 672079893 ps
CPU time 26.42 seconds
Started May 21 02:38:20 PM PDT 24
Finished May 21 02:39:09 PM PDT 24
Peak memory 244756 kb
Host smart-2017fa44-c960-493b-af6d-dc44c3c15e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=262542475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.262542475
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3814085405
Short name T715
Test name
Test status
Simulation time 738813478 ps
CPU time 11.6 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:38:58 PM PDT 24
Peak memory 252764 kb
Host smart-1fa8a5d5-0cbe-4b82-8c8c-d548c508dadf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3814085405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3814085405
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1831898686
Short name T190
Test name
Test status
Simulation time 262232843 ps
CPU time 5.52 seconds
Started May 21 02:38:21 PM PDT 24
Finished May 21 02:38:51 PM PDT 24
Peak memory 236544 kb
Host smart-58614846-f4c4-480a-82e5-58d3d60676e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831898686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1831898686
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.82822895
Short name T187
Test name
Test status
Simulation time 34054449 ps
CPU time 3.54 seconds
Started May 21 02:38:26 PM PDT 24
Finished May 21 02:38:54 PM PDT 24
Peak memory 239364 kb
Host smart-a2760338-1df6-46f9-89fa-39bc52c92090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=82822895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.82822895
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1121676044
Short name T745
Test name
Test status
Simulation time 10280912 ps
CPU time 1.33 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:38:47 PM PDT 24
Peak memory 236560 kb
Host smart-2fa533b9-cdc5-4996-b72d-095a85109cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1121676044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1121676044
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3668813240
Short name T810
Test name
Test status
Simulation time 2411440194 ps
CPU time 20.68 seconds
Started May 21 02:38:22 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 243708 kb
Host smart-38a64c81-3a54-4020-8f32-4f4be984ad4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668813240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3668813240
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1744550181
Short name T126
Test name
Test status
Simulation time 3806596942 ps
CPU time 169.31 seconds
Started May 21 02:38:23 PM PDT 24
Finished May 21 02:41:36 PM PDT 24
Peak memory 265072 kb
Host smart-d4553435-5147-48d0-89b6-739091c38fe8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744550181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1744550181
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1143613121
Short name T741
Test name
Test status
Simulation time 1105412552 ps
CPU time 9.71 seconds
Started May 21 02:38:23 PM PDT 24
Finished May 21 02:38:57 PM PDT 24
Peak memory 252140 kb
Host smart-a8a6ed1f-b576-4daf-8caf-64145253d1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1143613121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1143613121
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2556640282
Short name T347
Test name
Test status
Simulation time 75184505 ps
CPU time 11.83 seconds
Started May 21 02:38:28 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 252948 kb
Host smart-a1cce290-8081-41e1-a7c1-632944a6e456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556640282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2556640282
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.475876563
Short name T350
Test name
Test status
Simulation time 303618182 ps
CPU time 7.71 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:39:04 PM PDT 24
Peak memory 236520 kb
Host smart-0cbb0df7-6d39-4f5c-8530-d2c5ac7b8066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=475876563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.475876563
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2007230981
Short name T340
Test name
Test status
Simulation time 8360193 ps
CPU time 1.49 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:38:58 PM PDT 24
Peak memory 234540 kb
Host smart-fa4e264a-fd22-4e1a-a613-3d231df1d318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007230981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2007230981
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1262101685
Short name T773
Test name
Test status
Simulation time 220643290 ps
CPU time 23.17 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:39:20 PM PDT 24
Peak memory 244724 kb
Host smart-95d9f933-7f62-4145-b9d4-ceac0acdef21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1262101685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1262101685
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.884792402
Short name T779
Test name
Test status
Simulation time 125416159 ps
CPU time 4.99 seconds
Started May 21 02:38:27 PM PDT 24
Finished May 21 02:38:59 PM PDT 24
Peak memory 239948 kb
Host smart-2fcdff79-bbd5-44c0-a69a-3d3afb7935ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=884792402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.884792402
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2486861848
Short name T238
Test name
Test status
Simulation time 95550458 ps
CPU time 4.44 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:39:00 PM PDT 24
Peak memory 236616 kb
Host smart-e18ad388-bbd2-4f53-8394-7ef9f1aef8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2486861848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2486861848
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3383386659
Short name T804
Test name
Test status
Simulation time 1131181609 ps
CPU time 60.62 seconds
Started May 21 02:37:45 PM PDT 24
Finished May 21 02:39:03 PM PDT 24
Peak memory 240068 kb
Host smart-5cad9469-44d7-4e8b-98e7-706bc7b9430a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3383386659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3383386659
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1359385894
Short name T345
Test name
Test status
Simulation time 3406418449 ps
CPU time 87.75 seconds
Started May 21 02:37:49 PM PDT 24
Finished May 21 02:39:34 PM PDT 24
Peak memory 235576 kb
Host smart-45c6ce26-7c48-400f-9e06-5eea5509550b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1359385894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1359385894
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3049598603
Short name T744
Test name
Test status
Simulation time 393075629 ps
CPU time 8.88 seconds
Started May 21 02:37:49 PM PDT 24
Finished May 21 02:38:16 PM PDT 24
Peak memory 240052 kb
Host smart-0dd5e09d-79cf-46b1-8a17-5bc297018c1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3049598603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3049598603
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2942117360
Short name T750
Test name
Test status
Simulation time 103320740 ps
CPU time 8.55 seconds
Started May 21 02:37:45 PM PDT 24
Finished May 21 02:38:12 PM PDT 24
Peak memory 240128 kb
Host smart-418e4767-2731-44ed-b44e-c057ca586284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942117360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2942117360
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.59905497
Short name T186
Test name
Test status
Simulation time 35082577 ps
CPU time 5.85 seconds
Started May 21 02:37:46 PM PDT 24
Finished May 21 02:38:09 PM PDT 24
Peak memory 236504 kb
Host smart-d4bd168b-b990-4b63-b59d-e69ba1279a6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=59905497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.59905497
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.122334503
Short name T173
Test name
Test status
Simulation time 694887375 ps
CPU time 25.07 seconds
Started May 21 02:37:47 PM PDT 24
Finished May 21 02:38:30 PM PDT 24
Peak memory 244712 kb
Host smart-16822ae6-563f-406d-941a-453fcfc74942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=122334503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.122334503
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.175451796
Short name T144
Test name
Test status
Simulation time 25044061103 ps
CPU time 499.18 seconds
Started May 21 02:37:45 PM PDT 24
Finished May 21 02:46:22 PM PDT 24
Peak memory 265164 kb
Host smart-d151d858-f821-4e78-a450-257c7aff4d3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175451796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.175451796
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1914510555
Short name T235
Test name
Test status
Simulation time 655517316 ps
CPU time 22.79 seconds
Started May 21 02:37:44 PM PDT 24
Finished May 21 02:38:24 PM PDT 24
Peak memory 248488 kb
Host smart-d532f049-f7b6-4211-862c-b1abbe42d347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1914510555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1914510555
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1680348028
Short name T723
Test name
Test status
Simulation time 6863207 ps
CPU time 1.4 seconds
Started May 21 02:38:38 PM PDT 24
Finished May 21 02:39:11 PM PDT 24
Peak memory 236484 kb
Host smart-4a33c74c-c985-4f48-be5b-e978e5d3c99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1680348028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1680348028
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1908135615
Short name T746
Test name
Test status
Simulation time 6435722 ps
CPU time 1.4 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:38:57 PM PDT 24
Peak memory 234476 kb
Host smart-1241f40e-4e96-4146-9c78-8d9e2d59f4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1908135615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1908135615
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2130435446
Short name T157
Test name
Test status
Simulation time 12346267 ps
CPU time 1.49 seconds
Started May 21 02:38:28 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 236560 kb
Host smart-f8980d88-f4b4-4e26-bb67-e6d20d0f1c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2130435446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2130435446
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4102269261
Short name T755
Test name
Test status
Simulation time 6580327 ps
CPU time 1.41 seconds
Started May 21 02:38:38 PM PDT 24
Finished May 21 02:39:11 PM PDT 24
Peak memory 236488 kb
Host smart-3ff852b3-bac6-4739-b2bd-e9d3dd8db91f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4102269261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4102269261
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3808777179
Short name T790
Test name
Test status
Simulation time 10109863 ps
CPU time 1.61 seconds
Started May 21 02:38:28 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 236548 kb
Host smart-53fb4e50-e44a-4462-a155-6b095b2fae3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3808777179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3808777179
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1354658543
Short name T805
Test name
Test status
Simulation time 9331101 ps
CPU time 1.34 seconds
Started May 21 02:38:27 PM PDT 24
Finished May 21 02:38:54 PM PDT 24
Peak memory 235624 kb
Host smart-525e96ff-6523-453d-8fd0-c2eaf68ccddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1354658543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1354658543
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.331377567
Short name T802
Test name
Test status
Simulation time 10267872 ps
CPU time 1.52 seconds
Started May 21 02:38:27 PM PDT 24
Finished May 21 02:38:54 PM PDT 24
Peak memory 236556 kb
Host smart-e9b8a81b-8144-49e8-bb6d-541fb9dacf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331377567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.331377567
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1742960481
Short name T757
Test name
Test status
Simulation time 7973212 ps
CPU time 1.26 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:38:57 PM PDT 24
Peak memory 234560 kb
Host smart-bc81a74d-b27c-4d16-bb92-2d50281eaf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1742960481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1742960481
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3778391722
Short name T801
Test name
Test status
Simulation time 21091852 ps
CPU time 1.44 seconds
Started May 21 02:38:29 PM PDT 24
Finished May 21 02:38:57 PM PDT 24
Peak memory 235620 kb
Host smart-551add21-85d9-456f-96b0-ca418f7136cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3778391722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3778391722
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3139961949
Short name T230
Test name
Test status
Simulation time 11153063 ps
CPU time 1.47 seconds
Started May 21 02:38:27 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 234596 kb
Host smart-28289d3c-083b-4d8e-b6aa-8b277fb196fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3139961949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3139961949
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2507446410
Short name T172
Test name
Test status
Simulation time 2188127712 ps
CPU time 175.13 seconds
Started May 21 02:37:51 PM PDT 24
Finished May 21 02:41:04 PM PDT 24
Peak memory 240488 kb
Host smart-74846704-cce0-495b-ae44-568ede161d80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2507446410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2507446410
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1798454525
Short name T785
Test name
Test status
Simulation time 2861661121 ps
CPU time 176.68 seconds
Started May 21 02:37:50 PM PDT 24
Finished May 21 02:41:04 PM PDT 24
Peak memory 235600 kb
Host smart-c1545a12-c928-49e8-a91f-c9e11ad9af4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1798454525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1798454525
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1233725182
Short name T799
Test name
Test status
Simulation time 26771338 ps
CPU time 3.76 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:17 PM PDT 24
Peak memory 240028 kb
Host smart-25cf8d62-53d9-449a-b496-e2b7e17d9e44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1233725182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1233725182
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2978754642
Short name T747
Test name
Test status
Simulation time 222079782 ps
CPU time 9.05 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:19 PM PDT 24
Peak memory 237032 kb
Host smart-da02d64e-41a3-47d3-989a-2a9895c56d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978754642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2978754642
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3214347174
Short name T743
Test name
Test status
Simulation time 50107905 ps
CPU time 4.29 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:15 PM PDT 24
Peak memory 239456 kb
Host smart-8a133426-1bd7-4456-8618-70cc2751850e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3214347174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3214347174
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.833902865
Short name T797
Test name
Test status
Simulation time 10327084 ps
CPU time 1.27 seconds
Started May 21 02:37:50 PM PDT 24
Finished May 21 02:38:09 PM PDT 24
Peak memory 234556 kb
Host smart-4dd6b6fa-946f-47ad-8b0c-ed7c3636a9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=833902865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.833902865
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1952092098
Short name T189
Test name
Test status
Simulation time 1467476435 ps
CPU time 36.31 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:49 PM PDT 24
Peak memory 244716 kb
Host smart-730883ce-886c-4945-8405-6e1d35b5d0c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1952092098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1952092098
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2448955549
Short name T116
Test name
Test status
Simulation time 1558500101 ps
CPU time 132.48 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:40:21 PM PDT 24
Peak memory 265032 kb
Host smart-79636b23-68ac-470b-90a7-29ff822acec1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2448955549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2448955549
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3516358497
Short name T765
Test name
Test status
Simulation time 216556786 ps
CPU time 7.1 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:20 PM PDT 24
Peak memory 247844 kb
Host smart-d416b2f7-2fbb-41ad-90df-61438902f097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3516358497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3516358497
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4018802205
Short name T731
Test name
Test status
Simulation time 14612572 ps
CPU time 1.37 seconds
Started May 21 02:38:28 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 234576 kb
Host smart-1eccd961-c7aa-448b-9b0c-1dbcaa5abd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4018802205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4018802205
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3405157260
Short name T739
Test name
Test status
Simulation time 11276343 ps
CPU time 1.37 seconds
Started May 21 02:38:28 PM PDT 24
Finished May 21 02:38:56 PM PDT 24
Peak memory 236544 kb
Host smart-11931dd3-25d9-49a4-b36b-6abf278bcd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3405157260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3405157260
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1555874812
Short name T809
Test name
Test status
Simulation time 12258310 ps
CPU time 1.63 seconds
Started May 21 02:38:33 PM PDT 24
Finished May 21 02:39:05 PM PDT 24
Peak memory 236524 kb
Host smart-aac1d380-a748-460c-a8a0-74cac4890ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1555874812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1555874812
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.314850830
Short name T240
Test name
Test status
Simulation time 9208708 ps
CPU time 1.5 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235596 kb
Host smart-f90148bc-6119-4ddd-87a4-f36a961843bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=314850830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.314850830
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3494403214
Short name T766
Test name
Test status
Simulation time 11178350 ps
CPU time 1.24 seconds
Started May 21 02:38:38 PM PDT 24
Finished May 21 02:39:11 PM PDT 24
Peak memory 235552 kb
Host smart-27eae642-e3ae-4f4a-b831-9572cd078ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3494403214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3494403214
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.78918915
Short name T720
Test name
Test status
Simulation time 7689899 ps
CPU time 1.43 seconds
Started May 21 02:38:32 PM PDT 24
Finished May 21 02:39:01 PM PDT 24
Peak memory 235576 kb
Host smart-6dded125-f224-4f1a-947d-f0e949e89f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=78918915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.78918915
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.918524947
Short name T155
Test name
Test status
Simulation time 28439436 ps
CPU time 2.14 seconds
Started May 21 02:38:35 PM PDT 24
Finished May 21 02:39:08 PM PDT 24
Peak memory 234600 kb
Host smart-7b0c2634-7c5e-4dbe-9e12-4e9c469c229e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=918524947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.918524947
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1332422434
Short name T721
Test name
Test status
Simulation time 13801251 ps
CPU time 1.61 seconds
Started May 21 02:38:33 PM PDT 24
Finished May 21 02:39:05 PM PDT 24
Peak memory 235564 kb
Host smart-415a06bc-9b1f-4fde-b13c-f476727b7965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1332422434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1332422434
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2762532094
Short name T784
Test name
Test status
Simulation time 8071726 ps
CPU time 1.42 seconds
Started May 21 02:38:33 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 234652 kb
Host smart-f4089b34-527f-42c5-9803-dea5fbdf7fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2762532094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2762532094
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.462333526
Short name T776
Test name
Test status
Simulation time 3415609759 ps
CPU time 232.9 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:42:02 PM PDT 24
Peak memory 240148 kb
Host smart-9865b055-cd36-4c52-88c4-ab4ab1ece135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=462333526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.462333526
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2081759488
Short name T728
Test name
Test status
Simulation time 5950023449 ps
CPU time 200.64 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 236600 kb
Host smart-dcb5f352-7447-4013-b591-c7aa1afd83d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2081759488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2081759488
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2095354610
Short name T827
Test name
Test status
Simulation time 215928173 ps
CPU time 5.35 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:15 PM PDT 24
Peak memory 240088 kb
Host smart-78e3e029-4b68-41fa-9b64-571b9d71dea4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2095354610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2095354610
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1648421964
Short name T237
Test name
Test status
Simulation time 583991336 ps
CPU time 11.12 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:24 PM PDT 24
Peak memory 250496 kb
Host smart-06df86c1-0275-4a48-8af1-d56235b14c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648421964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1648421964
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1393533070
Short name T792
Test name
Test status
Simulation time 21444087 ps
CPU time 3.41 seconds
Started May 21 02:37:50 PM PDT 24
Finished May 21 02:38:11 PM PDT 24
Peak memory 236516 kb
Host smart-7ac8f5b0-0a8d-4f3f-afff-cb333594220a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1393533070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1393533070
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2844308086
Short name T729
Test name
Test status
Simulation time 8728879 ps
CPU time 1.29 seconds
Started May 21 02:37:51 PM PDT 24
Finished May 21 02:38:10 PM PDT 24
Peak memory 234560 kb
Host smart-2d7710b4-589f-4700-98c1-2a57ff78229e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2844308086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2844308086
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.187083603
Short name T760
Test name
Test status
Simulation time 106724392 ps
CPU time 12.57 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:38:22 PM PDT 24
Peak memory 248280 kb
Host smart-cc579dfc-cdc4-476c-9be7-858d2dc8fa99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=187083603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.187083603
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4031357788
Short name T734
Test name
Test status
Simulation time 186136787 ps
CPU time 12.61 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:24 PM PDT 24
Peak memory 248080 kb
Host smart-419a6ba8-af65-4731-b00f-60df22d1c4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4031357788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4031357788
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3737257724
Short name T811
Test name
Test status
Simulation time 27201756 ps
CPU time 1.36 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235608 kb
Host smart-bccee82c-6a47-40c6-b07b-02bfeeae3b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3737257724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3737257724
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1264355256
Short name T807
Test name
Test status
Simulation time 9555730 ps
CPU time 1.55 seconds
Started May 21 02:38:33 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235600 kb
Host smart-eeade804-5fc0-43e7-9d76-72f783465531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1264355256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1264355256
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.847911568
Short name T762
Test name
Test status
Simulation time 11075944 ps
CPU time 1.22 seconds
Started May 21 02:38:38 PM PDT 24
Finished May 21 02:39:11 PM PDT 24
Peak memory 234512 kb
Host smart-a4ddf58d-3109-41c8-ae6c-0b5f7e513d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847911568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.847911568
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.621876400
Short name T719
Test name
Test status
Simulation time 7648720 ps
CPU time 1.52 seconds
Started May 21 02:38:35 PM PDT 24
Finished May 21 02:39:07 PM PDT 24
Peak memory 234604 kb
Host smart-cdec2110-e474-43c6-ac33-578d1e57353a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=621876400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.621876400
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1419613859
Short name T722
Test name
Test status
Simulation time 30552699 ps
CPU time 1.47 seconds
Started May 21 02:38:33 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 236532 kb
Host smart-0e9cc6a5-ee5b-4082-8798-ffa28e3377ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1419613859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1419613859
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1092124921
Short name T342
Test name
Test status
Simulation time 6741404 ps
CPU time 1.52 seconds
Started May 21 02:38:34 PM PDT 24
Finished May 21 02:39:06 PM PDT 24
Peak memory 235612 kb
Host smart-ecdfc531-b649-4c2d-bc14-6f15814c65cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1092124921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1092124921
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.850249555
Short name T737
Test name
Test status
Simulation time 27860474 ps
CPU time 1.46 seconds
Started May 21 02:38:39 PM PDT 24
Finished May 21 02:39:16 PM PDT 24
Peak memory 236488 kb
Host smart-881a91be-eded-43e7-b1df-c432363edb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=850249555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.850249555
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2862230732
Short name T241
Test name
Test status
Simulation time 14266280 ps
CPU time 1.56 seconds
Started May 21 02:38:38 PM PDT 24
Finished May 21 02:39:11 PM PDT 24
Peak memory 236568 kb
Host smart-19a7363b-697e-4898-b0aa-e8f7206b4faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2862230732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2862230732
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2483870899
Short name T724
Test name
Test status
Simulation time 20169771 ps
CPU time 1.27 seconds
Started May 21 02:38:39 PM PDT 24
Finished May 21 02:39:16 PM PDT 24
Peak memory 236488 kb
Host smart-0d4ecb20-531b-4d32-a626-706d7ee1064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483870899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2483870899
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.226191473
Short name T239
Test name
Test status
Simulation time 122597109 ps
CPU time 8.6 seconds
Started May 21 02:37:54 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 240144 kb
Host smart-7cc6b5a5-d4d8-45cc-8d28-785ddcb0b18b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226191473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.226191473
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2789038121
Short name T769
Test name
Test status
Simulation time 26587474 ps
CPU time 3.32 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:14 PM PDT 24
Peak memory 236508 kb
Host smart-e52ef097-797b-4336-b575-9e941cf7fa16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2789038121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2789038121
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1566277302
Short name T758
Test name
Test status
Simulation time 14945650 ps
CPU time 1.56 seconds
Started May 21 02:37:55 PM PDT 24
Finished May 21 02:38:15 PM PDT 24
Peak memory 236552 kb
Host smart-96680a0e-2b24-4040-8149-522f644cca5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1566277302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1566277302
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2878454336
Short name T763
Test name
Test status
Simulation time 178873499 ps
CPU time 23.01 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:38:35 PM PDT 24
Peak memory 248284 kb
Host smart-3f6a64e0-1904-4f70-a4b5-6dd067ce66b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2878454336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2878454336
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.678910769
Short name T120
Test name
Test status
Simulation time 793621682 ps
CPU time 91.25 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:39:43 PM PDT 24
Peak memory 256788 kb
Host smart-21bf0394-db4f-4dcf-890b-137ff8edbe2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=678910769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.678910769
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1776176085
Short name T119
Test name
Test status
Simulation time 2440762361 ps
CPU time 321.47 seconds
Started May 21 02:37:53 PM PDT 24
Finished May 21 02:43:32 PM PDT 24
Peak memory 265084 kb
Host smart-42bbb9fe-bddf-4037-9b3a-2d4361b18dc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776176085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1776176085
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.784955350
Short name T791
Test name
Test status
Simulation time 754552626 ps
CPU time 14.07 seconds
Started May 21 02:37:52 PM PDT 24
Finished May 21 02:38:23 PM PDT 24
Peak memory 248288 kb
Host smart-cd3a36be-9538-4961-abdd-32f6aad2b4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=784955350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.784955350
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4030032754
Short name T816
Test name
Test status
Simulation time 149131092 ps
CPU time 6.5 seconds
Started May 21 02:37:58 PM PDT 24
Finished May 21 02:38:22 PM PDT 24
Peak memory 239196 kb
Host smart-46cd4ab4-c20e-4cba-9577-b1c3575933b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030032754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4030032754
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4234390768
Short name T826
Test name
Test status
Simulation time 19407999 ps
CPU time 3.36 seconds
Started May 21 02:38:01 PM PDT 24
Finished May 21 02:38:23 PM PDT 24
Peak memory 238252 kb
Host smart-300f4b26-f139-4ec4-b41d-c1b72a083ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4234390768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4234390768
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2706114941
Short name T789
Test name
Test status
Simulation time 7702086 ps
CPU time 1.41 seconds
Started May 21 02:38:00 PM PDT 24
Finished May 21 02:38:20 PM PDT 24
Peak memory 236528 kb
Host smart-bb821c8b-45fe-4b65-bddf-bcafc4885b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2706114941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2706114941
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3034896923
Short name T778
Test name
Test status
Simulation time 1353735445 ps
CPU time 24.02 seconds
Started May 21 02:37:59 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 248288 kb
Host smart-d0adc494-b46f-4905-b029-27d2bcd8b4a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3034896923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3034896923
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1756319087
Short name T136
Test name
Test status
Simulation time 7487161552 ps
CPU time 449.28 seconds
Started May 21 02:37:58 PM PDT 24
Finished May 21 02:45:45 PM PDT 24
Peak memory 267592 kb
Host smart-cad8aa84-7398-48ec-a639-c617fe3db5d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756319087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1756319087
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1095894503
Short name T713
Test name
Test status
Simulation time 69265020 ps
CPU time 5.79 seconds
Started May 21 02:37:58 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 248300 kb
Host smart-6d2acb8e-f44d-497d-bb2c-b56caabe3ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1095894503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1095894503
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3976058938
Short name T167
Test name
Test status
Simulation time 109094613 ps
CPU time 2.47 seconds
Started May 21 02:38:01 PM PDT 24
Finished May 21 02:38:22 PM PDT 24
Peak memory 236624 kb
Host smart-4692f27f-996f-4553-a0d3-3114badef913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3976058938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3976058938
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.552640459
Short name T798
Test name
Test status
Simulation time 157836523 ps
CPU time 13.03 seconds
Started May 21 02:37:59 PM PDT 24
Finished May 21 02:38:30 PM PDT 24
Peak memory 251400 kb
Host smart-75af9a26-a5c5-494a-a367-80679c2d1ff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552640459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.552640459
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.840124581
Short name T349
Test name
Test status
Simulation time 205211430 ps
CPU time 6.96 seconds
Started May 21 02:37:59 PM PDT 24
Finished May 21 02:38:24 PM PDT 24
Peak memory 235604 kb
Host smart-1b7b7eb2-878f-47d7-a270-b32266d0fd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=840124581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.840124581
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2236938393
Short name T775
Test name
Test status
Simulation time 24150945 ps
CPU time 1.38 seconds
Started May 21 02:38:02 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 236564 kb
Host smart-f5a73372-53ad-4dc6-8e47-0547425a0888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2236938393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2236938393
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1064674585
Short name T806
Test name
Test status
Simulation time 328978882 ps
CPU time 22.55 seconds
Started May 21 02:38:00 PM PDT 24
Finished May 21 02:38:41 PM PDT 24
Peak memory 244704 kb
Host smart-f67c7da3-900b-43e7-a19b-cd7d840b6c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1064674585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1064674585
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1534675809
Short name T143
Test name
Test status
Simulation time 2177178688 ps
CPU time 143.92 seconds
Started May 21 02:38:00 PM PDT 24
Finished May 21 02:40:42 PM PDT 24
Peak memory 265896 kb
Host smart-d18eb43c-5ee4-449c-9363-36b2a3777ad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1534675809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1534675809
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4255008420
Short name T714
Test name
Test status
Simulation time 43974480 ps
CPU time 5.51 seconds
Started May 21 02:37:58 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 247400 kb
Host smart-1f48c3fa-87bf-471d-8039-88d22895ba4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255008420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4255008420
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3391736429
Short name T736
Test name
Test status
Simulation time 67829710 ps
CPU time 10.77 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:43 PM PDT 24
Peak memory 252256 kb
Host smart-f8dc3d11-feec-4d14-89ac-4a54c07760bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391736429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3391736429
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.566185044
Short name T823
Test name
Test status
Simulation time 255763778 ps
CPU time 5.41 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:38:31 PM PDT 24
Peak memory 236152 kb
Host smart-7048a669-48ff-4619-b36e-0fb08e8c79d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=566185044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.566185044
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.876735317
Short name T796
Test name
Test status
Simulation time 8467670 ps
CPU time 1.45 seconds
Started May 21 02:38:03 PM PDT 24
Finished May 21 02:38:22 PM PDT 24
Peak memory 236540 kb
Host smart-7e8b3e36-b26b-407b-bffb-ef01531f63dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=876735317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.876735317
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3608021173
Short name T814
Test name
Test status
Simulation time 681609181 ps
CPU time 50.28 seconds
Started May 21 02:38:08 PM PDT 24
Finished May 21 02:39:18 PM PDT 24
Peak memory 244728 kb
Host smart-2c5ff4e8-a450-4d86-811b-7a1d7e85932b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3608021173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3608021173
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1764957905
Short name T134
Test name
Test status
Simulation time 1675545531 ps
CPU time 222.58 seconds
Started May 21 02:37:59 PM PDT 24
Finished May 21 02:42:01 PM PDT 24
Peak memory 265036 kb
Host smart-e788dcb7-0cf6-4d93-a8a7-d034511c868c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1764957905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1764957905
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1152417141
Short name T118
Test name
Test status
Simulation time 12677045661 ps
CPU time 454.63 seconds
Started May 21 02:37:59 PM PDT 24
Finished May 21 02:45:52 PM PDT 24
Peak memory 269592 kb
Host smart-fba2472e-35b8-4ec8-b098-74874cec7313
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152417141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1152417141
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3581251151
Short name T787
Test name
Test status
Simulation time 26095803 ps
CPU time 4.27 seconds
Started May 21 02:38:06 PM PDT 24
Finished May 21 02:38:30 PM PDT 24
Peak memory 248312 kb
Host smart-624e35ec-a531-4a4a-b6fa-7db5c6a613b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3581251151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3581251151
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2791894128
Short name T756
Test name
Test status
Simulation time 589071557 ps
CPU time 23.27 seconds
Started May 21 02:38:07 PM PDT 24
Finished May 21 02:38:49 PM PDT 24
Peak memory 239428 kb
Host smart-55284786-b80d-41d3-b0f5-d96e9e58108b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2791894128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2791894128
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.786072693
Short name T740
Test name
Test status
Simulation time 132515836 ps
CPU time 6.07 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:38:31 PM PDT 24
Peak memory 252960 kb
Host smart-20b01ca7-b16f-4874-ab89-bc22346dde8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786072693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.786072693
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4085295028
Short name T730
Test name
Test status
Simulation time 61298034 ps
CPU time 3.74 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:38:29 PM PDT 24
Peak memory 236480 kb
Host smart-80967c4f-375c-4be7-89d7-414f95e6ec84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4085295028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4085295028
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3996700112
Short name T718
Test name
Test status
Simulation time 14452190 ps
CPU time 1.36 seconds
Started May 21 02:38:12 PM PDT 24
Finished May 21 02:38:33 PM PDT 24
Peak memory 236332 kb
Host smart-dbe920de-a5db-4022-a025-eb44a7899de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3996700112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3996700112
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2412044886
Short name T735
Test name
Test status
Simulation time 96854476 ps
CPU time 14.39 seconds
Started May 21 02:38:04 PM PDT 24
Finished May 21 02:38:37 PM PDT 24
Peak memory 244744 kb
Host smart-322362a3-9e45-430b-8b71-323c2e181971
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2412044886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2412044886
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1081912205
Short name T148
Test name
Test status
Simulation time 17632071185 ps
CPU time 319.56 seconds
Started May 21 02:38:05 PM PDT 24
Finished May 21 02:43:44 PM PDT 24
Peak memory 271848 kb
Host smart-fe3f8d19-8c2e-4865-84e6-c50e2a225006
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1081912205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1081912205
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4007543274
Short name T150
Test name
Test status
Simulation time 9013746142 ps
CPU time 306.36 seconds
Started May 21 02:38:03 PM PDT 24
Finished May 21 02:43:28 PM PDT 24
Peak memory 265084 kb
Host smart-9446d3c5-9988-4a8b-9fa1-e97abe877e0b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007543274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4007543274
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3157788972
Short name T753
Test name
Test status
Simulation time 307600535 ps
CPU time 20.04 seconds
Started May 21 02:38:04 PM PDT 24
Finished May 21 02:38:44 PM PDT 24
Peak memory 248284 kb
Host smart-3557af81-f595-4b9f-8279-526b1ef5922e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157788972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3157788972
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3261392990
Short name T69
Test name
Test status
Simulation time 757012506 ps
CPU time 11.69 seconds
Started May 21 03:04:34 PM PDT 24
Finished May 21 03:04:47 PM PDT 24
Peak memory 248772 kb
Host smart-13110a28-bbc9-4444-8da7-a55701830d38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3261392990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3261392990
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1224826477
Short name T518
Test name
Test status
Simulation time 1837646686 ps
CPU time 144.9 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:06:55 PM PDT 24
Peak memory 256772 kb
Host smart-7dbbcc12-7b45-4224-9d2b-47b238ca2315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12248
26477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1224826477
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1284531848
Short name T503
Test name
Test status
Simulation time 380687695 ps
CPU time 9.89 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:40 PM PDT 24
Peak memory 249120 kb
Host smart-70d58b87-2004-4871-bfce-e0d4eda82a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12845
31848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1284531848
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1262167602
Short name T495
Test name
Test status
Simulation time 44791993668 ps
CPU time 996.31 seconds
Started May 21 03:04:27 PM PDT 24
Finished May 21 03:21:05 PM PDT 24
Peak memory 268296 kb
Host smart-8fd2b273-039f-4b2f-b338-5aa1a794e7ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262167602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1262167602
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1517462434
Short name T474
Test name
Test status
Simulation time 81830643717 ps
CPU time 2734.68 seconds
Started May 21 03:04:32 PM PDT 24
Finished May 21 03:50:08 PM PDT 24
Peak memory 289744 kb
Host smart-7ad13e72-1d47-43c1-b487-31ed4072e880
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517462434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1517462434
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3197132544
Short name T305
Test name
Test status
Simulation time 7115558164 ps
CPU time 293.05 seconds
Started May 21 03:04:31 PM PDT 24
Finished May 21 03:09:25 PM PDT 24
Peak memory 247932 kb
Host smart-4c3ef424-f846-4aba-8ae9-1e0143e74d22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197132544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3197132544
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.4195350316
Short name T374
Test name
Test status
Simulation time 2352267800 ps
CPU time 38.38 seconds
Started May 21 03:04:30 PM PDT 24
Finished May 21 03:05:09 PM PDT 24
Peak memory 248916 kb
Host smart-a7538f18-109f-4843-a12a-a95dadf233a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
50316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.4195350316
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3407711839
Short name T619
Test name
Test status
Simulation time 1311654090 ps
CPU time 28.47 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:59 PM PDT 24
Peak memory 255292 kb
Host smart-f76800d9-9b33-44a1-8415-11a8be456c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
11839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3407711839
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3791693675
Short name T35
Test name
Test status
Simulation time 2062259695 ps
CPU time 14.53 seconds
Started May 21 03:04:33 PM PDT 24
Finished May 21 03:04:48 PM PDT 24
Peak memory 270344 kb
Host smart-c01d58b0-5828-4e1c-865b-eb525a88a60a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3791693675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3791693675
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2783229491
Short name T428
Test name
Test status
Simulation time 208803522 ps
CPU time 20.77 seconds
Started May 21 03:04:27 PM PDT 24
Finished May 21 03:04:49 PM PDT 24
Peak memory 248776 kb
Host smart-b2fe074d-e923-4d93-b2ac-6b4457373d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27832
29491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2783229491
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2923248134
Short name T637
Test name
Test status
Simulation time 36646468527 ps
CPU time 2384.75 seconds
Started May 21 03:04:39 PM PDT 24
Finished May 21 03:44:26 PM PDT 24
Peak memory 288768 kb
Host smart-b25cbe07-0ff0-4566-9d75-ecb8f44b5659
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923248134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2923248134
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4076362442
Short name T42
Test name
Test status
Simulation time 13712203703 ps
CPU time 1037.46 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:21:56 PM PDT 24
Peak memory 281644 kb
Host smart-50a3f68e-2db6-48ce-9b29-e61cb9b75285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076362442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4076362442
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3936641476
Short name T634
Test name
Test status
Simulation time 201695500 ps
CPU time 12.05 seconds
Started May 21 03:04:39 PM PDT 24
Finished May 21 03:04:53 PM PDT 24
Peak memory 248792 kb
Host smart-acec90df-4098-4be2-b014-cbf6b13cb843
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3936641476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3936641476
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2132041935
Short name T622
Test name
Test status
Simulation time 14336570027 ps
CPU time 210.18 seconds
Started May 21 03:04:39 PM PDT 24
Finished May 21 03:08:11 PM PDT 24
Peak memory 256996 kb
Host smart-06f9131c-655a-4e42-b248-cd4903055829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21320
41935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2132041935
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2349337247
Short name T669
Test name
Test status
Simulation time 65760395 ps
CPU time 7.7 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:04:47 PM PDT 24
Peak memory 252932 kb
Host smart-e21f4f87-7d8a-4b27-bf28-233fc475af27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
37247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2349337247
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3686992085
Short name T694
Test name
Test status
Simulation time 181611106562 ps
CPU time 2660.74 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:49:00 PM PDT 24
Peak memory 288944 kb
Host smart-38a12fed-8364-4547-92cd-e36207d237b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686992085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3686992085
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.847514377
Short name T3
Test name
Test status
Simulation time 8688583806 ps
CPU time 901.4 seconds
Started May 21 03:04:36 PM PDT 24
Finished May 21 03:19:39 PM PDT 24
Peak memory 270704 kb
Host smart-154fa8e1-d1a4-4a1d-857d-e0baca1472c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847514377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.847514377
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2592911663
Short name T7
Test name
Test status
Simulation time 25359410053 ps
CPU time 217.21 seconds
Started May 21 03:04:35 PM PDT 24
Finished May 21 03:08:12 PM PDT 24
Peak memory 247388 kb
Host smart-19943ef8-aa0e-401d-a264-5c0a8c752c17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592911663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2592911663
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2998122460
Short name T212
Test name
Test status
Simulation time 379813697 ps
CPU time 34.24 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:05:16 PM PDT 24
Peak memory 255884 kb
Host smart-8ebb19a8-2d24-4682-a008-36ebd0347419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
22460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2998122460
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.964921323
Short name T111
Test name
Test status
Simulation time 856693816 ps
CPU time 51.33 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:05:30 PM PDT 24
Peak memory 248772 kb
Host smart-fbfa0cb7-a432-4af7-a7e2-7a9ad9acc525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96492
1323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.964921323
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.527240213
Short name T11
Test name
Test status
Simulation time 1257625179 ps
CPU time 53.77 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:05:33 PM PDT 24
Peak memory 270336 kb
Host smart-70b870c3-209d-4b5d-8101-da5717454442
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=527240213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.527240213
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2366891238
Short name T687
Test name
Test status
Simulation time 155535792 ps
CPU time 16.27 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:04:58 PM PDT 24
Peak memory 248560 kb
Host smart-6d77df50-7b0a-4fde-b575-a888f45f2197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23668
91238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2366891238
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3805540360
Short name T256
Test name
Test status
Simulation time 62813695680 ps
CPU time 1893.73 seconds
Started May 21 03:04:36 PM PDT 24
Finished May 21 03:36:11 PM PDT 24
Peak memory 286712 kb
Host smart-65a61459-2e17-4573-83d8-55a3dfe66b48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805540360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3805540360
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2167338786
Short name T196
Test name
Test status
Simulation time 16489353 ps
CPU time 2.53 seconds
Started May 21 03:05:09 PM PDT 24
Finished May 21 03:05:14 PM PDT 24
Peak memory 248948 kb
Host smart-b93434ab-57df-42c5-976f-999555c8fd66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2167338786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2167338786
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3987315774
Short name T442
Test name
Test status
Simulation time 43200754687 ps
CPU time 735.48 seconds
Started May 21 03:05:10 PM PDT 24
Finished May 21 03:17:27 PM PDT 24
Peak memory 273172 kb
Host smart-9ecb2ee5-973a-45c6-8c7a-a37a277fbdbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987315774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3987315774
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1069839757
Short name T587
Test name
Test status
Simulation time 258692141 ps
CPU time 14.23 seconds
Started May 21 03:05:11 PM PDT 24
Finished May 21 03:05:27 PM PDT 24
Peak memory 248768 kb
Host smart-66014a72-1627-458d-89dd-1aba2ef022dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1069839757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1069839757
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1807544358
Short name T519
Test name
Test status
Simulation time 1170012211 ps
CPU time 107.5 seconds
Started May 21 03:05:11 PM PDT 24
Finished May 21 03:07:01 PM PDT 24
Peak memory 256820 kb
Host smart-a9e2f002-81d0-484e-bf73-1744d8d165a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075
44358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1807544358
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1021829623
Short name T223
Test name
Test status
Simulation time 3944699466 ps
CPU time 74.58 seconds
Started May 21 03:05:11 PM PDT 24
Finished May 21 03:06:28 PM PDT 24
Peak memory 248816 kb
Host smart-426d98bb-764a-4642-b0fe-fefb54e7b419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10218
29623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1021829623
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2763531869
Short name T552
Test name
Test status
Simulation time 6341580197 ps
CPU time 630.2 seconds
Started May 21 03:05:11 PM PDT 24
Finished May 21 03:15:43 PM PDT 24
Peak memory 272040 kb
Host smart-486da8c6-9bda-4072-8e04-a9233a6aebc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763531869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2763531869
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.16094604
Short name T689
Test name
Test status
Simulation time 68787475762 ps
CPU time 2222.15 seconds
Started May 21 03:05:12 PM PDT 24
Finished May 21 03:42:16 PM PDT 24
Peak memory 289252 kb
Host smart-0623ebbe-9eb4-417d-863e-1987bc4aeb93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16094604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.16094604
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4226668909
Short name T656
Test name
Test status
Simulation time 148009429 ps
CPU time 3.77 seconds
Started May 21 03:05:12 PM PDT 24
Finished May 21 03:05:17 PM PDT 24
Peak memory 240580 kb
Host smart-48a2047c-b55a-4d82-af1e-0217cbeb0f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42266
68909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4226668909
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.798823561
Short name T477
Test name
Test status
Simulation time 1290021744 ps
CPU time 17.85 seconds
Started May 21 03:05:10 PM PDT 24
Finished May 21 03:05:30 PM PDT 24
Peak memory 253076 kb
Host smart-2478b085-97b3-440f-a2a2-e6136763eaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79882
3561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.798823561
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3350293463
Short name T449
Test name
Test status
Simulation time 165688676 ps
CPU time 3.6 seconds
Started May 21 03:05:09 PM PDT 24
Finished May 21 03:05:15 PM PDT 24
Peak memory 240600 kb
Host smart-d55a5155-ad56-46f5-8a82-6d2679f402e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33502
93463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3350293463
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2468165961
Short name T532
Test name
Test status
Simulation time 1233024004 ps
CPU time 24.84 seconds
Started May 21 03:05:10 PM PDT 24
Finished May 21 03:05:37 PM PDT 24
Peak memory 248788 kb
Host smart-f78c9735-c1da-4fc5-be2c-65e097453cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
65961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2468165961
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2871568585
Short name T590
Test name
Test status
Simulation time 16689151517 ps
CPU time 1523.89 seconds
Started May 21 03:05:12 PM PDT 24
Finished May 21 03:30:38 PM PDT 24
Peak memory 289116 kb
Host smart-b8924942-5635-4cbd-bf24-126bbbbcda99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871568585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2871568585
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.763889863
Short name T191
Test name
Test status
Simulation time 136360660 ps
CPU time 3.56 seconds
Started May 21 03:05:19 PM PDT 24
Finished May 21 03:05:26 PM PDT 24
Peak memory 248940 kb
Host smart-04704e62-f77d-4970-a108-0848d7ef8597
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=763889863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.763889863
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2956537210
Short name T73
Test name
Test status
Simulation time 294568407744 ps
CPU time 2864.92 seconds
Started May 21 03:05:23 PM PDT 24
Finished May 21 03:53:11 PM PDT 24
Peak memory 289476 kb
Host smart-ace21e2a-5a92-4550-8a7c-35aa77be960d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956537210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2956537210
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2270111914
Short name T628
Test name
Test status
Simulation time 889286100 ps
CPU time 13.54 seconds
Started May 21 03:05:21 PM PDT 24
Finished May 21 03:05:38 PM PDT 24
Peak memory 248780 kb
Host smart-a6226a16-f7c9-46db-8e43-8e75570063eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2270111914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2270111914
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.857398764
Short name T538
Test name
Test status
Simulation time 4312157810 ps
CPU time 227.79 seconds
Started May 21 03:05:16 PM PDT 24
Finished May 21 03:09:06 PM PDT 24
Peak memory 256884 kb
Host smart-5f246991-c8da-4598-92ad-de1bc4f92ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85739
8764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.857398764
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.11698143
Short name T63
Test name
Test status
Simulation time 1816061744 ps
CPU time 53.62 seconds
Started May 21 03:05:15 PM PDT 24
Finished May 21 03:06:10 PM PDT 24
Peak memory 248824 kb
Host smart-532bd99b-b845-4d4a-9b7b-2227ffe36e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.11698143
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.983776888
Short name T560
Test name
Test status
Simulation time 149890113520 ps
CPU time 2348.44 seconds
Started May 21 03:05:21 PM PDT 24
Finished May 21 03:44:34 PM PDT 24
Peak memory 281684 kb
Host smart-15103c5d-a7ae-44e4-9a38-c5391b9a1756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983776888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.983776888
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1351994742
Short name T680
Test name
Test status
Simulation time 500126947 ps
CPU time 19.06 seconds
Started May 21 03:05:17 PM PDT 24
Finished May 21 03:05:38 PM PDT 24
Peak memory 248780 kb
Host smart-d6132cfc-f82e-4487-a244-95fbedfa09d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
94742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1351994742
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3487741897
Short name T370
Test name
Test status
Simulation time 1541012010 ps
CPU time 19.26 seconds
Started May 21 03:05:18 PM PDT 24
Finished May 21 03:05:39 PM PDT 24
Peak memory 248892 kb
Host smart-5cca64fd-564d-44c0-a29e-71eee58e2e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
41897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3487741897
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3580011653
Short name T659
Test name
Test status
Simulation time 252072185 ps
CPU time 17.68 seconds
Started May 21 03:05:16 PM PDT 24
Finished May 21 03:05:35 PM PDT 24
Peak memory 248744 kb
Host smart-d9de5221-ae59-4be1-9d62-33c615ebc997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35800
11653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3580011653
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1565215431
Short name T529
Test name
Test status
Simulation time 2470350778 ps
CPU time 10.52 seconds
Started May 21 03:05:17 PM PDT 24
Finished May 21 03:05:29 PM PDT 24
Peak memory 248860 kb
Host smart-52d72803-e2d4-4f1e-b543-28549bc680ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
15431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1565215431
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2295683768
Short name T512
Test name
Test status
Simulation time 8923827990 ps
CPU time 525.2 seconds
Started May 21 03:05:22 PM PDT 24
Finished May 21 03:14:11 PM PDT 24
Peak memory 256640 kb
Host smart-2ac7bd4d-6dc5-432c-a4c9-2db52c3513c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295683768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2295683768
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.560680664
Short name T195
Test name
Test status
Simulation time 110338720 ps
CPU time 4.75 seconds
Started May 21 03:05:32 PM PDT 24
Finished May 21 03:05:39 PM PDT 24
Peak memory 248952 kb
Host smart-b225db52-a3aa-44b1-8dd7-408ca9c6ce5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=560680664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.560680664
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.411132527
Short name T633
Test name
Test status
Simulation time 52005108594 ps
CPU time 1613.8 seconds
Started May 21 03:05:36 PM PDT 24
Finished May 21 03:32:32 PM PDT 24
Peak memory 283032 kb
Host smart-75500527-c457-48d5-a7c4-7bc9332c356f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411132527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.411132527
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1410936650
Short name T67
Test name
Test status
Simulation time 3274715193 ps
CPU time 156.47 seconds
Started May 21 03:05:27 PM PDT 24
Finished May 21 03:08:05 PM PDT 24
Peak memory 250928 kb
Host smart-73706393-9efc-4f0e-97fb-ddae7d5b9563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14109
36650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1410936650
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1658220400
Short name T178
Test name
Test status
Simulation time 1721836066 ps
CPU time 38.41 seconds
Started May 21 03:05:26 PM PDT 24
Finished May 21 03:06:06 PM PDT 24
Peak memory 248788 kb
Host smart-d5964332-0ad4-4945-a4ed-0e6b71ff1ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16582
20400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1658220400
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2959044350
Short name T288
Test name
Test status
Simulation time 25580848363 ps
CPU time 1219.41 seconds
Started May 21 03:05:32 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 285396 kb
Host smart-29e4481a-55bd-473e-8ada-c6de4f612179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959044350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2959044350
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2757084206
Short name T216
Test name
Test status
Simulation time 28589381940 ps
CPU time 1098.78 seconds
Started May 21 03:05:32 PM PDT 24
Finished May 21 03:23:54 PM PDT 24
Peak memory 289780 kb
Host smart-e27bdd9c-23f6-4e7c-9f8c-d737cc79bc6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757084206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2757084206
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3107625670
Short name T395
Test name
Test status
Simulation time 519456027 ps
CPU time 11.48 seconds
Started May 21 03:05:20 PM PDT 24
Finished May 21 03:05:34 PM PDT 24
Peak memory 253052 kb
Host smart-7b32afc1-532b-451b-aad3-76af0571b339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
25670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3107625670
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2561454983
Short name T74
Test name
Test status
Simulation time 276442187 ps
CPU time 25.54 seconds
Started May 21 03:05:22 PM PDT 24
Finished May 21 03:05:51 PM PDT 24
Peak memory 249244 kb
Host smart-d20cf64f-c59e-4027-8ed8-3595ebcf8f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614
54983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2561454983
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3504116668
Short name T261
Test name
Test status
Simulation time 354073188 ps
CPU time 27.08 seconds
Started May 21 03:05:33 PM PDT 24
Finished May 21 03:06:03 PM PDT 24
Peak memory 249100 kb
Host smart-a03d15c1-e423-4c99-bef3-6bab9bd5736e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35041
16668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3504116668
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2320620188
Short name T484
Test name
Test status
Simulation time 1118402726 ps
CPU time 18.96 seconds
Started May 21 03:05:21 PM PDT 24
Finished May 21 03:05:43 PM PDT 24
Peak memory 248804 kb
Host smart-1f67cf0b-b3d5-4bfd-b225-b55fc3b3349a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
20188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2320620188
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2520355111
Short name T102
Test name
Test status
Simulation time 478839260368 ps
CPU time 1608.47 seconds
Started May 21 03:05:32 PM PDT 24
Finished May 21 03:32:23 PM PDT 24
Peak memory 281720 kb
Host smart-314a0f4e-78ea-4933-8d41-7b485b39b9ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520355111 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2520355111
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1205084951
Short name T695
Test name
Test status
Simulation time 116291317557 ps
CPU time 2015.27 seconds
Started May 21 03:05:40 PM PDT 24
Finished May 21 03:39:18 PM PDT 24
Peak memory 288948 kb
Host smart-498d85b4-8ff1-4a5f-bbcf-8d742d8043a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205084951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1205084951
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3135800015
Short name T643
Test name
Test status
Simulation time 388381117 ps
CPU time 18.75 seconds
Started May 21 03:05:40 PM PDT 24
Finished May 21 03:06:01 PM PDT 24
Peak memory 248768 kb
Host smart-b67b8aad-a20f-47d2-8101-9ef940baf61c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3135800015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3135800015
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3014345554
Short name T501
Test name
Test status
Simulation time 5513348689 ps
CPU time 88.29 seconds
Started May 21 03:05:39 PM PDT 24
Finished May 21 03:07:09 PM PDT 24
Peak memory 256992 kb
Host smart-55057c32-708f-493b-8c3f-7e4a204ecd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143
45554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3014345554
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2390998171
Short name T710
Test name
Test status
Simulation time 3990864680 ps
CPU time 59.89 seconds
Started May 21 03:05:32 PM PDT 24
Finished May 21 03:06:35 PM PDT 24
Peak memory 256796 kb
Host smart-2b452591-62bf-4c7d-9033-b3f00c3a019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
98171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2390998171
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2471022326
Short name T318
Test name
Test status
Simulation time 20765906246 ps
CPU time 743.38 seconds
Started May 21 03:05:40 PM PDT 24
Finished May 21 03:18:06 PM PDT 24
Peak memory 265200 kb
Host smart-2138efee-315b-41fc-8425-c0a468f2e4ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471022326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2471022326
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1076979328
Short name T654
Test name
Test status
Simulation time 32263881792 ps
CPU time 617.52 seconds
Started May 21 03:05:39 PM PDT 24
Finished May 21 03:15:59 PM PDT 24
Peak memory 256432 kb
Host smart-5eedecf4-8b8b-4c79-a518-225ed8a47946
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076979328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1076979328
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.736822485
Short name T58
Test name
Test status
Simulation time 4044587853 ps
CPU time 54.89 seconds
Started May 21 03:05:36 PM PDT 24
Finished May 21 03:06:33 PM PDT 24
Peak memory 248832 kb
Host smart-954a036d-c0b9-4e4d-b83a-0ce13a5f2fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73682
2485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.736822485
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.423210514
Short name T534
Test name
Test status
Simulation time 23744704 ps
CPU time 2.83 seconds
Started May 21 03:05:33 PM PDT 24
Finished May 21 03:05:38 PM PDT 24
Peak memory 240548 kb
Host smart-1bf2c660-5908-4acc-b709-847f7daa21fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42321
0514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.423210514
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3436781475
Short name T651
Test name
Test status
Simulation time 184364127 ps
CPU time 13.08 seconds
Started May 21 03:05:38 PM PDT 24
Finished May 21 03:05:53 PM PDT 24
Peak memory 248800 kb
Host smart-838271d9-c7c8-4d71-bfe8-91827fc1089b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
81475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3436781475
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3263603328
Short name T625
Test name
Test status
Simulation time 868046375 ps
CPU time 19.52 seconds
Started May 21 03:05:33 PM PDT 24
Finished May 21 03:05:55 PM PDT 24
Peak memory 248792 kb
Host smart-482d25f9-9fc5-488d-9738-8704920215b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
03328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3263603328
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3204350102
Short name T268
Test name
Test status
Simulation time 41607361121 ps
CPU time 2441.62 seconds
Started May 21 03:05:38 PM PDT 24
Finished May 21 03:46:22 PM PDT 24
Peak memory 284044 kb
Host smart-c3322c55-f99d-441a-aeef-264ca61a800d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204350102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3204350102
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.823388986
Short name T616
Test name
Test status
Simulation time 36680416376 ps
CPU time 4334.32 seconds
Started May 21 03:05:39 PM PDT 24
Finished May 21 04:17:56 PM PDT 24
Peak memory 337632 kb
Host smart-b22b0508-719d-4455-966f-b6fa63916aa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823388986 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.823388986
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2472598265
Short name T203
Test name
Test status
Simulation time 127754797 ps
CPU time 3.52 seconds
Started May 21 03:05:44 PM PDT 24
Finished May 21 03:05:49 PM PDT 24
Peak memory 248900 kb
Host smart-053d2a00-f3fd-4f5b-985e-c2b6560e4460
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2472598265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2472598265
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.436471274
Short name T414
Test name
Test status
Simulation time 59030022453 ps
CPU time 3342.14 seconds
Started May 21 03:05:44 PM PDT 24
Finished May 21 04:01:28 PM PDT 24
Peak memory 289164 kb
Host smart-f0eeda19-9dc6-4b4e-b851-452b295e6213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436471274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.436471274
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.4024505272
Short name T59
Test name
Test status
Simulation time 142466319 ps
CPU time 9.88 seconds
Started May 21 03:05:44 PM PDT 24
Finished May 21 03:05:56 PM PDT 24
Peak memory 248772 kb
Host smart-756b7305-30ac-42ef-aad5-d6b8bb768b71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4024505272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.4024505272
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3886038110
Short name T631
Test name
Test status
Simulation time 2672054160 ps
CPU time 156.15 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:08:24 PM PDT 24
Peak memory 249964 kb
Host smart-b3e489e1-e157-4ed8-b028-445971c1f15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38860
38110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3886038110
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3783551772
Short name T614
Test name
Test status
Simulation time 285722508 ps
CPU time 29.75 seconds
Started May 21 03:05:44 PM PDT 24
Finished May 21 03:06:17 PM PDT 24
Peak memory 255976 kb
Host smart-0d949fd7-7ebc-4686-bf6f-eebef02b21e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37835
51772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3783551772
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3341695126
Short name T321
Test name
Test status
Simulation time 180048224069 ps
CPU time 2315.85 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:44:23 PM PDT 24
Peak memory 272876 kb
Host smart-abc8e7aa-011d-4a99-a153-154a8ddc0a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341695126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3341695126
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.349930341
Short name T358
Test name
Test status
Simulation time 166661835995 ps
CPU time 2452.07 seconds
Started May 21 03:05:46 PM PDT 24
Finished May 21 03:46:40 PM PDT 24
Peak memory 283000 kb
Host smart-219c0d41-1d86-4942-a5b0-c43a06705298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349930341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.349930341
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3063885623
Short name T91
Test name
Test status
Simulation time 397691043 ps
CPU time 38.7 seconds
Started May 21 03:05:40 PM PDT 24
Finished May 21 03:06:21 PM PDT 24
Peak memory 255972 kb
Host smart-41017cc1-e9db-4afb-a35d-ff70bb0a5dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
85623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3063885623
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.677858023
Short name T68
Test name
Test status
Simulation time 189948247 ps
CPU time 21.01 seconds
Started May 21 03:05:39 PM PDT 24
Finished May 21 03:06:02 PM PDT 24
Peak memory 255320 kb
Host smart-b4a453e6-2b21-4c2e-bba2-6e5751c30f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67785
8023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.677858023
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.826094609
Short name T89
Test name
Test status
Simulation time 74450659 ps
CPU time 10.07 seconds
Started May 21 03:05:39 PM PDT 24
Finished May 21 03:05:51 PM PDT 24
Peak memory 248764 kb
Host smart-b7a52938-451f-40b4-81b4-c35078de92fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82609
4609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.826094609
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.115808820
Short name T542
Test name
Test status
Simulation time 114124778235 ps
CPU time 3328.25 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 04:01:16 PM PDT 24
Peak memory 289300 kb
Host smart-bd4fefe6-2491-4b74-a0b3-edfa9234e7d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115808820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.115808820
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.616369563
Short name T193
Test name
Test status
Simulation time 63405362 ps
CPU time 3.4 seconds
Started May 21 03:05:55 PM PDT 24
Finished May 21 03:06:00 PM PDT 24
Peak memory 248912 kb
Host smart-6777bbb0-ffcb-4e4d-b76f-7a3a5fe5e61f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=616369563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.616369563
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.813058473
Short name T473
Test name
Test status
Simulation time 27301446416 ps
CPU time 895.31 seconds
Started May 21 03:05:50 PM PDT 24
Finished May 21 03:20:46 PM PDT 24
Peak memory 289376 kb
Host smart-06d670f3-6480-48d3-a255-0bef1acb7b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813058473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.813058473
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.731373859
Short name T360
Test name
Test status
Simulation time 2600349450 ps
CPU time 30.35 seconds
Started May 21 03:05:54 PM PDT 24
Finished May 21 03:06:25 PM PDT 24
Peak memory 248836 kb
Host smart-eff79691-c0b5-4605-91ed-8cbb2384d82c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=731373859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.731373859
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3242131417
Short name T636
Test name
Test status
Simulation time 13656944316 ps
CPU time 201.1 seconds
Started May 21 03:05:50 PM PDT 24
Finished May 21 03:09:12 PM PDT 24
Peak memory 256996 kb
Host smart-0bef5e25-5b41-4dc6-845f-7495f55f347a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
31417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3242131417
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.432189296
Short name T85
Test name
Test status
Simulation time 127225171 ps
CPU time 7.78 seconds
Started May 21 03:05:43 PM PDT 24
Finished May 21 03:05:52 PM PDT 24
Peak memory 248756 kb
Host smart-42ebae6c-2aea-422f-b4e3-d7413fed843d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43218
9296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.432189296
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1593007075
Short name T682
Test name
Test status
Simulation time 158324117106 ps
CPU time 1254.19 seconds
Started May 21 03:05:49 PM PDT 24
Finished May 21 03:26:45 PM PDT 24
Peak memory 265228 kb
Host smart-63d49736-f9fd-4bf1-aa6d-5de119b73194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593007075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1593007075
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.377478844
Short name T93
Test name
Test status
Simulation time 48774853815 ps
CPU time 1328 seconds
Started May 21 03:05:51 PM PDT 24
Finished May 21 03:28:00 PM PDT 24
Peak memory 287444 kb
Host smart-de3f2a14-c96a-4f03-a11f-c4b39537c046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377478844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.377478844
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2997764669
Short name T297
Test name
Test status
Simulation time 9604594152 ps
CPU time 366.64 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:12:04 PM PDT 24
Peak memory 248024 kb
Host smart-558b644a-1527-4ea6-95b8-63a70eca3d4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997764669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2997764669
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.9022446
Short name T387
Test name
Test status
Simulation time 706247148 ps
CPU time 20.74 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:06:08 PM PDT 24
Peak memory 248776 kb
Host smart-1511bd3f-3397-41ef-bf5c-796365cb6078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90224
46 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.9022446
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.97338850
Short name T183
Test name
Test status
Simulation time 2676568628 ps
CPU time 40.75 seconds
Started May 21 03:05:45 PM PDT 24
Finished May 21 03:06:28 PM PDT 24
Peak memory 248860 kb
Host smart-4c3e8401-22b6-4452-ac3a-58fd89a52a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97338
850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.97338850
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.4127088494
Short name T630
Test name
Test status
Simulation time 1917046012 ps
CPU time 37.83 seconds
Started May 21 03:05:49 PM PDT 24
Finished May 21 03:06:28 PM PDT 24
Peak memory 248796 kb
Host smart-138e8c05-193a-4e65-9031-7a4bcf43b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
88494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4127088494
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4051541107
Short name T420
Test name
Test status
Simulation time 1191102529 ps
CPU time 51.94 seconds
Started May 21 03:05:46 PM PDT 24
Finished May 21 03:06:40 PM PDT 24
Peak memory 248776 kb
Host smart-a58a3ab1-4b3d-4071-9aae-d6f513290eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
41107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4051541107
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1155793278
Short name T179
Test name
Test status
Simulation time 50200561 ps
CPU time 3.61 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:06:01 PM PDT 24
Peak memory 248956 kb
Host smart-15f9b013-5be4-476b-a456-5ef8578fb501
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1155793278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1155793278
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2150369976
Short name T367
Test name
Test status
Simulation time 865184746 ps
CPU time 33.86 seconds
Started May 21 03:05:58 PM PDT 24
Finished May 21 03:06:33 PM PDT 24
Peak memory 248756 kb
Host smart-3487d56f-05e4-4340-ba54-ce57782b0603
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2150369976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2150369976
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3499577709
Short name T480
Test name
Test status
Simulation time 4649855272 ps
CPU time 107.23 seconds
Started May 21 03:05:50 PM PDT 24
Finished May 21 03:07:38 PM PDT 24
Peak memory 257004 kb
Host smart-7770e8ce-60ed-4149-8a55-fa5c831ac85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
77709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3499577709
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.716680920
Short name T16
Test name
Test status
Simulation time 93572007 ps
CPU time 5.13 seconds
Started May 21 03:05:49 PM PDT 24
Finished May 21 03:05:54 PM PDT 24
Peak memory 248792 kb
Host smart-02b4db3f-8ace-4174-ba5e-a3a72ca359e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71668
0920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.716680920
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.125573447
Short name T524
Test name
Test status
Simulation time 265083960107 ps
CPU time 2312.27 seconds
Started May 21 03:05:55 PM PDT 24
Finished May 21 03:44:29 PM PDT 24
Peak memory 272344 kb
Host smart-90daa7e0-463d-437d-bcfc-673c06262a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125573447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.125573447
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4273614090
Short name T402
Test name
Test status
Simulation time 26181442354 ps
CPU time 1646.86 seconds
Started May 21 03:05:54 PM PDT 24
Finished May 21 03:33:22 PM PDT 24
Peak memory 281668 kb
Host smart-5045d434-ba24-466b-880f-afbf2a2c483f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273614090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4273614090
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3538282654
Short name T283
Test name
Test status
Simulation time 2667464457 ps
CPU time 110.64 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:07:48 PM PDT 24
Peak memory 254976 kb
Host smart-75168f9e-a0c1-47bb-9b2c-e6bb40129d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538282654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3538282654
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1521528725
Short name T550
Test name
Test status
Simulation time 474825271 ps
CPU time 37.55 seconds
Started May 21 03:05:49 PM PDT 24
Finished May 21 03:06:28 PM PDT 24
Peak memory 248772 kb
Host smart-e63e9434-cdfe-475d-9645-837f9bb45da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
28725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1521528725
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2720406028
Short name T31
Test name
Test status
Simulation time 414359660 ps
CPU time 27.79 seconds
Started May 21 03:05:51 PM PDT 24
Finished May 21 03:06:20 PM PDT 24
Peak memory 254972 kb
Host smart-011cfa42-5afb-442e-8721-90ebf2cb51c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27204
06028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2720406028
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3042313281
Short name T292
Test name
Test status
Simulation time 801890700 ps
CPU time 22.31 seconds
Started May 21 03:05:54 PM PDT 24
Finished May 21 03:06:17 PM PDT 24
Peak memory 247456 kb
Host smart-c2203c3a-3b36-4e80-b873-7a2fe36b905b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30423
13281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3042313281
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1061197896
Short name T700
Test name
Test status
Simulation time 284707212 ps
CPU time 25.84 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:06:23 PM PDT 24
Peak memory 255676 kb
Host smart-90dac90e-021a-4385-a500-39da862a050c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10611
97896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1061197896
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2959346991
Short name T43
Test name
Test status
Simulation time 2761740833 ps
CPU time 121.84 seconds
Started May 21 03:05:57 PM PDT 24
Finished May 21 03:08:00 PM PDT 24
Peak memory 256944 kb
Host smart-3c26fa0c-dd2c-4fd2-999d-17c0813ea5a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959346991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2959346991
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3046963241
Short name T206
Test name
Test status
Simulation time 222878841 ps
CPU time 3.77 seconds
Started May 21 03:06:02 PM PDT 24
Finished May 21 03:06:07 PM PDT 24
Peak memory 248960 kb
Host smart-090379db-0076-4601-93d9-e4122981a0ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3046963241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3046963241
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.948168749
Short name T513
Test name
Test status
Simulation time 682149237436 ps
CPU time 2692.59 seconds
Started May 21 03:06:01 PM PDT 24
Finished May 21 03:50:55 PM PDT 24
Peak memory 273140 kb
Host smart-5fa38d2d-894a-474c-96c9-04a30aa84bcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948168749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.948168749
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3176237526
Short name T655
Test name
Test status
Simulation time 313801547 ps
CPU time 6.18 seconds
Started May 21 03:06:02 PM PDT 24
Finished May 21 03:06:09 PM PDT 24
Peak memory 248796 kb
Host smart-8d4f87b4-1b7b-4c7e-87ef-c3b32a7bcf03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3176237526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3176237526
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4171592411
Short name T398
Test name
Test status
Simulation time 909383184 ps
CPU time 62.91 seconds
Started May 21 03:05:55 PM PDT 24
Finished May 21 03:06:59 PM PDT 24
Peak memory 256808 kb
Host smart-d22183c7-76b6-49c5-b9b6-5577b668ce2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715
92411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4171592411
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.630496648
Short name T596
Test name
Test status
Simulation time 956548148 ps
CPU time 27.16 seconds
Started May 21 03:05:54 PM PDT 24
Finished May 21 03:06:23 PM PDT 24
Peak memory 249948 kb
Host smart-59e6a07c-9258-49ef-9d41-4cc774247770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63049
6648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.630496648
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2138337137
Short name T502
Test name
Test status
Simulation time 225673046384 ps
CPU time 1544.84 seconds
Started May 21 03:06:01 PM PDT 24
Finished May 21 03:31:46 PM PDT 24
Peak memory 289216 kb
Host smart-d409df49-5bf8-4a40-b5a2-4836fc5d8b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138337137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2138337137
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3328482143
Short name T229
Test name
Test status
Simulation time 22519703558 ps
CPU time 1301.14 seconds
Started May 21 03:06:02 PM PDT 24
Finished May 21 03:27:45 PM PDT 24
Peak memory 273140 kb
Host smart-1c4e220c-0567-499d-baa0-3b85f39e6628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328482143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3328482143
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.919572428
Short name T520
Test name
Test status
Simulation time 5406225238 ps
CPU time 218.97 seconds
Started May 21 03:06:03 PM PDT 24
Finished May 21 03:09:43 PM PDT 24
Peak memory 247120 kb
Host smart-21bc77f8-aac8-4140-a657-f0a37c34ad40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919572428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.919572428
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2359129831
Short name T422
Test name
Test status
Simulation time 2777086976 ps
CPU time 37.62 seconds
Started May 21 03:05:56 PM PDT 24
Finished May 21 03:06:35 PM PDT 24
Peak memory 248836 kb
Host smart-37390fdf-2ac3-48f5-8c29-f19a32a7d66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
29831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2359129831
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3112606740
Short name T561
Test name
Test status
Simulation time 674662009 ps
CPU time 51.4 seconds
Started May 21 03:05:55 PM PDT 24
Finished May 21 03:06:48 PM PDT 24
Peak memory 256664 kb
Host smart-40239e85-10ab-4e86-83bc-06230420a0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
06740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3112606740
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3753417803
Short name T403
Test name
Test status
Simulation time 702276041 ps
CPU time 44 seconds
Started May 21 03:05:55 PM PDT 24
Finished May 21 03:06:40 PM PDT 24
Peak memory 255932 kb
Host smart-e3cd0189-fb23-4ff5-8c1e-96dd04acbad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
17803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3753417803
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1632537802
Short name T55
Test name
Test status
Simulation time 62192961558 ps
CPU time 1014.57 seconds
Started May 21 03:06:02 PM PDT 24
Finished May 21 03:22:58 PM PDT 24
Peak memory 281648 kb
Host smart-16613bfa-05b7-4029-aae6-68fc071e2b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632537802 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1632537802
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2441879662
Short name T197
Test name
Test status
Simulation time 20508163 ps
CPU time 2.35 seconds
Started May 21 03:06:13 PM PDT 24
Finished May 21 03:06:17 PM PDT 24
Peak memory 248928 kb
Host smart-0c064b97-3a71-4855-869a-e83b29f7b465
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2441879662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2441879662
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2996719871
Short name T76
Test name
Test status
Simulation time 10689361775 ps
CPU time 923.44 seconds
Started May 21 03:06:08 PM PDT 24
Finished May 21 03:21:33 PM PDT 24
Peak memory 273424 kb
Host smart-d86c03df-26a9-4fec-a7cc-89925a785c9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996719871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2996719871
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3568031970
Short name T626
Test name
Test status
Simulation time 1502277324 ps
CPU time 35.77 seconds
Started May 21 03:06:09 PM PDT 24
Finished May 21 03:06:45 PM PDT 24
Peak memory 248756 kb
Host smart-4c7c2ab6-ddd3-426d-a201-8ae68957d99b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3568031970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3568031970
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1601297764
Short name T459
Test name
Test status
Simulation time 5163860633 ps
CPU time 79.47 seconds
Started May 21 03:06:07 PM PDT 24
Finished May 21 03:07:28 PM PDT 24
Peak memory 256440 kb
Host smart-9428e5f2-551d-4d00-8a96-a2b7a53aa285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16012
97764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1601297764
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2580901666
Short name T572
Test name
Test status
Simulation time 1298872130 ps
CPU time 73.98 seconds
Started May 21 03:06:09 PM PDT 24
Finished May 21 03:07:24 PM PDT 24
Peak memory 248784 kb
Host smart-18bb2f51-f33d-4dbd-99cb-472eff137956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
01666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2580901666
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2707384497
Short name T287
Test name
Test status
Simulation time 15356747686 ps
CPU time 658.09 seconds
Started May 21 03:06:07 PM PDT 24
Finished May 21 03:17:05 PM PDT 24
Peak memory 272524 kb
Host smart-75f77948-2988-4779-a54c-d45b8740888b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707384497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2707384497
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1987680114
Short name T660
Test name
Test status
Simulation time 15133594338 ps
CPU time 1457.23 seconds
Started May 21 03:06:08 PM PDT 24
Finished May 21 03:30:27 PM PDT 24
Peak memory 288640 kb
Host smart-641e4482-265b-4fd0-a390-48cae165fb4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987680114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1987680114
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2954441624
Short name T302
Test name
Test status
Simulation time 54057111979 ps
CPU time 407.1 seconds
Started May 21 03:06:07 PM PDT 24
Finished May 21 03:12:56 PM PDT 24
Peak memory 255500 kb
Host smart-30ba706b-7786-429f-9e22-963db16fb446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954441624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2954441624
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4260854048
Short name T439
Test name
Test status
Simulation time 1088831526 ps
CPU time 61.73 seconds
Started May 21 03:06:05 PM PDT 24
Finished May 21 03:07:07 PM PDT 24
Peak memory 255904 kb
Host smart-46340a98-3f57-4a18-8046-49f82f032b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
54048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4260854048
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.572130394
Short name T419
Test name
Test status
Simulation time 3022261870 ps
CPU time 16.73 seconds
Started May 21 03:06:08 PM PDT 24
Finished May 21 03:06:26 PM PDT 24
Peak memory 254320 kb
Host smart-cb88734e-1c78-460d-b0e8-2f42950b7bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57213
0394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.572130394
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1921567934
Short name T423
Test name
Test status
Simulation time 402118560 ps
CPU time 24.95 seconds
Started May 21 03:06:08 PM PDT 24
Finished May 21 03:06:34 PM PDT 24
Peak memory 254188 kb
Host smart-c9caf2bb-f955-4ef3-b1d4-6d97e774d1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
67934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1921567934
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3131564395
Short name T394
Test name
Test status
Simulation time 1862999778 ps
CPU time 49.54 seconds
Started May 21 03:06:01 PM PDT 24
Finished May 21 03:06:51 PM PDT 24
Peak memory 255976 kb
Host smart-6920ac05-9bc0-4bd9-a085-21ae6468267c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
64395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3131564395
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3818301906
Short name T463
Test name
Test status
Simulation time 408805032 ps
CPU time 26.97 seconds
Started May 21 03:06:07 PM PDT 24
Finished May 21 03:06:35 PM PDT 24
Peak memory 248884 kb
Host smart-2d6d044a-8cea-4aed-be4d-ff2c3b9aa5b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818301906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3818301906
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.81172196
Short name T675
Test name
Test status
Simulation time 297970118843 ps
CPU time 7411.01 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 05:09:49 PM PDT 24
Peak memory 367184 kb
Host smart-c1ce06c4-b878-4bf8-8af1-34a7674efa48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81172196 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.81172196
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2775792089
Short name T202
Test name
Test status
Simulation time 171694544 ps
CPU time 3.94 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 03:06:20 PM PDT 24
Peak memory 248936 kb
Host smart-c2098bb0-4dd2-4a99-b5b1-45fea2bddcfc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2775792089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2775792089
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1933279370
Short name T221
Test name
Test status
Simulation time 387096383528 ps
CPU time 2923.87 seconds
Started May 21 03:06:16 PM PDT 24
Finished May 21 03:55:02 PM PDT 24
Peak memory 281668 kb
Host smart-7d615cd0-9cba-4497-a971-5e5c04bb57a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933279370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1933279370
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2189418961
Short name T658
Test name
Test status
Simulation time 536463358 ps
CPU time 24.09 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 03:06:41 PM PDT 24
Peak memory 248800 kb
Host smart-5b355a81-d9c4-4cee-9533-996e4e0bdc17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2189418961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2189418961
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3600039909
Short name T591
Test name
Test status
Simulation time 26269229 ps
CPU time 3 seconds
Started May 21 03:06:14 PM PDT 24
Finished May 21 03:06:19 PM PDT 24
Peak memory 239140 kb
Host smart-f6ff4fc6-c807-4806-9698-8a6fbb872bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36000
39909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3600039909
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.830144769
Short name T332
Test name
Test status
Simulation time 19485024340 ps
CPU time 1089.95 seconds
Started May 21 03:06:13 PM PDT 24
Finished May 21 03:24:25 PM PDT 24
Peak memory 270328 kb
Host smart-f86084ed-4876-4c3f-b58b-3154764ef4df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830144769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.830144769
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2048729719
Short name T184
Test name
Test status
Simulation time 10736035631 ps
CPU time 1177.33 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 272792 kb
Host smart-85679fa0-b47a-4b0e-8bbf-d680b049cc2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048729719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2048729719
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2233618318
Short name T683
Test name
Test status
Simulation time 9865110505 ps
CPU time 379.64 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 03:12:37 PM PDT 24
Peak memory 248032 kb
Host smart-c141e99f-2539-4308-9c11-c927bc8b7935
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233618318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2233618318
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.75432813
Short name T271
Test name
Test status
Simulation time 3114403334 ps
CPU time 51.2 seconds
Started May 21 03:06:14 PM PDT 24
Finished May 21 03:07:07 PM PDT 24
Peak memory 256140 kb
Host smart-b4cbe2c5-9a20-45f8-b051-3c0fc91439e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75432
813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.75432813
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3316777443
Short name T22
Test name
Test status
Simulation time 511695452 ps
CPU time 16.83 seconds
Started May 21 03:06:16 PM PDT 24
Finished May 21 03:06:35 PM PDT 24
Peak memory 252840 kb
Host smart-259a3fcd-bf2d-44cf-8d86-81a867f7e2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
77443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3316777443
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2027540334
Short name T653
Test name
Test status
Simulation time 641222025 ps
CPU time 38.4 seconds
Started May 21 03:06:12 PM PDT 24
Finished May 21 03:06:51 PM PDT 24
Peak memory 255948 kb
Host smart-ff8b6ff1-aee3-448c-aa55-07351a792fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
40334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2027540334
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2657761695
Short name T400
Test name
Test status
Simulation time 1565597966 ps
CPU time 47.26 seconds
Started May 21 03:06:15 PM PDT 24
Finished May 21 03:07:04 PM PDT 24
Peak memory 256008 kb
Host smart-e3afeccc-65eb-445a-b37c-7dd1b74277cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
61695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2657761695
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3334818266
Short name T641
Test name
Test status
Simulation time 187908347379 ps
CPU time 3004.58 seconds
Started May 21 03:06:11 PM PDT 24
Finished May 21 03:56:17 PM PDT 24
Peak memory 298772 kb
Host smart-4e3ff6ab-136a-496a-bac3-1ab17c69a9f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334818266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3334818266
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2279217959
Short name T642
Test name
Test status
Simulation time 83551742280 ps
CPU time 3820.2 seconds
Started May 21 03:06:17 PM PDT 24
Finished May 21 04:09:59 PM PDT 24
Peak memory 289840 kb
Host smart-7de6024c-ffa5-4268-b43a-b0615b49f144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279217959 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2279217959
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3060234745
Short name T200
Test name
Test status
Simulation time 146517548 ps
CPU time 3.78 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:04:46 PM PDT 24
Peak memory 248988 kb
Host smart-a0c2303e-1c46-4e8b-be98-0adaac4dc839
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3060234745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3060234745
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.118111281
Short name T640
Test name
Test status
Simulation time 30842374886 ps
CPU time 1949.74 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:37:15 PM PDT 24
Peak memory 273020 kb
Host smart-ea4f6b91-f157-4f24-90af-6f88943a4349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118111281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.118111281
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2653231436
Short name T461
Test name
Test status
Simulation time 1553072683 ps
CPU time 15.15 seconds
Started May 21 03:04:41 PM PDT 24
Finished May 21 03:05:00 PM PDT 24
Peak memory 248736 kb
Host smart-c74cde34-225a-4878-b49a-8a1ed6d65dc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2653231436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2653231436
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2033207609
Short name T363
Test name
Test status
Simulation time 1096219857 ps
CPU time 16.46 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:04:56 PM PDT 24
Peak memory 255792 kb
Host smart-8d07209c-652f-4c43-a872-ebba40d7a88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
07609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2033207609
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1790005758
Short name T426
Test name
Test status
Simulation time 263933474 ps
CPU time 19.29 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:04:58 PM PDT 24
Peak memory 255748 kb
Host smart-67a72e6a-e9e5-489e-b275-e05aae300479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
05758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1790005758
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2533097063
Short name T94
Test name
Test status
Simulation time 48548993102 ps
CPU time 2795.89 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:51:22 PM PDT 24
Peak memory 281648 kb
Host smart-18fb00ec-207d-4e20-ae16-8fcc4963062e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533097063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2533097063
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1027597323
Short name T385
Test name
Test status
Simulation time 6368592845 ps
CPU time 59.39 seconds
Started May 21 03:04:36 PM PDT 24
Finished May 21 03:05:36 PM PDT 24
Peak memory 256204 kb
Host smart-9f71825a-352a-44ac-b990-f88ccbe73f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
97323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1027597323
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1273795426
Short name T432
Test name
Test status
Simulation time 374009243 ps
CPU time 24.82 seconds
Started May 21 03:04:37 PM PDT 24
Finished May 21 03:05:04 PM PDT 24
Peak memory 248720 kb
Host smart-646c381e-1dc0-4dcf-a01f-13f70a3a6107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
95426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1273795426
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.9045668
Short name T34
Test name
Test status
Simulation time 4169571562 ps
CPU time 24.78 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:05:11 PM PDT 24
Peak memory 273068 kb
Host smart-2f9e5b33-846f-48bc-a850-49ac6ea036b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=9045668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.9045668
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1013880097
Short name T482
Test name
Test status
Simulation time 1028746754 ps
CPU time 30.1 seconds
Started May 21 03:04:35 PM PDT 24
Finished May 21 03:05:06 PM PDT 24
Peak memory 254908 kb
Host smart-050c47ad-24be-42a2-97b2-3903b182a2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10138
80097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1013880097
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2743841244
Short name T21
Test name
Test status
Simulation time 645934415 ps
CPU time 35.96 seconds
Started May 21 03:04:35 PM PDT 24
Finished May 21 03:05:12 PM PDT 24
Peak memory 256084 kb
Host smart-02d67f65-1939-418e-a2a9-5e61e3f384c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438
41244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2743841244
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1146306103
Short name T565
Test name
Test status
Simulation time 13879691978 ps
CPU time 1363.53 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 289556 kb
Host smart-11a0d44c-0dd8-4dd1-b27d-2b3014a77f0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146306103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1146306103
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2791219693
Short name T498
Test name
Test status
Simulation time 53479692601 ps
CPU time 1150.62 seconds
Started May 21 03:06:22 PM PDT 24
Finished May 21 03:25:34 PM PDT 24
Peak memory 283780 kb
Host smart-1026bf2a-f34f-4e93-a254-3fa6f7be662a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791219693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2791219693
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3176926468
Short name T410
Test name
Test status
Simulation time 968202552 ps
CPU time 55.02 seconds
Started May 21 03:06:20 PM PDT 24
Finished May 21 03:07:17 PM PDT 24
Peak memory 256092 kb
Host smart-44fb0c29-9d10-4b92-a957-ac04b97428ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
26468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3176926468
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.816370061
Short name T522
Test name
Test status
Simulation time 544621459 ps
CPU time 29.97 seconds
Started May 21 03:06:21 PM PDT 24
Finished May 21 03:06:52 PM PDT 24
Peak memory 256152 kb
Host smart-13de6b38-d911-495a-be88-f826ec5fcdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81637
0061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.816370061
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2386514993
Short name T319
Test name
Test status
Simulation time 132872033474 ps
CPU time 1969.35 seconds
Started May 21 03:06:21 PM PDT 24
Finished May 21 03:39:12 PM PDT 24
Peak memory 288444 kb
Host smart-d6578db1-24f6-461b-8da0-f94e3f707f35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386514993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2386514993
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1212949033
Short name T679
Test name
Test status
Simulation time 12199513238 ps
CPU time 1167.25 seconds
Started May 21 03:06:26 PM PDT 24
Finished May 21 03:25:54 PM PDT 24
Peak memory 273408 kb
Host smart-53be5aec-a151-4098-8322-d63d4a79bf9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212949033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1212949033
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1902044279
Short name T291
Test name
Test status
Simulation time 24111860514 ps
CPU time 513.2 seconds
Started May 21 03:06:22 PM PDT 24
Finished May 21 03:14:56 PM PDT 24
Peak memory 248172 kb
Host smart-515c0a67-5ea8-4c4b-9b28-844bc0f37b4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902044279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1902044279
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2643828350
Short name T47
Test name
Test status
Simulation time 392798837 ps
CPU time 24.61 seconds
Started May 21 03:06:19 PM PDT 24
Finished May 21 03:06:45 PM PDT 24
Peak memory 248828 kb
Host smart-1d6fc618-58af-435f-94e1-6e173cb11f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26438
28350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2643828350
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1541524579
Short name T270
Test name
Test status
Simulation time 523969203 ps
CPU time 33.59 seconds
Started May 21 03:06:21 PM PDT 24
Finished May 21 03:06:56 PM PDT 24
Peak memory 249140 kb
Host smart-cbcb5ae7-e3bb-4976-8f9c-92402d17a5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
24579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1541524579
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.247073004
Short name T389
Test name
Test status
Simulation time 1171961892 ps
CPU time 35.52 seconds
Started May 21 03:06:20 PM PDT 24
Finished May 21 03:06:57 PM PDT 24
Peak memory 254784 kb
Host smart-43c75cb8-e9e4-4586-a4a5-8138b352159c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
3004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.247073004
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3573826224
Short name T648
Test name
Test status
Simulation time 292209005 ps
CPU time 5.55 seconds
Started May 21 03:06:21 PM PDT 24
Finished May 21 03:06:28 PM PDT 24
Peak memory 248872 kb
Host smart-d01d1a51-36cb-4717-ae46-508a4f6802ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
26224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3573826224
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.317508149
Short name T585
Test name
Test status
Simulation time 526150661 ps
CPU time 40.61 seconds
Started May 21 03:06:24 PM PDT 24
Finished May 21 03:07:06 PM PDT 24
Peak memory 256200 kb
Host smart-7c0fc754-fe75-4343-8ab7-e008fca2c01a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317508149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.317508149
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3174242972
Short name T176
Test name
Test status
Simulation time 122223455774 ps
CPU time 2610.07 seconds
Started May 21 03:06:25 PM PDT 24
Finished May 21 03:49:56 PM PDT 24
Peak memory 322008 kb
Host smart-0ceff9f2-5449-4a42-8af1-7ed1e6ec95e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174242972 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3174242972
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3151821735
Short name T584
Test name
Test status
Simulation time 30202861146 ps
CPU time 1811.78 seconds
Started May 21 03:06:32 PM PDT 24
Finished May 21 03:36:46 PM PDT 24
Peak memory 283128 kb
Host smart-2608e8b0-7d5c-45e3-aa63-212f76977461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151821735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3151821735
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2525711435
Short name T36
Test name
Test status
Simulation time 10943730522 ps
CPU time 136.09 seconds
Started May 21 03:06:31 PM PDT 24
Finished May 21 03:08:48 PM PDT 24
Peak memory 256972 kb
Host smart-cfdcf7c5-a5b3-43ae-b6c9-8c79604b2f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
11435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2525711435
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.642799770
Short name T455
Test name
Test status
Simulation time 406670348 ps
CPU time 29.18 seconds
Started May 21 03:06:26 PM PDT 24
Finished May 21 03:06:55 PM PDT 24
Peak memory 255564 kb
Host smart-c6c8535a-f484-4fdc-807d-c96ade438b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64279
9770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.642799770
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.333199052
Short name T324
Test name
Test status
Simulation time 11230343657 ps
CPU time 992.44 seconds
Started May 21 03:06:30 PM PDT 24
Finished May 21 03:23:03 PM PDT 24
Peak memory 267660 kb
Host smart-b4106a4e-f060-47ea-bf33-715fba44af76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333199052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.333199052
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3621644495
Short name T434
Test name
Test status
Simulation time 179501159621 ps
CPU time 2480.93 seconds
Started May 21 03:06:33 PM PDT 24
Finished May 21 03:47:56 PM PDT 24
Peak memory 281608 kb
Host smart-b6fbfd19-2d98-4a1c-8836-1e6005fff937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621644495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3621644495
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.728152880
Short name T314
Test name
Test status
Simulation time 6293563824 ps
CPU time 223.34 seconds
Started May 21 03:06:33 PM PDT 24
Finished May 21 03:10:18 PM PDT 24
Peak memory 254900 kb
Host smart-03bf8603-d180-4950-bd84-3f99a8a8c6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728152880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.728152880
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1196999793
Short name T357
Test name
Test status
Simulation time 1005372594 ps
CPU time 52.72 seconds
Started May 21 03:06:26 PM PDT 24
Finished May 21 03:07:20 PM PDT 24
Peak memory 248752 kb
Host smart-d07d33d8-e657-4191-81e7-cd5b1e10f5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11969
99793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1196999793
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3353586261
Short name T549
Test name
Test status
Simulation time 474582735 ps
CPU time 36.59 seconds
Started May 21 03:06:26 PM PDT 24
Finished May 21 03:07:04 PM PDT 24
Peak memory 248880 kb
Host smart-7a63b1c7-d918-4916-885e-87cac4343a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
86261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3353586261
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2502249509
Short name T361
Test name
Test status
Simulation time 1160175703 ps
CPU time 58.15 seconds
Started May 21 03:06:24 PM PDT 24
Finished May 21 03:07:23 PM PDT 24
Peak memory 248748 kb
Host smart-949c6cd4-38fa-490c-889f-88be39eae83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25022
49509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2502249509
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.966793948
Short name T110
Test name
Test status
Simulation time 13881879334 ps
CPU time 1327.25 seconds
Started May 21 03:06:32 PM PDT 24
Finished May 21 03:28:41 PM PDT 24
Peak memory 289488 kb
Host smart-93afca22-3bcb-4674-aea4-02804a507ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966793948 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.966793948
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.675515461
Short name T79
Test name
Test status
Simulation time 30603019375 ps
CPU time 1362.89 seconds
Started May 21 03:06:42 PM PDT 24
Finished May 21 03:29:26 PM PDT 24
Peak memory 281660 kb
Host smart-49db59e6-93c2-41e3-9fa8-94c315c5e1d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675515461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.675515461
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3585123721
Short name T95
Test name
Test status
Simulation time 38802379731 ps
CPU time 170.14 seconds
Started May 21 03:06:44 PM PDT 24
Finished May 21 03:09:35 PM PDT 24
Peak memory 256952 kb
Host smart-a0cc2e10-eb33-44be-a629-81d63ee18961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35851
23721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3585123721
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2076421521
Short name T472
Test name
Test status
Simulation time 4279337276 ps
CPU time 26.59 seconds
Started May 21 03:06:40 PM PDT 24
Finished May 21 03:07:08 PM PDT 24
Peak memory 255496 kb
Host smart-27ecd4c4-e51d-4839-b981-1cac9366a7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20764
21521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2076421521
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4284886553
Short name T211
Test name
Test status
Simulation time 42528476164 ps
CPU time 1112.32 seconds
Started May 21 03:06:45 PM PDT 24
Finished May 21 03:25:19 PM PDT 24
Peak memory 289232 kb
Host smart-43e47766-4e79-4336-bfe8-b8ee29b2d5da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284886553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4284886553
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3514314379
Short name T293
Test name
Test status
Simulation time 5478344930 ps
CPU time 211.25 seconds
Started May 21 03:06:43 PM PDT 24
Finished May 21 03:10:14 PM PDT 24
Peak memory 248220 kb
Host smart-96792c10-9c57-4e6e-99c7-19995fee460c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514314379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3514314379
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.45416180
Short name T578
Test name
Test status
Simulation time 776010390 ps
CPU time 23.8 seconds
Started May 21 03:06:31 PM PDT 24
Finished May 21 03:06:57 PM PDT 24
Peak memory 256068 kb
Host smart-86189f33-b5a9-44bd-bdcd-2003cc45e838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45416
180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.45416180
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2803931134
Short name T681
Test name
Test status
Simulation time 179538687 ps
CPU time 12.68 seconds
Started May 21 03:06:31 PM PDT 24
Finished May 21 03:06:46 PM PDT 24
Peak memory 252756 kb
Host smart-7761744a-44c9-41c7-a775-6742f4ea3b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
31134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2803931134
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.229680957
Short name T20
Test name
Test status
Simulation time 916467665 ps
CPU time 29.86 seconds
Started May 21 03:06:32 PM PDT 24
Finished May 21 03:07:04 PM PDT 24
Peak memory 256100 kb
Host smart-e0d30aae-d72b-43c9-b032-b76eabc37a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22968
0957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.229680957
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1478457901
Short name T56
Test name
Test status
Simulation time 42792783582 ps
CPU time 2836.52 seconds
Started May 21 03:06:43 PM PDT 24
Finished May 21 03:54:01 PM PDT 24
Peak memory 288764 kb
Host smart-91803e53-dcfe-4a09-b611-f228b590d402
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478457901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1478457901
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3784127477
Short name T557
Test name
Test status
Simulation time 79058030006 ps
CPU time 3850.4 seconds
Started May 21 03:06:41 PM PDT 24
Finished May 21 04:10:53 PM PDT 24
Peak memory 298136 kb
Host smart-9d21be97-f2a6-4664-a684-a21a0b92b596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784127477 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3784127477
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.632402296
Short name T429
Test name
Test status
Simulation time 30184938805 ps
CPU time 1274.06 seconds
Started May 21 03:06:46 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 265420 kb
Host smart-e0730640-50a8-4718-b403-e9f4b309c8de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632402296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.632402296
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4244072051
Short name T379
Test name
Test status
Simulation time 11470890522 ps
CPU time 198.93 seconds
Started May 21 03:06:45 PM PDT 24
Finished May 21 03:10:05 PM PDT 24
Peak memory 256928 kb
Host smart-a34b1d00-4f53-4687-b023-31325e64fdbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42440
72051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4244072051
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2754458767
Short name T369
Test name
Test status
Simulation time 1023338022 ps
CPU time 28.63 seconds
Started May 21 03:06:44 PM PDT 24
Finished May 21 03:07:14 PM PDT 24
Peak memory 255836 kb
Host smart-943623f3-6e58-4a40-a238-4245bb3e2a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27544
58767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2754458767
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4161680166
Short name T326
Test name
Test status
Simulation time 20871070082 ps
CPU time 1695.77 seconds
Started May 21 03:06:49 PM PDT 24
Finished May 21 03:35:06 PM PDT 24
Peak memory 289760 kb
Host smart-2a5ccb66-d488-4a40-b004-d4e25da492ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161680166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4161680166
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.634242826
Short name T541
Test name
Test status
Simulation time 10370439426 ps
CPU time 811.82 seconds
Started May 21 03:06:49 PM PDT 24
Finished May 21 03:20:22 PM PDT 24
Peak memory 266284 kb
Host smart-0dc96d4c-5c04-410b-be7f-f7c11f6943b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634242826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.634242826
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.305127174
Short name T313
Test name
Test status
Simulation time 74279971708 ps
CPU time 533.35 seconds
Started May 21 03:06:43 PM PDT 24
Finished May 21 03:15:37 PM PDT 24
Peak memory 248224 kb
Host smart-dd12ff2c-bf6c-4bb2-9dbf-cff62049266a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305127174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.305127174
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1383490808
Short name T431
Test name
Test status
Simulation time 102487490 ps
CPU time 4.12 seconds
Started May 21 03:06:45 PM PDT 24
Finished May 21 03:06:50 PM PDT 24
Peak memory 248776 kb
Host smart-2f093d2b-3c1b-46df-be29-f0a97b72b29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834
90808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1383490808
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2850594469
Short name T486
Test name
Test status
Simulation time 357285318 ps
CPU time 21.02 seconds
Started May 21 03:06:45 PM PDT 24
Finished May 21 03:07:07 PM PDT 24
Peak memory 248748 kb
Host smart-96fb910c-be13-4ff7-bed0-74220d7cd8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28505
94469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2850594469
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1371458607
Short name T245
Test name
Test status
Simulation time 1064427843 ps
CPU time 53.94 seconds
Started May 21 03:06:44 PM PDT 24
Finished May 21 03:07:39 PM PDT 24
Peak memory 255636 kb
Host smart-846d848a-b341-439e-ad12-9b41d8535615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
58607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1371458607
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1888033221
Short name T568
Test name
Test status
Simulation time 3086919357 ps
CPU time 25.64 seconds
Started May 21 03:06:42 PM PDT 24
Finished May 21 03:07:08 PM PDT 24
Peak memory 248808 kb
Host smart-a3d51100-5bb6-49e3-985c-75df57ac69b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
33221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1888033221
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.832412710
Short name T595
Test name
Test status
Simulation time 11599499340 ps
CPU time 1071.65 seconds
Started May 21 03:06:47 PM PDT 24
Finished May 21 03:24:40 PM PDT 24
Peak memory 270648 kb
Host smart-642d4d0e-0ffb-4e44-a09d-c51334220ce2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832412710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.832412710
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1378093664
Short name T446
Test name
Test status
Simulation time 7063276383 ps
CPU time 762.87 seconds
Started May 21 03:06:54 PM PDT 24
Finished May 21 03:19:38 PM PDT 24
Peak memory 267348 kb
Host smart-e80551d8-74e0-47ab-b051-bf769d5f00e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378093664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1378093664
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3508870950
Short name T401
Test name
Test status
Simulation time 28313563355 ps
CPU time 165.42 seconds
Started May 21 03:06:54 PM PDT 24
Finished May 21 03:09:40 PM PDT 24
Peak memory 250892 kb
Host smart-4f162f4c-5a06-406a-b476-ab4df9cbac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
70950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3508870950
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2707943280
Short name T712
Test name
Test status
Simulation time 222423369 ps
CPU time 21.49 seconds
Started May 21 03:06:54 PM PDT 24
Finished May 21 03:07:16 PM PDT 24
Peak memory 255944 kb
Host smart-2b101ab5-6d19-4aa7-8f56-ecaef98e0214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
43280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2707943280
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2047323432
Short name T441
Test name
Test status
Simulation time 23184098227 ps
CPU time 1261.67 seconds
Started May 21 03:06:53 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 286304 kb
Host smart-ea9bdf00-30e6-47d6-b0e8-f504258fa8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047323432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2047323432
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2142276516
Short name T277
Test name
Test status
Simulation time 194704637221 ps
CPU time 2729.24 seconds
Started May 21 03:06:56 PM PDT 24
Finished May 21 03:52:26 PM PDT 24
Peak memory 289264 kb
Host smart-9877600c-0d40-4404-8503-d6f8ee77a397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142276516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2142276516
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.980485020
Short name T567
Test name
Test status
Simulation time 23278239100 ps
CPU time 275.86 seconds
Started May 21 03:06:56 PM PDT 24
Finished May 21 03:11:33 PM PDT 24
Peak memory 248176 kb
Host smart-05b9d8b9-b215-4cdf-b521-a3939fa77253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980485020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.980485020
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2761053048
Short name T618
Test name
Test status
Simulation time 5486357585 ps
CPU time 51.22 seconds
Started May 21 03:06:56 PM PDT 24
Finished May 21 03:07:48 PM PDT 24
Peak memory 256304 kb
Host smart-743f2a68-5f28-473c-9719-19d240daf9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
53048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2761053048
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2897172249
Short name T603
Test name
Test status
Simulation time 1827354304 ps
CPU time 31.26 seconds
Started May 21 03:06:53 PM PDT 24
Finished May 21 03:07:25 PM PDT 24
Peak memory 255536 kb
Host smart-dc59cbfd-6be4-433e-a3ba-9df8e8d7d9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28971
72249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2897172249
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.785817559
Short name T262
Test name
Test status
Simulation time 788706349 ps
CPU time 29.43 seconds
Started May 21 03:06:54 PM PDT 24
Finished May 21 03:07:24 PM PDT 24
Peak memory 247788 kb
Host smart-75933caf-0a10-4152-8051-6ecf14249c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78581
7559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.785817559
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3787006086
Short name T218
Test name
Test status
Simulation time 44479541 ps
CPU time 4.56 seconds
Started May 21 03:06:47 PM PDT 24
Finished May 21 03:06:53 PM PDT 24
Peak memory 248768 kb
Host smart-37960f94-17c1-4952-b39c-a9c1e91aedef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37870
06086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3787006086
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1725154011
Short name T678
Test name
Test status
Simulation time 25210904655 ps
CPU time 88.33 seconds
Started May 21 03:07:02 PM PDT 24
Finished May 21 03:08:31 PM PDT 24
Peak memory 256384 kb
Host smart-ae184e51-66d9-43e6-846f-18ea7b40d784
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725154011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1725154011
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.195612303
Short name T224
Test name
Test status
Simulation time 53757852764 ps
CPU time 5345.81 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 04:36:08 PM PDT 24
Peak memory 355536 kb
Host smart-16eb62f9-c55b-4852-846f-1fbdc1223e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195612303 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.195612303
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1252444759
Short name T438
Test name
Test status
Simulation time 54633189875 ps
CPU time 1846.71 seconds
Started May 21 03:07:00 PM PDT 24
Finished May 21 03:37:48 PM PDT 24
Peak memory 289092 kb
Host smart-a83515a1-fa8b-4b87-96b6-4507c835d627
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252444759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1252444759
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.27668273
Short name T499
Test name
Test status
Simulation time 32644479220 ps
CPU time 158.02 seconds
Started May 21 03:07:00 PM PDT 24
Finished May 21 03:09:38 PM PDT 24
Peak memory 257004 kb
Host smart-9af91d02-8a75-42a9-b046-4a23989f9557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.27668273
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1755809437
Short name T388
Test name
Test status
Simulation time 3193343224 ps
CPU time 50.14 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 03:07:52 PM PDT 24
Peak memory 256204 kb
Host smart-dce98d30-0934-4d74-a547-7bc697a5e50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17558
09437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1755809437
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4269632462
Short name T665
Test name
Test status
Simulation time 44023849729 ps
CPU time 1474.18 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 03:31:37 PM PDT 24
Peak memory 281556 kb
Host smart-90e9378a-303d-46ea-a409-d75d1723133b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269632462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4269632462
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.224049866
Short name T220
Test name
Test status
Simulation time 81267622809 ps
CPU time 2732.75 seconds
Started May 21 03:07:07 PM PDT 24
Finished May 21 03:52:41 PM PDT 24
Peak memory 281160 kb
Host smart-87ab5214-b442-4c36-ac36-58b4ed97afc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224049866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.224049866
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1994793303
Short name T600
Test name
Test status
Simulation time 4442718859 ps
CPU time 170.34 seconds
Started May 21 03:07:02 PM PDT 24
Finished May 21 03:09:53 PM PDT 24
Peak memory 248108 kb
Host smart-77cf45ed-bff8-4f75-8d09-5e058bc39434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994793303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1994793303
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.497254134
Short name T506
Test name
Test status
Simulation time 3675927541 ps
CPU time 51.77 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 03:07:54 PM PDT 24
Peak memory 248816 kb
Host smart-75a37c3d-451d-4486-9de2-3a831a9fd79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49725
4134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.497254134
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3962445444
Short name T444
Test name
Test status
Simulation time 122477139 ps
CPU time 9.57 seconds
Started May 21 03:07:02 PM PDT 24
Finished May 21 03:07:12 PM PDT 24
Peak memory 253044 kb
Host smart-b6757606-6c96-42b9-b7c2-461c5a5c4b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39624
45444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3962445444
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3107414581
Short name T479
Test name
Test status
Simulation time 385611186 ps
CPU time 12.8 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 03:07:15 PM PDT 24
Peak memory 255660 kb
Host smart-21701f73-a20b-4521-9000-79bd54742dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31074
14581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3107414581
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.702426762
Short name T65
Test name
Test status
Simulation time 216394701 ps
CPU time 7.85 seconds
Started May 21 03:07:01 PM PDT 24
Finished May 21 03:07:09 PM PDT 24
Peak memory 254672 kb
Host smart-ca53432b-ea55-4079-9725-7d273012bc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70242
6762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.702426762
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.899649038
Short name T531
Test name
Test status
Simulation time 19017992371 ps
CPU time 810.81 seconds
Started May 21 03:07:08 PM PDT 24
Finished May 21 03:20:40 PM PDT 24
Peak memory 273220 kb
Host smart-8e168d8c-3fe0-41ce-ac93-6b56dc894408
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899649038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.899649038
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1789783392
Short name T599
Test name
Test status
Simulation time 101155495011 ps
CPU time 8191.84 seconds
Started May 21 03:07:10 PM PDT 24
Finished May 21 05:23:43 PM PDT 24
Peak memory 371832 kb
Host smart-92507053-b0b7-4d5d-9013-71ac2d490152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789783392 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1789783392
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.144786232
Short name T702
Test name
Test status
Simulation time 12688371604 ps
CPU time 1334.76 seconds
Started May 21 03:07:07 PM PDT 24
Finished May 21 03:29:22 PM PDT 24
Peak memory 289560 kb
Host smart-2d3ee756-b44b-428d-b05f-6e1af68b7c45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144786232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.144786232
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3308201506
Short name T688
Test name
Test status
Simulation time 13411087648 ps
CPU time 195.04 seconds
Started May 21 03:07:09 PM PDT 24
Finished May 21 03:10:25 PM PDT 24
Peak memory 250140 kb
Host smart-d4aa5eb2-846e-443b-a3be-a75f529beb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
01506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3308201506
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3994589649
Short name T649
Test name
Test status
Simulation time 2285990116 ps
CPU time 39.27 seconds
Started May 21 03:07:07 PM PDT 24
Finished May 21 03:07:47 PM PDT 24
Peak memory 248944 kb
Host smart-41d27085-1292-4001-b849-b14318747de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
89649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3994589649
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4121019062
Short name T650
Test name
Test status
Simulation time 62325020178 ps
CPU time 1268.13 seconds
Started May 21 03:07:12 PM PDT 24
Finished May 21 03:28:21 PM PDT 24
Peak memory 273044 kb
Host smart-ceccb6ff-6633-4356-9bb8-16c4fe4b0c82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121019062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4121019062
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1281994318
Short name T317
Test name
Test status
Simulation time 17631248842 ps
CPU time 400.24 seconds
Started May 21 03:07:14 PM PDT 24
Finished May 21 03:13:55 PM PDT 24
Peak memory 248200 kb
Host smart-ce827a10-35bd-421d-b1a4-9937e8a6a315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281994318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1281994318
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2597583507
Short name T416
Test name
Test status
Simulation time 673589139 ps
CPU time 8.11 seconds
Started May 21 03:07:08 PM PDT 24
Finished May 21 03:07:17 PM PDT 24
Peak memory 248764 kb
Host smart-bde26d99-ef15-46a7-b9d1-f9d1fb49e556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975
83507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2597583507
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2483691822
Short name T415
Test name
Test status
Simulation time 1724520000 ps
CPU time 31.89 seconds
Started May 21 03:07:10 PM PDT 24
Finished May 21 03:07:42 PM PDT 24
Peak memory 247672 kb
Host smart-4830a683-7fc5-433d-9336-9b699ac8b7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24836
91822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2483691822
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.997521534
Short name T108
Test name
Test status
Simulation time 34375736 ps
CPU time 4.8 seconds
Started May 21 03:07:09 PM PDT 24
Finished May 21 03:07:14 PM PDT 24
Peak memory 239424 kb
Host smart-cad0d661-4656-4adf-817f-0a1680c75802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99752
1534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.997521534
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3140723784
Short name T377
Test name
Test status
Simulation time 1608001324 ps
CPU time 25.09 seconds
Started May 21 03:07:07 PM PDT 24
Finished May 21 03:07:33 PM PDT 24
Peak memory 248772 kb
Host smart-f01400fa-a137-4710-9b86-77977eec4195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407
23784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3140723784
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2096116680
Short name T543
Test name
Test status
Simulation time 76902738122 ps
CPU time 4515.55 seconds
Started May 21 03:07:13 PM PDT 24
Finished May 21 04:22:30 PM PDT 24
Peak memory 297740 kb
Host smart-7a87f93a-d048-4aee-ba67-9e46b44efac3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096116680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2096116680
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1023632739
Short name T177
Test name
Test status
Simulation time 83054320335 ps
CPU time 1787.98 seconds
Started May 21 03:07:13 PM PDT 24
Finished May 21 03:37:02 PM PDT 24
Peak memory 302692 kb
Host smart-0377441f-3494-4b25-927c-c80f6f25e484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023632739 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1023632739
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1547859656
Short name T41
Test name
Test status
Simulation time 8470873983 ps
CPU time 990.3 seconds
Started May 21 03:07:16 PM PDT 24
Finished May 21 03:23:47 PM PDT 24
Peak memory 273336 kb
Host smart-b2363fd8-c002-437e-bbd5-e51dce8caf4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547859656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1547859656
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3807975710
Short name T496
Test name
Test status
Simulation time 17299115721 ps
CPU time 247.82 seconds
Started May 21 03:07:18 PM PDT 24
Finished May 21 03:11:26 PM PDT 24
Peak memory 250808 kb
Host smart-3852b987-9761-4c0c-a5d9-ec4625eec572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38079
75710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3807975710
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2384093687
Short name T562
Test name
Test status
Simulation time 321635878 ps
CPU time 8.24 seconds
Started May 21 03:07:14 PM PDT 24
Finished May 21 03:07:23 PM PDT 24
Peak memory 253128 kb
Host smart-52c90879-c11d-48f4-a961-e04a69dfab24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23840
93687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2384093687
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.52531755
Short name T335
Test name
Test status
Simulation time 71276525950 ps
CPU time 1334.32 seconds
Started May 21 03:07:19 PM PDT 24
Finished May 21 03:29:35 PM PDT 24
Peak memory 267276 kb
Host smart-b2ff1a87-bdf9-4886-8f81-e47182e2d86e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52531755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.52531755
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4248901604
Short name T612
Test name
Test status
Simulation time 50582784116 ps
CPU time 2939.58 seconds
Started May 21 03:07:28 PM PDT 24
Finished May 21 03:56:29 PM PDT 24
Peak memory 287728 kb
Host smart-38e9356f-451d-49ee-beb9-56a2706117d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248901604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4248901604
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3690680293
Short name T97
Test name
Test status
Simulation time 117923918 ps
CPU time 15.51 seconds
Started May 21 03:07:13 PM PDT 24
Finished May 21 03:07:29 PM PDT 24
Peak memory 248776 kb
Host smart-9d13265e-b282-4e46-874f-0e71a35bc4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36906
80293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3690680293
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3233687015
Short name T66
Test name
Test status
Simulation time 1780936182 ps
CPU time 28.3 seconds
Started May 21 03:07:13 PM PDT 24
Finished May 21 03:07:43 PM PDT 24
Peak memory 248804 kb
Host smart-9576799b-576b-480e-bb76-09c9eef160d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32336
87015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3233687015
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2384519563
Short name T380
Test name
Test status
Simulation time 244800287 ps
CPU time 28.11 seconds
Started May 21 03:07:18 PM PDT 24
Finished May 21 03:07:47 PM PDT 24
Peak memory 248780 kb
Host smart-d0e7dd25-2239-4d0a-99f5-c6306b5e4829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
19563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2384519563
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.567637110
Short name T493
Test name
Test status
Simulation time 749395861 ps
CPU time 36.62 seconds
Started May 21 03:07:14 PM PDT 24
Finished May 21 03:07:52 PM PDT 24
Peak memory 256964 kb
Host smart-04700d34-4df0-48d0-9316-eaf5250d6024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56763
7110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.567637110
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1526000686
Short name T98
Test name
Test status
Simulation time 7413549472 ps
CPU time 645.06 seconds
Started May 21 03:07:26 PM PDT 24
Finished May 21 03:18:12 PM PDT 24
Peak memory 268616 kb
Host smart-77a054fd-7ee8-4cad-87ea-22a5920ef5cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526000686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1526000686
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.841924158
Short name T540
Test name
Test status
Simulation time 35672528172 ps
CPU time 1939.92 seconds
Started May 21 03:07:27 PM PDT 24
Finished May 21 03:39:48 PM PDT 24
Peak memory 288680 kb
Host smart-9f84f4fb-6e74-40ef-93de-4d7fb53d052c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841924158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.841924158
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3180327724
Short name T351
Test name
Test status
Simulation time 12392865837 ps
CPU time 302.51 seconds
Started May 21 03:07:31 PM PDT 24
Finished May 21 03:12:34 PM PDT 24
Peak memory 256976 kb
Host smart-026e9e3f-4f1d-457f-8d40-036553968c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31803
27724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3180327724
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1883500526
Short name T83
Test name
Test status
Simulation time 1127189575 ps
CPU time 66.1 seconds
Started May 21 03:07:29 PM PDT 24
Finished May 21 03:08:36 PM PDT 24
Peak memory 248784 kb
Host smart-623c9391-a836-462d-872f-6b13235b4433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
00526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1883500526
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1088440091
Short name T448
Test name
Test status
Simulation time 182878587483 ps
CPU time 2922.97 seconds
Started May 21 03:07:30 PM PDT 24
Finished May 21 03:56:14 PM PDT 24
Peak memory 281600 kb
Host smart-9dd0d9f8-21d0-438a-b893-7d8dd8de3e1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088440091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1088440091
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1641242349
Short name T316
Test name
Test status
Simulation time 23620062611 ps
CPU time 517.24 seconds
Started May 21 03:07:31 PM PDT 24
Finished May 21 03:16:09 PM PDT 24
Peak memory 248056 kb
Host smart-f41e7b36-9ff3-47cb-91a5-88360e08eeb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641242349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1641242349
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2496281327
Short name T673
Test name
Test status
Simulation time 259088218 ps
CPU time 23.68 seconds
Started May 21 03:07:27 PM PDT 24
Finished May 21 03:07:51 PM PDT 24
Peak memory 255320 kb
Host smart-58f59aaf-1f3f-4a0f-9b84-0f3bc6119627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
81327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2496281327
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3778992697
Short name T60
Test name
Test status
Simulation time 730344269 ps
CPU time 19.27 seconds
Started May 21 03:07:31 PM PDT 24
Finished May 21 03:07:51 PM PDT 24
Peak memory 255176 kb
Host smart-59cfc2ba-e04a-41b1-b243-15ed4f5ad451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37789
92697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3778992697
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2783877400
Short name T391
Test name
Test status
Simulation time 442546720 ps
CPU time 13.66 seconds
Started May 21 03:07:28 PM PDT 24
Finished May 21 03:07:43 PM PDT 24
Peak memory 248740 kb
Host smart-cbc740ec-7968-422c-addc-1cc604416884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27838
77400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2783877400
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2230407339
Short name T272
Test name
Test status
Simulation time 49901952859 ps
CPU time 2006.47 seconds
Started May 21 03:07:32 PM PDT 24
Finished May 21 03:40:59 PM PDT 24
Peak memory 281624 kb
Host smart-1d9faa0c-7e75-493c-98cb-8af9452d8725
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230407339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2230407339
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.750207416
Short name T620
Test name
Test status
Simulation time 3765864891 ps
CPU time 480.38 seconds
Started May 21 03:07:32 PM PDT 24
Finished May 21 03:15:34 PM PDT 24
Peak memory 270008 kb
Host smart-ce07fa38-1d77-47a3-9722-4eb349d547df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750207416 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.750207416
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1165452902
Short name T564
Test name
Test status
Simulation time 8824320167 ps
CPU time 747.04 seconds
Started May 21 03:07:34 PM PDT 24
Finished May 21 03:20:02 PM PDT 24
Peak memory 267276 kb
Host smart-48c16656-c548-457a-8536-8176de4f4a46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165452902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1165452902
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1942840315
Short name T617
Test name
Test status
Simulation time 16909316798 ps
CPU time 243.86 seconds
Started May 21 03:07:35 PM PDT 24
Finished May 21 03:11:40 PM PDT 24
Peak memory 250000 kb
Host smart-8fbf4e50-37c2-464b-ab0f-5e2293af70a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
40315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1942840315
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.927583426
Short name T249
Test name
Test status
Simulation time 356112353 ps
CPU time 26.81 seconds
Started May 21 03:07:36 PM PDT 24
Finished May 21 03:08:04 PM PDT 24
Peak memory 248804 kb
Host smart-c654f502-0327-4b71-ba3a-e94f1d7669f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92758
3426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.927583426
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.309059621
Short name T602
Test name
Test status
Simulation time 22527797176 ps
CPU time 1297.09 seconds
Started May 21 03:07:35 PM PDT 24
Finished May 21 03:29:13 PM PDT 24
Peak memory 265244 kb
Host smart-fff140e2-b110-4972-a340-c0c2a3afa087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309059621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.309059621
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3604778549
Short name T494
Test name
Test status
Simulation time 384555041207 ps
CPU time 2285.71 seconds
Started May 21 03:07:42 PM PDT 24
Finished May 21 03:45:49 PM PDT 24
Peak memory 281672 kb
Host smart-cd6a9ae2-dc6e-46d3-af9f-e66fe356c32d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604778549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3604778549
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4025278335
Short name T445
Test name
Test status
Simulation time 25708166797 ps
CPU time 307.8 seconds
Started May 21 03:07:36 PM PDT 24
Finished May 21 03:12:45 PM PDT 24
Peak memory 254880 kb
Host smart-cfde4007-c592-48c3-945b-516e4572ccc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025278335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4025278335
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2417380826
Short name T353
Test name
Test status
Simulation time 833185215 ps
CPU time 50.65 seconds
Started May 21 03:07:30 PM PDT 24
Finished May 21 03:08:22 PM PDT 24
Peak memory 248812 kb
Host smart-1e662d79-bdf6-4f39-95b9-b433fd48159b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
80826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2417380826
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.98473241
Short name T510
Test name
Test status
Simulation time 1064028054 ps
CPU time 56.47 seconds
Started May 21 03:07:36 PM PDT 24
Finished May 21 03:08:34 PM PDT 24
Peak memory 255884 kb
Host smart-6cfa0235-1c26-4a18-95e2-5bdf0f9f2dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98473
241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.98473241
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.990231024
Short name T443
Test name
Test status
Simulation time 323414528 ps
CPU time 12.66 seconds
Started May 21 03:07:36 PM PDT 24
Finished May 21 03:07:49 PM PDT 24
Peak memory 252888 kb
Host smart-f4a0d7bd-6bec-4a08-8d3e-6fab5e89057f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99023
1024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.990231024
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.80159331
Short name T707
Test name
Test status
Simulation time 1086656495 ps
CPU time 24.06 seconds
Started May 21 03:07:31 PM PDT 24
Finished May 21 03:07:56 PM PDT 24
Peak memory 248768 kb
Host smart-723b3f34-1a7e-4d65-921d-9f07183e2a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80159
331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.80159331
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.786403908
Short name T49
Test name
Test status
Simulation time 162694285888 ps
CPU time 2745.72 seconds
Started May 21 03:07:40 PM PDT 24
Finished May 21 03:53:27 PM PDT 24
Peak memory 289408 kb
Host smart-d6533391-1b91-40d9-8fed-cb335d7f8106
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786403908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.786403908
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3138714037
Short name T37
Test name
Test status
Simulation time 24226616 ps
CPU time 2.41 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:04:45 PM PDT 24
Peak memory 248900 kb
Host smart-5187a56c-91b2-46e2-ada7-88c138fdeb2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3138714037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3138714037
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2629270313
Short name T285
Test name
Test status
Simulation time 6518362384 ps
CPU time 692.72 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:16:18 PM PDT 24
Peak memory 273296 kb
Host smart-1641058d-d66b-4cf9-b98b-ed4bd187b739
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629270313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2629270313
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2819420052
Short name T456
Test name
Test status
Simulation time 853464010 ps
CPU time 36.62 seconds
Started May 21 03:04:41 PM PDT 24
Finished May 21 03:05:20 PM PDT 24
Peak memory 248788 kb
Host smart-69b97b5f-8af7-49e3-b3d1-e6d32e5126bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2819420052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2819420052
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1157964442
Short name T39
Test name
Test status
Simulation time 295291745 ps
CPU time 24.35 seconds
Started May 21 03:04:41 PM PDT 24
Finished May 21 03:05:08 PM PDT 24
Peak memory 256516 kb
Host smart-68c3064d-33ce-434a-91b6-e0d95746fdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
64442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1157964442
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.43493711
Short name T523
Test name
Test status
Simulation time 126214733 ps
CPU time 8.87 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:04:54 PM PDT 24
Peak memory 240916 kb
Host smart-097229dc-f9b0-46e2-be2d-39d5542c9bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43493
711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.43493711
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3901903567
Short name T704
Test name
Test status
Simulation time 57111783729 ps
CPU time 1792.06 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:34:37 PM PDT 24
Peak memory 280908 kb
Host smart-2b32fe4d-b30a-4f16-a052-dbf20f7721be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901903567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3901903567
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1615018796
Short name T664
Test name
Test status
Simulation time 49257409640 ps
CPU time 520.21 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:13:23 PM PDT 24
Peak memory 247108 kb
Host smart-808ddba0-369c-4c98-afd5-d8011147a041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615018796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1615018796
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.852795699
Short name T18
Test name
Test status
Simulation time 1050073030 ps
CPU time 22.52 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:05:05 PM PDT 24
Peak memory 248816 kb
Host smart-45aa3ce1-0224-4d40-95ef-86802459fcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85279
5699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.852795699
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.391403480
Short name T684
Test name
Test status
Simulation time 244052799 ps
CPU time 27.09 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:05:14 PM PDT 24
Peak memory 248448 kb
Host smart-d836cd56-fba8-43a0-9fb9-f87210facddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39140
3480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.391403480
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.217622232
Short name T10
Test name
Test status
Simulation time 1250885177 ps
CPU time 55.2 seconds
Started May 21 03:04:41 PM PDT 24
Finished May 21 03:05:39 PM PDT 24
Peak memory 265588 kb
Host smart-7a95e582-54ca-4416-810e-eb26174a6bca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=217622232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.217622232
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3307848797
Short name T38
Test name
Test status
Simulation time 299066311 ps
CPU time 10.86 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:04:55 PM PDT 24
Peak memory 247452 kb
Host smart-ac012d07-09ed-4cf0-a171-eaa5e2d49f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078
48797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3307848797
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1408207213
Short name T570
Test name
Test status
Simulation time 80836279 ps
CPU time 3.78 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:04:46 PM PDT 24
Peak memory 240584 kb
Host smart-2cad2eb4-664e-493e-89ab-d36e44305cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14082
07213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1408207213
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4259885205
Short name T54
Test name
Test status
Simulation time 71677464148 ps
CPU time 2064.9 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:39:11 PM PDT 24
Peak memory 273432 kb
Host smart-5206bb54-8fa6-4cb2-8ffc-3a75da8d68ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259885205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4259885205
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4105519223
Short name T103
Test name
Test status
Simulation time 51458088437 ps
CPU time 2465 seconds
Started May 21 03:07:39 PM PDT 24
Finished May 21 03:48:45 PM PDT 24
Peak memory 288696 kb
Host smart-0ee34540-0e9e-4530-bbd2-af11cde29503
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105519223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4105519223
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1643264617
Short name T661
Test name
Test status
Simulation time 1910797530 ps
CPU time 58.08 seconds
Started May 21 03:07:44 PM PDT 24
Finished May 21 03:08:43 PM PDT 24
Peak memory 254968 kb
Host smart-2b34b779-4c16-4bd8-9dfa-ec2b3721c924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16432
64617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1643264617
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3910861308
Short name T359
Test name
Test status
Simulation time 14357584201 ps
CPU time 1370.27 seconds
Started May 21 03:07:48 PM PDT 24
Finished May 21 03:30:39 PM PDT 24
Peak memory 281620 kb
Host smart-f611f517-e6f3-4b92-afc5-480b29ce1201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910861308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3910861308
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3342106938
Short name T309
Test name
Test status
Simulation time 13862516355 ps
CPU time 570.8 seconds
Started May 21 03:07:46 PM PDT 24
Finished May 21 03:17:17 PM PDT 24
Peak memory 247384 kb
Host smart-40ab27f3-a656-4973-9d22-b58ea9c6856a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342106938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3342106938
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3755967975
Short name T638
Test name
Test status
Simulation time 9617496997 ps
CPU time 56.26 seconds
Started May 21 03:07:40 PM PDT 24
Finished May 21 03:08:37 PM PDT 24
Peak memory 256288 kb
Host smart-456523bd-dcad-40d1-b666-42068761fdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
67975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3755967975
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1246669323
Short name T621
Test name
Test status
Simulation time 1707728054 ps
CPU time 27.6 seconds
Started May 21 03:07:42 PM PDT 24
Finished May 21 03:08:10 PM PDT 24
Peak memory 249028 kb
Host smart-a675515e-a77c-4ab7-b263-325201a8ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12466
69323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1246669323
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.682368631
Short name T408
Test name
Test status
Simulation time 726529259 ps
CPU time 23.9 seconds
Started May 21 03:07:43 PM PDT 24
Finished May 21 03:08:08 PM PDT 24
Peak memory 254988 kb
Host smart-2b6aa44c-5b58-44a9-ac44-a3f0f1f3a943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68236
8631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.682368631
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2397721838
Short name T465
Test name
Test status
Simulation time 1641343060 ps
CPU time 26.77 seconds
Started May 21 03:07:41 PM PDT 24
Finished May 21 03:08:09 PM PDT 24
Peak memory 248948 kb
Host smart-233621a2-bf65-42f9-9267-6615e0f25727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23977
21838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2397721838
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3239959816
Short name T575
Test name
Test status
Simulation time 38125568983 ps
CPU time 853.97 seconds
Started May 21 03:07:49 PM PDT 24
Finished May 21 03:22:04 PM PDT 24
Peak memory 267352 kb
Host smart-19f1a269-fa4e-4156-8c78-81953693e34f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239959816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3239959816
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1875946612
Short name T706
Test name
Test status
Simulation time 17390564429 ps
CPU time 115 seconds
Started May 21 03:07:50 PM PDT 24
Finished May 21 03:09:46 PM PDT 24
Peak memory 256788 kb
Host smart-835790b4-1e33-4689-8844-0dfc9be1cc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
46612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1875946612
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1037946307
Short name T354
Test name
Test status
Simulation time 1428928593 ps
CPU time 30.98 seconds
Started May 21 03:07:46 PM PDT 24
Finished May 21 03:08:17 PM PDT 24
Peak memory 256024 kb
Host smart-e41a0184-e991-4edf-af41-cf890de4e337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10379
46307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1037946307
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3120734340
Short name T310
Test name
Test status
Simulation time 152160745379 ps
CPU time 2105.19 seconds
Started May 21 03:07:54 PM PDT 24
Finished May 21 03:43:01 PM PDT 24
Peak memory 273584 kb
Host smart-cca9e3b1-4682-4bb1-8132-eb8a1905d9e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120734340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3120734340
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2496235570
Short name T601
Test name
Test status
Simulation time 451445574663 ps
CPU time 1982.7 seconds
Started May 21 03:07:52 PM PDT 24
Finished May 21 03:40:55 PM PDT 24
Peak memory 273448 kb
Host smart-bef8e63a-4849-4bce-8203-0ad13cc994ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496235570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2496235570
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1876861054
Short name T307
Test name
Test status
Simulation time 36570880589 ps
CPU time 395.48 seconds
Started May 21 03:07:51 PM PDT 24
Finished May 21 03:14:27 PM PDT 24
Peak memory 248056 kb
Host smart-adba4ee6-409c-4584-bd77-c48cd210c2ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876861054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1876861054
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.537886231
Short name T507
Test name
Test status
Simulation time 175497283 ps
CPU time 22.1 seconds
Started May 21 03:07:48 PM PDT 24
Finished May 21 03:08:10 PM PDT 24
Peak memory 255996 kb
Host smart-af670ed7-68a5-49f7-b8f9-796f86f5e1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53788
6231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.537886231
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1046587835
Short name T382
Test name
Test status
Simulation time 1614651821 ps
CPU time 32.47 seconds
Started May 21 03:07:50 PM PDT 24
Finished May 21 03:08:23 PM PDT 24
Peak memory 248940 kb
Host smart-816a240a-2d15-4818-adc9-6a1e08bf5ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
87835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1046587835
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2525955521
Short name T604
Test name
Test status
Simulation time 963617537 ps
CPU time 16.21 seconds
Started May 21 03:07:51 PM PDT 24
Finished May 21 03:08:08 PM PDT 24
Peak memory 253864 kb
Host smart-5c6f75ca-9f35-48d8-a037-87db1bfb1ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
55521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2525955521
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3193112885
Short name T383
Test name
Test status
Simulation time 168457188 ps
CPU time 17.16 seconds
Started May 21 03:07:46 PM PDT 24
Finished May 21 03:08:04 PM PDT 24
Peak memory 248760 kb
Host smart-62df1984-5e09-4f2e-866d-0b66b60dded8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
12885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3193112885
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4144629072
Short name T458
Test name
Test status
Simulation time 7178049445 ps
CPU time 97.94 seconds
Started May 21 03:07:54 PM PDT 24
Finished May 21 03:09:33 PM PDT 24
Peak memory 250020 kb
Host smart-a2f3f9c3-f63e-474b-9c9c-229ed1501bab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144629072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4144629072
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3974927778
Short name T686
Test name
Test status
Simulation time 19765869598 ps
CPU time 1184.89 seconds
Started May 21 03:07:59 PM PDT 24
Finished May 21 03:27:45 PM PDT 24
Peak memory 265240 kb
Host smart-c741d397-9e3f-46d9-8c69-9c6d276a8966
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974927778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3974927778
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4176365308
Short name T475
Test name
Test status
Simulation time 10958543706 ps
CPU time 343.51 seconds
Started May 21 03:07:58 PM PDT 24
Finished May 21 03:13:42 PM PDT 24
Peak memory 256968 kb
Host smart-fba5c376-3b21-40c1-88d2-7f2fdb829866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41763
65308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4176365308
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.138948398
Short name T505
Test name
Test status
Simulation time 160974897 ps
CPU time 4.91 seconds
Started May 21 03:07:57 PM PDT 24
Finished May 21 03:08:02 PM PDT 24
Peak memory 250864 kb
Host smart-28a198d2-2ba2-4e1d-a5fe-a0108710c4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894
8398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.138948398
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3187767307
Short name T576
Test name
Test status
Simulation time 348086162189 ps
CPU time 3170.7 seconds
Started May 21 03:07:59 PM PDT 24
Finished May 21 04:00:51 PM PDT 24
Peak memory 289204 kb
Host smart-cade9b51-e569-4074-a3a7-132110ef0481
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187767307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3187767307
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2031852325
Short name T711
Test name
Test status
Simulation time 70157796087 ps
CPU time 1656.1 seconds
Started May 21 03:07:59 PM PDT 24
Finished May 21 03:35:37 PM PDT 24
Peak memory 273412 kb
Host smart-4b8a6780-6c04-4161-80ad-9522be8efd18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031852325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2031852325
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.954799021
Short name T504
Test name
Test status
Simulation time 5121908926 ps
CPU time 33.14 seconds
Started May 21 03:07:57 PM PDT 24
Finished May 21 03:08:30 PM PDT 24
Peak memory 256184 kb
Host smart-87c62982-33e2-445c-bd03-2e56779d67e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95479
9021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.954799021
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.243369776
Short name T460
Test name
Test status
Simulation time 832538906 ps
CPU time 15.35 seconds
Started May 21 03:08:01 PM PDT 24
Finished May 21 03:08:17 PM PDT 24
Peak memory 255608 kb
Host smart-7778a9c6-c241-4b30-81f9-a2cb39915834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
9776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.243369776
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2518608328
Short name T217
Test name
Test status
Simulation time 3017096674 ps
CPU time 47.2 seconds
Started May 21 03:07:58 PM PDT 24
Finished May 21 03:08:47 PM PDT 24
Peak memory 256184 kb
Host smart-09fe694f-9659-4503-bde2-7346af7f73e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25186
08328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2518608328
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3917330236
Short name T381
Test name
Test status
Simulation time 4928701230 ps
CPU time 58.01 seconds
Started May 21 03:07:53 PM PDT 24
Finished May 21 03:08:52 PM PDT 24
Peak memory 256272 kb
Host smart-86acd369-1dbf-444c-a61d-5ee732a827a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
30236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3917330236
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1629830612
Short name T112
Test name
Test status
Simulation time 5004332009 ps
CPU time 77.62 seconds
Started May 21 03:08:10 PM PDT 24
Finished May 21 03:09:29 PM PDT 24
Peak memory 256892 kb
Host smart-8aa02e90-d71a-4908-8d47-343bd7fbaa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
30612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1629830612
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1642631336
Short name T690
Test name
Test status
Simulation time 249558506 ps
CPU time 9.22 seconds
Started May 21 03:08:03 PM PDT 24
Finished May 21 03:08:14 PM PDT 24
Peak memory 251948 kb
Host smart-cc6f2db7-4acf-4a82-b4fc-c3c303b7e093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
31336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1642631336
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4088571126
Short name T336
Test name
Test status
Simulation time 46973717651 ps
CPU time 1576.8 seconds
Started May 21 03:08:15 PM PDT 24
Finished May 21 03:34:33 PM PDT 24
Peak memory 288996 kb
Host smart-b4e5411a-15fc-4b4e-9121-43677fd0b344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088571126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4088571126
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1977532156
Short name T375
Test name
Test status
Simulation time 10140267222 ps
CPU time 903.32 seconds
Started May 21 03:08:16 PM PDT 24
Finished May 21 03:23:20 PM PDT 24
Peak memory 273452 kb
Host smart-37211118-ff3e-4aca-9d55-d169454eb216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977532156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1977532156
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.478359045
Short name T311
Test name
Test status
Simulation time 11420568153 ps
CPU time 472.29 seconds
Started May 21 03:08:15 PM PDT 24
Finished May 21 03:16:08 PM PDT 24
Peak memory 248308 kb
Host smart-b610e87d-b645-450f-976c-7d209d84ddd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478359045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.478359045
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1708444186
Short name T368
Test name
Test status
Simulation time 922733037 ps
CPU time 54.71 seconds
Started May 21 03:08:02 PM PDT 24
Finished May 21 03:08:58 PM PDT 24
Peak memory 248956 kb
Host smart-e3bb7b48-06bc-4e79-a4c6-221ca2457a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17084
44186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1708444186
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.989426823
Short name T709
Test name
Test status
Simulation time 586419599 ps
CPU time 39.32 seconds
Started May 21 03:08:04 PM PDT 24
Finished May 21 03:08:45 PM PDT 24
Peak memory 255020 kb
Host smart-145b3cf9-59ca-412e-8247-f582235645df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98942
6823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.989426823
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3684624434
Short name T539
Test name
Test status
Simulation time 1545101415 ps
CPU time 46.28 seconds
Started May 21 03:08:09 PM PDT 24
Finished May 21 03:08:56 PM PDT 24
Peak memory 255980 kb
Host smart-1059f43e-6c72-4bb1-8e99-d9eb93e775c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
24434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3684624434
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.949637482
Short name T70
Test name
Test status
Simulation time 900549263 ps
CPU time 27.77 seconds
Started May 21 03:08:03 PM PDT 24
Finished May 21 03:08:31 PM PDT 24
Peak memory 256084 kb
Host smart-8e7cf636-902a-4c3d-b466-2fa53247550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94963
7482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.949637482
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2727871100
Short name T82
Test name
Test status
Simulation time 211107700692 ps
CPU time 2868.22 seconds
Started May 21 03:08:24 PM PDT 24
Finished May 21 03:56:14 PM PDT 24
Peak memory 281600 kb
Host smart-2f54f1d4-6bae-4194-afb7-c9a08860bf1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727871100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2727871100
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1902613871
Short name T558
Test name
Test status
Simulation time 642559903 ps
CPU time 45.36 seconds
Started May 21 03:08:20 PM PDT 24
Finished May 21 03:09:06 PM PDT 24
Peak memory 256892 kb
Host smart-fef28410-cc60-4c93-b89b-e97d6b5274e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
13871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1902613871
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2210553639
Short name T78
Test name
Test status
Simulation time 3146143335 ps
CPU time 44.19 seconds
Started May 21 03:08:25 PM PDT 24
Finished May 21 03:09:10 PM PDT 24
Peak memory 255148 kb
Host smart-e53c2b96-d5ef-42bf-a5be-0822701a92db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22105
53639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2210553639
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.75145986
Short name T662
Test name
Test status
Simulation time 17316710741 ps
CPU time 1563.65 seconds
Started May 21 03:08:25 PM PDT 24
Finished May 21 03:34:30 PM PDT 24
Peak memory 287860 kb
Host smart-6fc5d30f-444d-4240-8801-14118f964278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75145986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.75145986
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1373340981
Short name T435
Test name
Test status
Simulation time 42736946298 ps
CPU time 2462.81 seconds
Started May 21 03:08:25 PM PDT 24
Finished May 21 03:49:29 PM PDT 24
Peak memory 285396 kb
Host smart-8b73676c-1fe4-4dd9-906b-b1cbacd9817c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373340981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1373340981
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1832926360
Short name T639
Test name
Test status
Simulation time 43832789739 ps
CPU time 397.17 seconds
Started May 21 03:08:24 PM PDT 24
Finished May 21 03:15:02 PM PDT 24
Peak memory 248368 kb
Host smart-ec1defe8-67ef-4dfa-8b42-080d0142ef11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832926360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1832926360
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.578445788
Short name T71
Test name
Test status
Simulation time 221760415 ps
CPU time 14.18 seconds
Started May 21 03:08:21 PM PDT 24
Finished May 21 03:08:36 PM PDT 24
Peak memory 248804 kb
Host smart-5fb5621a-1f59-48e5-99fd-c9014d478eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57844
5788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.578445788
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1134426709
Short name T657
Test name
Test status
Simulation time 1867703580 ps
CPU time 56.47 seconds
Started May 21 03:08:20 PM PDT 24
Finished May 21 03:09:17 PM PDT 24
Peak memory 255984 kb
Host smart-93b99223-2d3c-4adf-b521-88656a704c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11344
26709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1134426709
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1831848941
Short name T703
Test name
Test status
Simulation time 1003792454 ps
CPU time 61.03 seconds
Started May 21 03:08:24 PM PDT 24
Finished May 21 03:09:27 PM PDT 24
Peak memory 255504 kb
Host smart-d2f02283-3809-4d5e-8191-6d3fdcee142a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18318
48941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1831848941
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.236455515
Short name T390
Test name
Test status
Simulation time 100926446 ps
CPU time 7 seconds
Started May 21 03:08:20 PM PDT 24
Finished May 21 03:08:27 PM PDT 24
Peak memory 248776 kb
Host smart-3b8cbb5b-c22f-4274-95ac-358622b59621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
5515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.236455515
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.966921318
Short name T264
Test name
Test status
Simulation time 219017935657 ps
CPU time 3174.34 seconds
Started May 21 03:08:26 PM PDT 24
Finished May 21 04:01:22 PM PDT 24
Peak memory 289720 kb
Host smart-9162daf5-dc84-4c8f-b592-acfe415610a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966921318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.966921318
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1440315688
Short name T228
Test name
Test status
Simulation time 24239793372 ps
CPU time 1671.22 seconds
Started May 21 03:08:41 PM PDT 24
Finished May 21 03:36:33 PM PDT 24
Peak memory 273420 kb
Host smart-c73854f0-29ca-47c4-8a29-6237e1684134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440315688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1440315688
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.179983787
Short name T581
Test name
Test status
Simulation time 36725691 ps
CPU time 3.9 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:08:49 PM PDT 24
Peak memory 239320 kb
Host smart-b8d6b41c-b620-49b5-8394-3f8b20bdc73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17998
3787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.179983787
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1544218683
Short name T528
Test name
Test status
Simulation time 89808264 ps
CPU time 7.96 seconds
Started May 21 03:08:33 PM PDT 24
Finished May 21 03:08:42 PM PDT 24
Peak memory 240928 kb
Host smart-55d01afc-3606-4cd9-ab1b-533abdfa50f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
18683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1544218683
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1218421194
Short name T338
Test name
Test status
Simulation time 21840655303 ps
CPU time 1055.09 seconds
Started May 21 03:08:43 PM PDT 24
Finished May 21 03:26:19 PM PDT 24
Peak memory 289116 kb
Host smart-d3eee0ce-6102-4532-9e89-210d485746fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218421194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1218421194
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.664598696
Short name T613
Test name
Test status
Simulation time 27201262728 ps
CPU time 1664.29 seconds
Started May 21 03:08:38 PM PDT 24
Finished May 21 03:36:23 PM PDT 24
Peak memory 273384 kb
Host smart-7ce3e00f-8151-4a4f-a9dc-c34652aa5c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664598696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.664598696
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2450584958
Short name T598
Test name
Test status
Simulation time 24081924478 ps
CPU time 274.45 seconds
Started May 21 03:08:40 PM PDT 24
Finished May 21 03:13:15 PM PDT 24
Peak memory 247152 kb
Host smart-31827c31-4fe2-4c2e-8576-16fcf3defe63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450584958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2450584958
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.89829332
Short name T615
Test name
Test status
Simulation time 1704612114 ps
CPU time 29.48 seconds
Started May 21 03:08:34 PM PDT 24
Finished May 21 03:09:05 PM PDT 24
Peak memory 248816 kb
Host smart-b3760513-5b20-40f2-87eb-3250d6d36bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89829
332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.89829332
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3076733088
Short name T430
Test name
Test status
Simulation time 2375463481 ps
CPU time 22.8 seconds
Started May 21 03:08:34 PM PDT 24
Finished May 21 03:08:58 PM PDT 24
Peak memory 248812 kb
Host smart-64cc9ddd-3f23-41ba-88bc-1719b487d9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
33088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3076733088
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2579972792
Short name T508
Test name
Test status
Simulation time 320078020 ps
CPU time 9.98 seconds
Started May 21 03:08:43 PM PDT 24
Finished May 21 03:08:53 PM PDT 24
Peak memory 247360 kb
Host smart-5954ffac-5d62-441b-a005-2976522ba847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25799
72792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2579972792
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.214866358
Short name T516
Test name
Test status
Simulation time 1237608482 ps
CPU time 40.83 seconds
Started May 21 03:08:34 PM PDT 24
Finished May 21 03:09:16 PM PDT 24
Peak memory 248744 kb
Host smart-a003f5be-c3e2-4c0d-b2aa-917cabe88092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21486
6358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.214866358
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3873095326
Short name T406
Test name
Test status
Simulation time 94417615426 ps
CPU time 2797.92 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:55:24 PM PDT 24
Peak memory 288812 kb
Host smart-2c8fe0d6-a2e1-4c60-9817-bdad7edf1a18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873095326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3873095326
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2999610669
Short name T566
Test name
Test status
Simulation time 573620683 ps
CPU time 14.96 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:09:01 PM PDT 24
Peak memory 256532 kb
Host smart-09dec9cf-4a76-4996-a277-63dd3ffe062e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
10669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2999610669
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2218509616
Short name T530
Test name
Test status
Simulation time 116913086 ps
CPU time 7.5 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:08:53 PM PDT 24
Peak memory 248864 kb
Host smart-97c95517-4788-4840-b1b3-2f04da233b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22185
09616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2218509616
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.610169404
Short name T181
Test name
Test status
Simulation time 197475836716 ps
CPU time 2202.73 seconds
Started May 21 03:08:49 PM PDT 24
Finished May 21 03:45:33 PM PDT 24
Peak memory 281652 kb
Host smart-49445306-8891-41f8-8522-47ccf4f52619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610169404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.610169404
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.504746341
Short name T481
Test name
Test status
Simulation time 43366003585 ps
CPU time 2428.46 seconds
Started May 21 03:08:53 PM PDT 24
Finished May 21 03:49:22 PM PDT 24
Peak memory 281620 kb
Host smart-12372046-8eaf-4a4a-9132-b6a48465b30b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504746341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.504746341
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1704767947
Short name T301
Test name
Test status
Simulation time 19372434981 ps
CPU time 357.05 seconds
Started May 21 03:08:50 PM PDT 24
Finished May 21 03:14:48 PM PDT 24
Peak memory 254760 kb
Host smart-31386bbc-e9e0-4815-865e-bf099f592852
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704767947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1704767947
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.161020212
Short name T537
Test name
Test status
Simulation time 176906798 ps
CPU time 4.31 seconds
Started May 21 03:08:45 PM PDT 24
Finished May 21 03:08:50 PM PDT 24
Peak memory 240688 kb
Host smart-90b11302-c549-49ce-9a22-2c2fe77f268b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
0212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.161020212
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.694482322
Short name T393
Test name
Test status
Simulation time 845770071 ps
CPU time 39.69 seconds
Started May 21 03:08:42 PM PDT 24
Finished May 21 03:09:23 PM PDT 24
Peak memory 248868 kb
Host smart-affcc516-3b94-468f-a199-dd4607f7b090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69448
2322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.694482322
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2303774827
Short name T645
Test name
Test status
Simulation time 1743109584 ps
CPU time 32.83 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:09:18 PM PDT 24
Peak memory 255536 kb
Host smart-4a45a3ea-6ccd-4df6-8615-353ce7071958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037
74827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2303774827
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1735649218
Short name T471
Test name
Test status
Simulation time 539702346 ps
CPU time 30.93 seconds
Started May 21 03:08:44 PM PDT 24
Finished May 21 03:09:17 PM PDT 24
Peak memory 256068 kb
Host smart-b8d771cd-417d-422d-bf84-23b5c06e8145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17356
49218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1735649218
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.946127494
Short name T696
Test name
Test status
Simulation time 199292620 ps
CPU time 8.68 seconds
Started May 21 03:08:59 PM PDT 24
Finished May 21 03:09:09 PM PDT 24
Peak memory 251580 kb
Host smart-3798ccff-a655-4225-bd27-dd4aa2d69840
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946127494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.946127494
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1050689416
Short name T13
Test name
Test status
Simulation time 55074693990 ps
CPU time 1391.44 seconds
Started May 21 03:09:08 PM PDT 24
Finished May 21 03:32:22 PM PDT 24
Peak memory 283760 kb
Host smart-ff7edf46-bb6a-4f3b-a300-a81ce734b664
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050689416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1050689416
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.747289663
Short name T535
Test name
Test status
Simulation time 7780233715 ps
CPU time 206.41 seconds
Started May 21 03:09:02 PM PDT 24
Finished May 21 03:12:29 PM PDT 24
Peak memory 257144 kb
Host smart-3044a0da-b687-436a-a1d6-3ba250124554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74728
9663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.747289663
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1859354694
Short name T594
Test name
Test status
Simulation time 683454335 ps
CPU time 30.66 seconds
Started May 21 03:09:01 PM PDT 24
Finished May 21 03:09:33 PM PDT 24
Peak memory 249128 kb
Host smart-23bcf896-4150-4e4a-bba4-3019217ec886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
54694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1859354694
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3640266489
Short name T234
Test name
Test status
Simulation time 59569377687 ps
CPU time 997.67 seconds
Started May 21 03:09:08 PM PDT 24
Finished May 21 03:25:48 PM PDT 24
Peak memory 271428 kb
Host smart-bbd48ebf-1f46-4694-8bb8-d68dd843123d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640266489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3640266489
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4008552974
Short name T646
Test name
Test status
Simulation time 231126522816 ps
CPU time 3037.91 seconds
Started May 21 03:09:08 PM PDT 24
Finished May 21 03:59:48 PM PDT 24
Peak memory 289136 kb
Host smart-33c50ba2-7c6c-47ce-864d-65a40b7e2b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008552974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4008552974
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1538553450
Short name T303
Test name
Test status
Simulation time 8121307214 ps
CPU time 329.26 seconds
Started May 21 03:09:07 PM PDT 24
Finished May 21 03:14:37 PM PDT 24
Peak memory 248260 kb
Host smart-8cf0b8a9-e824-4c60-8b6e-18787db5966e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538553450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1538553450
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4062856307
Short name T672
Test name
Test status
Simulation time 179208508 ps
CPU time 5.55 seconds
Started May 21 03:08:58 PM PDT 24
Finished May 21 03:09:04 PM PDT 24
Peak memory 250980 kb
Host smart-0ea55ddf-2d6a-4cd5-b78d-b5ca0937cf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
56307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4062856307
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2660394193
Short name T107
Test name
Test status
Simulation time 5749835212 ps
CPU time 43.9 seconds
Started May 21 03:08:58 PM PDT 24
Finished May 21 03:09:44 PM PDT 24
Peak memory 256152 kb
Host smart-8518fb87-1a91-401f-9d6e-8ac9aa12f875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
94193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2660394193
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2618474815
Short name T697
Test name
Test status
Simulation time 169291278 ps
CPU time 7.57 seconds
Started May 21 03:09:03 PM PDT 24
Finished May 21 03:09:11 PM PDT 24
Peak memory 252036 kb
Host smart-108c1865-0ead-4127-bf6b-15b267c06bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26184
74815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2618474815
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1390322104
Short name T213
Test name
Test status
Simulation time 155539122 ps
CPU time 6.85 seconds
Started May 21 03:08:58 PM PDT 24
Finished May 21 03:09:06 PM PDT 24
Peak memory 240648 kb
Host smart-ce70a2fb-5701-4a94-bd59-30ad8be93064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13903
22104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1390322104
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3061121211
Short name T514
Test name
Test status
Simulation time 29487373346 ps
CPU time 692.61 seconds
Started May 21 03:09:08 PM PDT 24
Finished May 21 03:20:43 PM PDT 24
Peak memory 273372 kb
Host smart-943bce14-e45f-4bb2-988a-80a932503a36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061121211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3061121211
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.18367375
Short name T559
Test name
Test status
Simulation time 13362314260 ps
CPU time 1250.04 seconds
Started May 21 03:09:14 PM PDT 24
Finished May 21 03:30:07 PM PDT 24
Peak memory 289532 kb
Host smart-bbace3f7-ee77-4a5e-b1a9-7544f5a8bd74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18367375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.18367375
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.394458067
Short name T608
Test name
Test status
Simulation time 39279057191 ps
CPU time 208.4 seconds
Started May 21 03:09:13 PM PDT 24
Finished May 21 03:12:44 PM PDT 24
Peak memory 250976 kb
Host smart-70062045-0fdf-466a-a7aa-39ec1d3ab119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
8067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.394458067
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3248417065
Short name T468
Test name
Test status
Simulation time 3071531720 ps
CPU time 44.09 seconds
Started May 21 03:09:12 PM PDT 24
Finished May 21 03:09:58 PM PDT 24
Peak memory 248836 kb
Host smart-86e69d9a-3e01-4648-bca0-db509dc29de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32484
17065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3248417065
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1728386
Short name T556
Test name
Test status
Simulation time 16286533157 ps
CPU time 1145.18 seconds
Started May 21 03:09:19 PM PDT 24
Finished May 21 03:28:25 PM PDT 24
Peak memory 271420 kb
Host smart-c28edb28-bae3-4d31-b807-541384c270a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1728386
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.324555323
Short name T577
Test name
Test status
Simulation time 98230269530 ps
CPU time 2053.81 seconds
Started May 21 03:09:19 PM PDT 24
Finished May 21 03:43:34 PM PDT 24
Peak memory 283188 kb
Host smart-c41b2dd5-113f-4a44-a568-ac6c05d20b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324555323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.324555323
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.756761622
Short name T676
Test name
Test status
Simulation time 12850453330 ps
CPU time 548.58 seconds
Started May 21 03:09:25 PM PDT 24
Finished May 21 03:18:35 PM PDT 24
Peak memory 255160 kb
Host smart-f2150bd2-de89-44a8-ade0-98657cfb17ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756761622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.756761622
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2787123589
Short name T371
Test name
Test status
Simulation time 880455946 ps
CPU time 53.15 seconds
Started May 21 03:09:13 PM PDT 24
Finished May 21 03:10:08 PM PDT 24
Peak memory 248832 kb
Host smart-9f0adead-d12a-4715-abcc-18837abaa3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27871
23589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2787123589
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1882426155
Short name T64
Test name
Test status
Simulation time 819001081 ps
CPU time 32.64 seconds
Started May 21 03:09:15 PM PDT 24
Finished May 21 03:09:49 PM PDT 24
Peak memory 255648 kb
Host smart-95191b06-5f1d-463d-9318-838b09959dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
26155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1882426155
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3444558355
Short name T84
Test name
Test status
Simulation time 778395390 ps
CPU time 56.73 seconds
Started May 21 03:09:14 PM PDT 24
Finished May 21 03:10:13 PM PDT 24
Peak memory 255956 kb
Host smart-41325b61-cbdc-4083-81af-71aca305d947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34445
58355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3444558355
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2362026357
Short name T352
Test name
Test status
Simulation time 178614018 ps
CPU time 16.87 seconds
Started May 21 03:09:07 PM PDT 24
Finished May 21 03:09:25 PM PDT 24
Peak memory 248744 kb
Host smart-69e02998-1907-41f0-8a38-a3098edc10e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23620
26357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2362026357
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2941955504
Short name T50
Test name
Test status
Simulation time 8162154430 ps
CPU time 162.45 seconds
Started May 21 03:09:21 PM PDT 24
Finished May 21 03:12:04 PM PDT 24
Peak memory 251912 kb
Host smart-3dd6b86f-9eec-4b9b-a31f-d94d1efc26d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941955504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2941955504
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3373526298
Short name T378
Test name
Test status
Simulation time 49253150270 ps
CPU time 1786.92 seconds
Started May 21 03:09:24 PM PDT 24
Finished May 21 03:39:12 PM PDT 24
Peak memory 273400 kb
Host smart-044f7188-9665-4bce-bd5a-402ae149b051
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373526298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3373526298
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2543267389
Short name T517
Test name
Test status
Simulation time 4679926097 ps
CPU time 70.13 seconds
Started May 21 03:09:24 PM PDT 24
Finished May 21 03:10:35 PM PDT 24
Peak memory 256728 kb
Host smart-6339bef8-f1e2-414d-9e68-f50f8c93fe2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
67389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2543267389
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2862274226
Short name T467
Test name
Test status
Simulation time 1486063786 ps
CPU time 33.65 seconds
Started May 21 03:09:27 PM PDT 24
Finished May 21 03:10:01 PM PDT 24
Peak memory 255988 kb
Host smart-776cbcb1-5031-4c41-ae89-c2bcdf43c6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28622
74226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2862274226
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.371387093
Short name T290
Test name
Test status
Simulation time 31954366896 ps
CPU time 1457.13 seconds
Started May 21 03:09:37 PM PDT 24
Finished May 21 03:33:55 PM PDT 24
Peak memory 285060 kb
Host smart-6fb4cc05-0038-4e15-ab01-69e32858e106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371387093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.371387093
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4273288436
Short name T652
Test name
Test status
Simulation time 26082045108 ps
CPU time 1673.5 seconds
Started May 21 03:09:29 PM PDT 24
Finished May 21 03:37:24 PM PDT 24
Peak memory 273376 kb
Host smart-f9f76641-7109-45dd-9745-911d469a9688
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273288436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4273288436
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1404014810
Short name T315
Test name
Test status
Simulation time 10992494530 ps
CPU time 218.13 seconds
Started May 21 03:09:27 PM PDT 24
Finished May 21 03:13:06 PM PDT 24
Peak memory 254440 kb
Host smart-0003ce60-31af-4e6c-83a3-96f9f9401da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404014810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1404014810
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3409518050
Short name T497
Test name
Test status
Simulation time 828090469 ps
CPU time 53.01 seconds
Started May 21 03:09:18 PM PDT 24
Finished May 21 03:10:12 PM PDT 24
Peak memory 248768 kb
Host smart-df4493d2-77e3-4467-b138-6344a172536d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34095
18050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3409518050
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2364432694
Short name T364
Test name
Test status
Simulation time 222675660 ps
CPU time 11.37 seconds
Started May 21 03:09:24 PM PDT 24
Finished May 21 03:09:37 PM PDT 24
Peak memory 248752 kb
Host smart-ffe47eb2-7c58-4e53-8ab4-45e8a902c55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644
32694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2364432694
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4139302412
Short name T247
Test name
Test status
Simulation time 175045518 ps
CPU time 10.64 seconds
Started May 21 03:09:26 PM PDT 24
Finished May 21 03:09:38 PM PDT 24
Peak memory 253100 kb
Host smart-a126bf9e-a8fe-4c2e-9f4d-62c81702d31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41393
02412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4139302412
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3573247993
Short name T521
Test name
Test status
Simulation time 1774694445 ps
CPU time 46.6 seconds
Started May 21 03:09:20 PM PDT 24
Finished May 21 03:10:07 PM PDT 24
Peak memory 256040 kb
Host smart-69ab5cb4-b180-4a12-b49b-7e2c79d76e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35732
47993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3573247993
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.473818597
Short name T255
Test name
Test status
Simulation time 26023861972 ps
CPU time 1154.83 seconds
Started May 21 03:09:30 PM PDT 24
Finished May 21 03:28:46 PM PDT 24
Peak memory 285636 kb
Host smart-13989d0a-36b0-4595-9df4-932af1fb0be4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473818597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.473818597
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2675507129
Short name T198
Test name
Test status
Simulation time 141407283 ps
CPU time 3.21 seconds
Started May 21 03:04:51 PM PDT 24
Finished May 21 03:04:56 PM PDT 24
Peak memory 248932 kb
Host smart-789c321f-b588-4afc-a73c-58afaa0d2ed0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2675507129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2675507129
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4055388870
Short name T433
Test name
Test status
Simulation time 96527359064 ps
CPU time 1276.99 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:26:03 PM PDT 24
Peak memory 272852 kb
Host smart-03795d67-4579-4945-8f6d-d49e649a6ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055388870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4055388870
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.716009556
Short name T593
Test name
Test status
Simulation time 181001255 ps
CPU time 10.24 seconds
Started May 21 03:04:49 PM PDT 24
Finished May 21 03:05:00 PM PDT 24
Peak memory 248716 kb
Host smart-843909a4-6e77-46b5-9c9a-a04512665cca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=716009556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.716009556
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3075217588
Short name T267
Test name
Test status
Simulation time 6454828917 ps
CPU time 237.91 seconds
Started May 21 03:04:40 PM PDT 24
Finished May 21 03:08:40 PM PDT 24
Peak memory 249844 kb
Host smart-c56bf948-f941-40fc-bede-4e9f8e719da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
17588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3075217588
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4241287352
Short name T253
Test name
Test status
Simulation time 4324490406 ps
CPU time 61.85 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:05:47 PM PDT 24
Peak memory 256896 kb
Host smart-5f30acfd-d54c-480e-bf5b-fd23660f2686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
87352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4241287352
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.876466350
Short name T329
Test name
Test status
Simulation time 155923873872 ps
CPU time 739.12 seconds
Started May 21 03:04:46 PM PDT 24
Finished May 21 03:17:08 PM PDT 24
Peak memory 265244 kb
Host smart-a580265b-8f45-4d8a-9e88-3b661a851a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876466350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.876466350
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3937987779
Short name T469
Test name
Test status
Simulation time 45372143213 ps
CPU time 2687.38 seconds
Started May 21 03:04:46 PM PDT 24
Finished May 21 03:49:37 PM PDT 24
Peak memory 281624 kb
Host smart-a6f5a006-0894-439c-9a49-84a057c7b629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937987779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3937987779
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1485457586
Short name T384
Test name
Test status
Simulation time 830583916 ps
CPU time 26.26 seconds
Started May 21 03:04:43 PM PDT 24
Finished May 21 03:05:13 PM PDT 24
Peak memory 256928 kb
Host smart-94a5c887-f185-4aa0-8f99-3224b986b750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14854
57586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1485457586
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.467136974
Short name T671
Test name
Test status
Simulation time 3527601825 ps
CPU time 56.5 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:05:42 PM PDT 24
Peak memory 255192 kb
Host smart-4ee9f0cd-ad92-46c8-a847-2d113b4ba7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46713
6974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.467136974
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.286588378
Short name T366
Test name
Test status
Simulation time 895952961 ps
CPU time 49.88 seconds
Started May 21 03:04:42 PM PDT 24
Finished May 21 03:05:35 PM PDT 24
Peak memory 248816 kb
Host smart-4d45eeb1-a054-4eb2-8435-aed325fa0d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28658
8378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.286588378
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1622845010
Short name T185
Test name
Test status
Simulation time 388120776 ps
CPU time 23.26 seconds
Started May 21 03:04:41 PM PDT 24
Finished May 21 03:05:07 PM PDT 24
Peak memory 256956 kb
Host smart-113abfe0-017b-4539-afbc-1c67231364c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
45010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1622845010
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1040456490
Short name T436
Test name
Test status
Simulation time 3853725378 ps
CPU time 56.55 seconds
Started May 21 03:04:47 PM PDT 24
Finished May 21 03:05:46 PM PDT 24
Peak memory 256572 kb
Host smart-b552bad0-d151-4cb6-bc8c-39ae3d9f034a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040456490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1040456490
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3434645210
Short name T106
Test name
Test status
Simulation time 71928580976 ps
CPU time 3053.49 seconds
Started May 21 03:09:34 PM PDT 24
Finished May 21 04:00:29 PM PDT 24
Peak memory 289396 kb
Host smart-261e7544-2f09-4be1-a28a-e70f4160e681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434645210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3434645210
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3524933628
Short name T362
Test name
Test status
Simulation time 794323359 ps
CPU time 43.58 seconds
Started May 21 03:09:34 PM PDT 24
Finished May 21 03:10:18 PM PDT 24
Peak memory 248916 kb
Host smart-18327ad6-6077-46bc-b976-db70755ea406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35249
33628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3524933628
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.177633527
Short name T405
Test name
Test status
Simulation time 1081645863 ps
CPU time 27.99 seconds
Started May 21 03:09:40 PM PDT 24
Finished May 21 03:10:09 PM PDT 24
Peak memory 248772 kb
Host smart-e1d594f1-7358-4646-8b16-d4e47ded3a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17763
3527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.177633527
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3963859911
Short name T337
Test name
Test status
Simulation time 74702638887 ps
CPU time 2589.72 seconds
Started May 21 03:09:41 PM PDT 24
Finished May 21 03:52:52 PM PDT 24
Peak memory 288156 kb
Host smart-64f28aed-747c-4b41-b23c-3674488761b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963859911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3963859911
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1750232501
Short name T647
Test name
Test status
Simulation time 11218991143 ps
CPU time 1075.48 seconds
Started May 21 03:09:42 PM PDT 24
Finished May 21 03:27:39 PM PDT 24
Peak memory 273020 kb
Host smart-25ab69a1-3aa5-4c96-9343-e6e2e7331fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750232501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1750232501
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4052647959
Short name T300
Test name
Test status
Simulation time 74547436343 ps
CPU time 727.96 seconds
Started May 21 03:09:42 PM PDT 24
Finished May 21 03:21:51 PM PDT 24
Peak memory 248020 kb
Host smart-dfba05ca-8a73-468c-9d5d-7d774a1b1750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052647959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4052647959
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.69871014
Short name T663
Test name
Test status
Simulation time 2793436423 ps
CPU time 57.51 seconds
Started May 21 03:09:31 PM PDT 24
Finished May 21 03:10:29 PM PDT 24
Peak memory 248836 kb
Host smart-ffdaa64e-8719-46bb-b291-7a071b202997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69871
014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.69871014
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3463772777
Short name T280
Test name
Test status
Simulation time 471479133 ps
CPU time 32.47 seconds
Started May 21 03:09:40 PM PDT 24
Finished May 21 03:10:14 PM PDT 24
Peak memory 247444 kb
Host smart-3f508266-7f99-45f2-b100-43ba0e4e8d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
72777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3463772777
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1863827701
Short name T582
Test name
Test status
Simulation time 1372761140 ps
CPU time 45.72 seconds
Started May 21 03:09:35 PM PDT 24
Finished May 21 03:10:21 PM PDT 24
Peak memory 256724 kb
Host smart-412be553-01b3-4b3f-bfad-aeed1c68d1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
27701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1863827701
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2779352702
Short name T451
Test name
Test status
Simulation time 230561876 ps
CPU time 22.75 seconds
Started May 21 03:09:31 PM PDT 24
Finished May 21 03:09:54 PM PDT 24
Peak memory 256100 kb
Host smart-eff2ef4f-0672-4dca-bd1f-164a36c6746c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27793
52702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2779352702
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1065721209
Short name T407
Test name
Test status
Simulation time 21621939501 ps
CPU time 1349 seconds
Started May 21 03:09:48 PM PDT 24
Finished May 21 03:32:18 PM PDT 24
Peak memory 273008 kb
Host smart-6c35a9f5-fdaa-43e8-ad5e-78a7d7bb77b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065721209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1065721209
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.933488742
Short name T674
Test name
Test status
Simulation time 11608144193 ps
CPU time 184.23 seconds
Started May 21 03:09:48 PM PDT 24
Finished May 21 03:12:53 PM PDT 24
Peak memory 257028 kb
Host smart-6964504e-c230-4dde-a5ee-5a0df1a492c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93348
8742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.933488742
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1250148616
Short name T409
Test name
Test status
Simulation time 1781714580 ps
CPU time 33.97 seconds
Started May 21 03:09:48 PM PDT 24
Finished May 21 03:10:23 PM PDT 24
Peak memory 248756 kb
Host smart-71ffe3a7-f318-4710-b2a7-4517f55f8b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
48616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1250148616
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2028628558
Short name T691
Test name
Test status
Simulation time 69058226400 ps
CPU time 2212.76 seconds
Started May 21 03:09:56 PM PDT 24
Finished May 21 03:46:50 PM PDT 24
Peak memory 289180 kb
Host smart-537fd6e6-ab87-4121-b924-2bdf41c54142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028628558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2028628558
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1447066293
Short name T466
Test name
Test status
Simulation time 19246854520 ps
CPU time 117.96 seconds
Started May 21 03:10:08 PM PDT 24
Finished May 21 03:12:07 PM PDT 24
Peak memory 247928 kb
Host smart-e4ff78b0-5b46-45f2-8488-e4d7fb41a0c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447066293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1447066293
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1348314484
Short name T399
Test name
Test status
Simulation time 2002873260 ps
CPU time 29.74 seconds
Started May 21 03:09:43 PM PDT 24
Finished May 21 03:10:14 PM PDT 24
Peak memory 248780 kb
Host smart-824269bc-b1a3-4568-bf19-b0fd90f4f9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
14484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1348314484
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2421011447
Short name T632
Test name
Test status
Simulation time 42809652 ps
CPU time 4.08 seconds
Started May 21 03:09:47 PM PDT 24
Finished May 21 03:09:52 PM PDT 24
Peak memory 240544 kb
Host smart-dd15ee00-0f15-4cec-a788-7781eb082700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
11447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2421011447
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3100605384
Short name T635
Test name
Test status
Simulation time 2333507918 ps
CPU time 39.05 seconds
Started May 21 03:09:48 PM PDT 24
Finished May 21 03:10:28 PM PDT 24
Peak memory 255540 kb
Host smart-21433961-d8fe-4d1d-bbd4-0ac34ac28852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
05384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3100605384
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4198154042
Short name T372
Test name
Test status
Simulation time 319560608 ps
CPU time 10.18 seconds
Started May 21 03:09:44 PM PDT 24
Finished May 21 03:09:55 PM PDT 24
Peak memory 248780 kb
Host smart-5a596378-0a4f-4a2c-a061-d71a54cb8ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
54042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4198154042
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2447735846
Short name T263
Test name
Test status
Simulation time 53114555671 ps
CPU time 1196.99 seconds
Started May 21 03:09:54 PM PDT 24
Finished May 21 03:29:53 PM PDT 24
Peak memory 287628 kb
Host smart-91dcad4d-ecc1-4f14-90f3-48f4a2d03ae6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447735846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2447735846
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1574654322
Short name T701
Test name
Test status
Simulation time 78885791019 ps
CPU time 1302.63 seconds
Started May 21 03:10:05 PM PDT 24
Finished May 21 03:31:48 PM PDT 24
Peak memory 288812 kb
Host smart-7bdf08ab-7298-4e09-befe-8f91c2517572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574654322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1574654322
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4098779628
Short name T210
Test name
Test status
Simulation time 16719042603 ps
CPU time 332.14 seconds
Started May 21 03:10:06 PM PDT 24
Finished May 21 03:15:39 PM PDT 24
Peak memory 256928 kb
Host smart-ece3386d-4e40-4eea-8c80-f0a6b52ac8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
79628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4098779628
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3819348948
Short name T355
Test name
Test status
Simulation time 1433548729 ps
CPU time 32.37 seconds
Started May 21 03:10:05 PM PDT 24
Finished May 21 03:10:37 PM PDT 24
Peak memory 248800 kb
Host smart-e156d507-0e55-48cb-81ae-32ee3b17e291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
48948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3819348948
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2848709561
Short name T667
Test name
Test status
Simulation time 80346955789 ps
CPU time 2114.25 seconds
Started May 21 03:10:05 PM PDT 24
Finished May 21 03:45:20 PM PDT 24
Peak memory 269308 kb
Host smart-d93d7d31-fd5a-4a0a-b02a-5099d4cb4cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848709561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2848709561
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1771519442
Short name T6
Test name
Test status
Simulation time 50692900810 ps
CPU time 1254.76 seconds
Started May 21 03:10:10 PM PDT 24
Finished May 21 03:31:05 PM PDT 24
Peak memory 285724 kb
Host smart-58bf2510-d1ac-45a5-9bc7-8abbe4068a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771519442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1771519442
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2786985646
Short name T693
Test name
Test status
Simulation time 11367572630 ps
CPU time 442.13 seconds
Started May 21 03:10:07 PM PDT 24
Finished May 21 03:17:30 PM PDT 24
Peak memory 254552 kb
Host smart-9f93860a-ead4-4360-9af3-118cdb071e88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786985646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2786985646
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4148782905
Short name T227
Test name
Test status
Simulation time 82030921 ps
CPU time 11.92 seconds
Started May 21 03:10:00 PM PDT 24
Finished May 21 03:10:13 PM PDT 24
Peak memory 248760 kb
Host smart-2d20b470-39ab-466b-8b54-ce4c81bdfdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
82905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4148782905
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2065585437
Short name T427
Test name
Test status
Simulation time 409492754 ps
CPU time 32.41 seconds
Started May 21 03:10:04 PM PDT 24
Finished May 21 03:10:37 PM PDT 24
Peak memory 248740 kb
Host smart-6359ebf5-1c7b-40cc-9f68-dd0c8902e394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20655
85437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2065585437
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1222440419
Short name T90
Test name
Test status
Simulation time 89519521 ps
CPU time 9.78 seconds
Started May 21 03:10:07 PM PDT 24
Finished May 21 03:10:17 PM PDT 24
Peak memory 249228 kb
Host smart-eed0e5ff-f26a-4927-8ad5-045fca0f7c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
40419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1222440419
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3991763148
Short name T279
Test name
Test status
Simulation time 5789789476 ps
CPU time 39.9 seconds
Started May 21 03:10:00 PM PDT 24
Finished May 21 03:10:41 PM PDT 24
Peak memory 248816 kb
Host smart-6ceffc8f-888f-40dc-a19d-50bdb4fcb69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39917
63148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3991763148
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3693724578
Short name T629
Test name
Test status
Simulation time 218336846862 ps
CPU time 3490.48 seconds
Started May 21 03:10:16 PM PDT 24
Finished May 21 04:08:28 PM PDT 24
Peak memory 297712 kb
Host smart-5aef379a-f24e-4ab1-b15f-c870d445198e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693724578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3693724578
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2574823843
Short name T100
Test name
Test status
Simulation time 53438314850 ps
CPU time 1680.58 seconds
Started May 21 03:10:17 PM PDT 24
Finished May 21 03:38:19 PM PDT 24
Peak memory 273424 kb
Host smart-2e874415-e063-4d3c-a478-964c1737396a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574823843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2574823843
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.832476061
Short name T424
Test name
Test status
Simulation time 1070397911 ps
CPU time 127.97 seconds
Started May 21 03:10:16 PM PDT 24
Finished May 21 03:12:24 PM PDT 24
Peak memory 256932 kb
Host smart-db0175e8-f154-4b80-9f4c-6a8dc6b18f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83247
6061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.832476061
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.104166790
Short name T485
Test name
Test status
Simulation time 441858581 ps
CPU time 43.57 seconds
Started May 21 03:10:17 PM PDT 24
Finished May 21 03:11:01 PM PDT 24
Peak memory 256164 kb
Host smart-4f4583de-62f4-4b20-bd56-254f2601af1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10416
6790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.104166790
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3099809444
Short name T571
Test name
Test status
Simulation time 39923446466 ps
CPU time 975.73 seconds
Started May 21 03:10:21 PM PDT 24
Finished May 21 03:26:37 PM PDT 24
Peak memory 272748 kb
Host smart-7a2e73fd-ff02-4f84-931b-33e8c8b79ad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099809444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3099809444
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.736489526
Short name T440
Test name
Test status
Simulation time 23736896952 ps
CPU time 1701.67 seconds
Started May 21 03:10:20 PM PDT 24
Finished May 21 03:38:43 PM PDT 24
Peak memory 273404 kb
Host smart-68255578-1787-4dcc-9fa8-0d3f5f409427
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736489526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.736489526
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2304149977
Short name T215
Test name
Test status
Simulation time 6145973583 ps
CPU time 245.44 seconds
Started May 21 03:10:20 PM PDT 24
Finished May 21 03:14:26 PM PDT 24
Peak memory 248376 kb
Host smart-e78127c4-d2c9-4df3-913c-8bbb2975cb87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304149977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2304149977
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.976525892
Short name T611
Test name
Test status
Simulation time 1126559288 ps
CPU time 22.75 seconds
Started May 21 03:10:16 PM PDT 24
Finished May 21 03:10:39 PM PDT 24
Peak memory 255928 kb
Host smart-5f8a5500-f2c2-499d-8d73-f942bfccc26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97652
5892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.976525892
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3772061353
Short name T574
Test name
Test status
Simulation time 2340096295 ps
CPU time 65.11 seconds
Started May 21 03:10:16 PM PDT 24
Finished May 21 03:11:23 PM PDT 24
Peak memory 248840 kb
Host smart-528338ee-295d-4c3d-838b-9dfe7cab758f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37720
61353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3772061353
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1497970757
Short name T254
Test name
Test status
Simulation time 594691446 ps
CPU time 19.12 seconds
Started May 21 03:10:16 PM PDT 24
Finished May 21 03:10:36 PM PDT 24
Peak memory 248764 kb
Host smart-44b520e3-cbcd-420d-9059-97742dcdff26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14979
70757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1497970757
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.586900668
Short name T450
Test name
Test status
Simulation time 270879594 ps
CPU time 16.44 seconds
Started May 21 03:10:11 PM PDT 24
Finished May 21 03:10:28 PM PDT 24
Peak memory 248796 kb
Host smart-1e3a6a0b-03f7-4742-b7fe-6383f501e99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58690
0668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.586900668
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2476688409
Short name T705
Test name
Test status
Simulation time 166313833606 ps
CPU time 3843.9 seconds
Started May 21 03:10:29 PM PDT 24
Finished May 21 04:14:34 PM PDT 24
Peak memory 289824 kb
Host smart-d4b74888-f295-480f-b8a1-da912f868216
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476688409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2476688409
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3140658277
Short name T269
Test name
Test status
Simulation time 34499339341 ps
CPU time 1976.59 seconds
Started May 21 03:10:27 PM PDT 24
Finished May 21 03:43:25 PM PDT 24
Peak memory 281648 kb
Host smart-7bf8c9c6-90e2-4798-8c3e-a74702e5d25d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140658277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3140658277
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3055837095
Short name T609
Test name
Test status
Simulation time 20452456059 ps
CPU time 261.99 seconds
Started May 21 03:10:29 PM PDT 24
Finished May 21 03:14:52 PM PDT 24
Peak memory 257020 kb
Host smart-4d74b13d-36a7-48f5-b011-4debc6cf2650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30558
37095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3055837095
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1754324435
Short name T487
Test name
Test status
Simulation time 333248646 ps
CPU time 4.9 seconds
Started May 21 03:10:35 PM PDT 24
Finished May 21 03:10:41 PM PDT 24
Peak memory 240584 kb
Host smart-828758bd-ee10-496e-9005-412140be8f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
24435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1754324435
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.764230946
Short name T322
Test name
Test status
Simulation time 37280594492 ps
CPU time 2150.78 seconds
Started May 21 03:10:33 PM PDT 24
Finished May 21 03:46:25 PM PDT 24
Peak memory 273368 kb
Host smart-3dc5d9e9-d39e-4144-a1bc-452f6b2a9276
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764230946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.764230946
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3080416068
Short name T437
Test name
Test status
Simulation time 481453120539 ps
CPU time 1491.02 seconds
Started May 21 03:10:33 PM PDT 24
Finished May 21 03:35:25 PM PDT 24
Peak memory 268332 kb
Host smart-91c4a116-6ebd-4431-9df2-2635b234749b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080416068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3080416068
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2931193658
Short name T312
Test name
Test status
Simulation time 65596860640 ps
CPU time 423.97 seconds
Started May 21 03:10:35 PM PDT 24
Finished May 21 03:17:39 PM PDT 24
Peak memory 248236 kb
Host smart-d6d4dc0a-77a0-457f-8867-39496aa17e70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931193658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2931193658
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1902195383
Short name T509
Test name
Test status
Simulation time 3321563260 ps
CPU time 33.83 seconds
Started May 21 03:10:29 PM PDT 24
Finished May 21 03:11:04 PM PDT 24
Peak memory 248864 kb
Host smart-46187f61-5439-4c1c-a3c0-6908a5cec411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
95383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1902195383
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.716174698
Short name T365
Test name
Test status
Simulation time 1526443122 ps
CPU time 26.19 seconds
Started May 21 03:10:29 PM PDT 24
Finished May 21 03:10:56 PM PDT 24
Peak memory 248840 kb
Host smart-589d6d8e-dc54-4af0-934d-c69dba2613e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71617
4698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.716174698
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.788996438
Short name T243
Test name
Test status
Simulation time 61263315705 ps
CPU time 3654.09 seconds
Started May 21 03:10:32 PM PDT 24
Finished May 21 04:11:29 PM PDT 24
Peak memory 288720 kb
Host smart-3cb3d3c8-67ae-4ebc-a90b-4497901db9e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788996438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.788996438
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3539267783
Short name T418
Test name
Test status
Simulation time 56074977816 ps
CPU time 1815.8 seconds
Started May 21 03:11:02 PM PDT 24
Finished May 21 03:41:18 PM PDT 24
Peak memory 285748 kb
Host smart-80925d6b-c803-44a0-af9b-20621f10dd61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539267783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3539267783
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.829025417
Short name T488
Test name
Test status
Simulation time 4194093925 ps
CPU time 80.46 seconds
Started May 21 03:10:46 PM PDT 24
Finished May 21 03:12:07 PM PDT 24
Peak memory 257004 kb
Host smart-2af2efab-5b3d-406d-9f39-1a75bc5b3c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82902
5417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.829025417
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1553813238
Short name T464
Test name
Test status
Simulation time 1496757425 ps
CPU time 30.92 seconds
Started May 21 03:10:51 PM PDT 24
Finished May 21 03:11:23 PM PDT 24
Peak memory 248784 kb
Host smart-bb618684-b0cb-41b3-8a5d-b9024a081e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
13238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1553813238
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3158095026
Short name T289
Test name
Test status
Simulation time 25903892736 ps
CPU time 1608.34 seconds
Started May 21 03:10:46 PM PDT 24
Finished May 21 03:37:35 PM PDT 24
Peak memory 272812 kb
Host smart-790766c0-00ee-4ac1-948d-b9d4cd5aff28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158095026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3158095026
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3028529858
Short name T527
Test name
Test status
Simulation time 119747084535 ps
CPU time 689.24 seconds
Started May 21 03:10:46 PM PDT 24
Finished May 21 03:22:16 PM PDT 24
Peak memory 272496 kb
Host smart-0efe190d-0bf9-4745-92c2-ab7d302fff62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028529858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3028529858
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.223995342
Short name T547
Test name
Test status
Simulation time 3385378400 ps
CPU time 75.46 seconds
Started May 21 03:10:47 PM PDT 24
Finished May 21 03:12:04 PM PDT 24
Peak memory 248240 kb
Host smart-1e52b637-cb3c-4639-8071-9d5dbe6bb338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223995342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.223995342
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.15595524
Short name T425
Test name
Test status
Simulation time 1328137869 ps
CPU time 43.42 seconds
Started May 21 03:10:41 PM PDT 24
Finished May 21 03:11:26 PM PDT 24
Peak memory 248812 kb
Host smart-7eade1dd-5bc6-4427-a823-66583fd54f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15595
524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.15595524
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2903470928
Short name T52
Test name
Test status
Simulation time 1040130215 ps
CPU time 20.64 seconds
Started May 21 03:10:50 PM PDT 24
Finished May 21 03:11:12 PM PDT 24
Peak memory 248892 kb
Host smart-5ee2b54e-bd41-4c12-bfeb-9b8b540e46aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
70928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2903470928
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2222193244
Short name T624
Test name
Test status
Simulation time 421032958 ps
CPU time 6.95 seconds
Started May 21 03:10:48 PM PDT 24
Finished May 21 03:10:56 PM PDT 24
Peak memory 252980 kb
Host smart-8b17d44e-d57e-4093-9f66-365046478a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
93244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2222193244
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2798191161
Short name T597
Test name
Test status
Simulation time 7572408175 ps
CPU time 28.62 seconds
Started May 21 03:10:40 PM PDT 24
Finished May 21 03:11:09 PM PDT 24
Peak memory 248828 kb
Host smart-db329d39-4934-4f3e-917e-6371c287343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981
91161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2798191161
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.442424507
Short name T553
Test name
Test status
Simulation time 948107450 ps
CPU time 17.62 seconds
Started May 21 03:10:47 PM PDT 24
Finished May 21 03:11:05 PM PDT 24
Peak memory 248776 kb
Host smart-ba87f1e1-d353-4fc6-9aa7-5d426a6101d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442424507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.442424507
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2331568210
Short name T88
Test name
Test status
Simulation time 49911584130 ps
CPU time 4642.85 seconds
Started May 21 03:10:53 PM PDT 24
Finished May 21 04:28:18 PM PDT 24
Peak memory 322656 kb
Host smart-f5f887be-2d76-4960-9d41-8505c0981835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331568210 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2331568210
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2040289887
Short name T373
Test name
Test status
Simulation time 2598683396 ps
CPU time 30.04 seconds
Started May 21 03:10:52 PM PDT 24
Finished May 21 03:11:23 PM PDT 24
Peak memory 248964 kb
Host smart-9dbc0d9a-5cca-411d-ac93-e261712cc014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
89887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2040289887
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2824276279
Short name T413
Test name
Test status
Simulation time 994584749 ps
CPU time 29.85 seconds
Started May 21 03:10:54 PM PDT 24
Finished May 21 03:11:24 PM PDT 24
Peak memory 256032 kb
Host smart-f6f1778f-1d8d-4b05-8432-4f11d83a81bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
76279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2824276279
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2071938650
Short name T605
Test name
Test status
Simulation time 107449951837 ps
CPU time 1710.15 seconds
Started May 21 03:11:00 PM PDT 24
Finished May 21 03:39:32 PM PDT 24
Peak memory 283156 kb
Host smart-e6e86019-4ea3-4680-90ca-54ff28aac89b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071938650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2071938650
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1382208875
Short name T296
Test name
Test status
Simulation time 43714624147 ps
CPU time 256.35 seconds
Started May 21 03:10:59 PM PDT 24
Finished May 21 03:15:16 PM PDT 24
Peak memory 248812 kb
Host smart-ca04a094-760a-423e-846b-30a732f69cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382208875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1382208875
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3891102390
Short name T356
Test name
Test status
Simulation time 468096139 ps
CPU time 14.42 seconds
Started May 21 03:10:56 PM PDT 24
Finished May 21 03:11:11 PM PDT 24
Peak memory 254080 kb
Host smart-d423381d-fec3-4afb-a143-76455a600066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38911
02390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3891102390
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4263454097
Short name T592
Test name
Test status
Simulation time 1512375387 ps
CPU time 49.61 seconds
Started May 21 03:10:54 PM PDT 24
Finished May 21 03:11:44 PM PDT 24
Peak memory 255616 kb
Host smart-2f42801a-99d0-42e1-bacc-4ba48760258a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42634
54097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4263454097
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3417500786
Short name T699
Test name
Test status
Simulation time 1567660725 ps
CPU time 40.92 seconds
Started May 21 03:10:54 PM PDT 24
Finished May 21 03:11:36 PM PDT 24
Peak memory 248764 kb
Host smart-7ac617b6-8cc0-4286-beff-dd7a434d825e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175
00786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3417500786
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.152377736
Short name T569
Test name
Test status
Simulation time 240866927 ps
CPU time 20.97 seconds
Started May 21 03:10:52 PM PDT 24
Finished May 21 03:11:14 PM PDT 24
Peak memory 248776 kb
Host smart-0a96a782-835f-4a08-ac70-2a4d9926ea53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
7736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.152377736
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3879414044
Short name T46
Test name
Test status
Simulation time 17024503835 ps
CPU time 1573.41 seconds
Started May 21 03:10:57 PM PDT 24
Finished May 21 03:37:12 PM PDT 24
Peak memory 305616 kb
Host smart-1eb4e878-a84d-47a9-bfb2-718052ccc2e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879414044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3879414044
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2290154131
Short name T273
Test name
Test status
Simulation time 202945214143 ps
CPU time 5806.98 seconds
Started May 21 03:10:58 PM PDT 24
Finished May 21 04:47:47 PM PDT 24
Peak memory 355244 kb
Host smart-1a9c1179-96bd-4bbc-aa88-6b5b48c822c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290154131 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2290154131
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1842149390
Short name T580
Test name
Test status
Simulation time 100631438924 ps
CPU time 1537.24 seconds
Started May 21 03:11:10 PM PDT 24
Finished May 21 03:36:47 PM PDT 24
Peak memory 281632 kb
Host smart-d6a8f149-a394-45d8-9292-26f5d18ca650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842149390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1842149390
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.581254662
Short name T525
Test name
Test status
Simulation time 17332788712 ps
CPU time 245.7 seconds
Started May 21 03:11:05 PM PDT 24
Finished May 21 03:15:11 PM PDT 24
Peak memory 257040 kb
Host smart-a8c8ae4d-cbf4-453f-944a-a96e1c2f4463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58125
4662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.581254662
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3231565904
Short name T551
Test name
Test status
Simulation time 4503331441 ps
CPU time 59.43 seconds
Started May 21 03:11:05 PM PDT 24
Finished May 21 03:12:05 PM PDT 24
Peak memory 248852 kb
Host smart-d83d1bf8-cee2-429f-8ddf-ebb0319702d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32315
65904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3231565904
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2681550210
Short name T334
Test name
Test status
Simulation time 37193576214 ps
CPU time 1174.22 seconds
Started May 21 03:11:12 PM PDT 24
Finished May 21 03:30:46 PM PDT 24
Peak memory 265208 kb
Host smart-235771e9-5d44-416e-b22d-60cc3bed5cc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681550210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2681550210
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1375886071
Short name T583
Test name
Test status
Simulation time 107677469756 ps
CPU time 1644.85 seconds
Started May 21 03:11:13 PM PDT 24
Finished May 21 03:38:39 PM PDT 24
Peak memory 273448 kb
Host smart-8677910b-68ce-402f-a84b-70546773caad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375886071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1375886071
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.929982185
Short name T209
Test name
Test status
Simulation time 9303376823 ps
CPU time 108.1 seconds
Started May 21 03:11:09 PM PDT 24
Finished May 21 03:12:57 PM PDT 24
Peak memory 248296 kb
Host smart-626f909c-bbb4-446c-8c4e-795823d93631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929982185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.929982185
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.952818405
Short name T61
Test name
Test status
Simulation time 430550592 ps
CPU time 31.24 seconds
Started May 21 03:11:03 PM PDT 24
Finished May 21 03:11:35 PM PDT 24
Peak memory 248772 kb
Host smart-04c4284a-f414-4ff2-b47d-0e6819c849d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95281
8405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.952818405
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3934960545
Short name T105
Test name
Test status
Simulation time 2624567851 ps
CPU time 47.79 seconds
Started May 21 03:11:03 PM PDT 24
Finished May 21 03:11:52 PM PDT 24
Peak memory 248280 kb
Host smart-e36ca4d0-9053-43b0-b9fc-57c7226efabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349
60545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3934960545
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2072269365
Short name T412
Test name
Test status
Simulation time 958186316 ps
CPU time 35.22 seconds
Started May 21 03:11:19 PM PDT 24
Finished May 21 03:11:56 PM PDT 24
Peak memory 255620 kb
Host smart-17dd4e23-dfde-4579-a9cd-e6110e79b04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
69365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2072269365
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.813905059
Short name T666
Test name
Test status
Simulation time 3435087839 ps
CPU time 50.84 seconds
Started May 21 03:10:58 PM PDT 24
Finished May 21 03:11:50 PM PDT 24
Peak memory 248856 kb
Host smart-071022e7-0515-4188-9f3d-18bb55b922b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81390
5059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.813905059
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2402000541
Short name T606
Test name
Test status
Simulation time 860968056 ps
CPU time 21.18 seconds
Started May 21 03:11:10 PM PDT 24
Finished May 21 03:11:32 PM PDT 24
Peak memory 256112 kb
Host smart-c461f047-2730-476c-88a7-08584f20c353
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402000541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2402000541
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4184048735
Short name T275
Test name
Test status
Simulation time 79862709752 ps
CPU time 1548.88 seconds
Started May 21 03:11:22 PM PDT 24
Finished May 21 03:37:13 PM PDT 24
Peak memory 289432 kb
Host smart-4f94a0e2-74ef-45a4-80a8-9dadbc77c1b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184048735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4184048735
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.677322494
Short name T546
Test name
Test status
Simulation time 8902236466 ps
CPU time 132.83 seconds
Started May 21 03:11:18 PM PDT 24
Finished May 21 03:13:33 PM PDT 24
Peak memory 256988 kb
Host smart-9768607f-99e1-439b-9143-207c372f2a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67732
2494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.677322494
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1714904424
Short name T182
Test name
Test status
Simulation time 107013878 ps
CPU time 11.73 seconds
Started May 21 03:11:16 PM PDT 24
Finished May 21 03:11:29 PM PDT 24
Peak memory 248852 kb
Host smart-750a28dd-834d-448a-a03f-0e0214af8169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17149
04424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1714904424
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3104563445
Short name T327
Test name
Test status
Simulation time 65336256390 ps
CPU time 1341.44 seconds
Started May 21 03:11:32 PM PDT 24
Finished May 21 03:33:54 PM PDT 24
Peak memory 281584 kb
Host smart-f92f1646-16ce-4814-b7a4-dc3fd091564d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104563445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3104563445
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3300338848
Short name T533
Test name
Test status
Simulation time 440014221601 ps
CPU time 2486.72 seconds
Started May 21 03:11:36 PM PDT 24
Finished May 21 03:53:04 PM PDT 24
Peak memory 281164 kb
Host smart-b5144fea-3a82-431e-98f6-5dba0eba4e70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300338848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3300338848
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1637086413
Short name T623
Test name
Test status
Simulation time 21404089183 ps
CPU time 475.82 seconds
Started May 21 03:11:31 PM PDT 24
Finished May 21 03:19:28 PM PDT 24
Peak memory 248360 kb
Host smart-731ed2f6-343c-4fb7-bf20-f870b5d3ee20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637086413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1637086413
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2726633474
Short name T476
Test name
Test status
Simulation time 627495378 ps
CPU time 21.42 seconds
Started May 21 03:11:15 PM PDT 24
Finished May 21 03:11:38 PM PDT 24
Peak memory 254692 kb
Host smart-a8ec19ab-dc8d-49c6-b503-c241564ac15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27266
33474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2726633474
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.850523240
Short name T500
Test name
Test status
Simulation time 1025485232 ps
CPU time 64.27 seconds
Started May 21 03:11:17 PM PDT 24
Finished May 21 03:12:23 PM PDT 24
Peak memory 248804 kb
Host smart-9d55949c-e00c-4f76-8a4e-a28962b78efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85052
3240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.850523240
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1763948494
Short name T252
Test name
Test status
Simulation time 1112441118 ps
CPU time 63.71 seconds
Started May 21 03:11:16 PM PDT 24
Finished May 21 03:12:21 PM PDT 24
Peak memory 255760 kb
Host smart-c7dc40fc-aca3-422b-947c-37ae22b5977c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17639
48494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1763948494
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.73815340
Short name T536
Test name
Test status
Simulation time 600781816 ps
CPU time 42.73 seconds
Started May 21 03:11:15 PM PDT 24
Finished May 21 03:11:59 PM PDT 24
Peak memory 248916 kb
Host smart-6e78d067-2cb0-4af4-9cc5-107a7603aafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73815
340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.73815340
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1564873158
Short name T244
Test name
Test status
Simulation time 11039346221 ps
CPU time 1013.79 seconds
Started May 21 03:11:39 PM PDT 24
Finished May 21 03:28:33 PM PDT 24
Peak memory 285984 kb
Host smart-7336a2e7-ede7-437a-be32-da49dcfbdf58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564873158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1564873158
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1065564087
Short name T30
Test name
Test status
Simulation time 9567530375 ps
CPU time 595.22 seconds
Started May 21 03:11:37 PM PDT 24
Finished May 21 03:21:32 PM PDT 24
Peak memory 266356 kb
Host smart-22792b5c-5207-424a-814b-636c769feebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065564087 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1065564087
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1189193689
Short name T470
Test name
Test status
Simulation time 3390675729 ps
CPU time 60.7 seconds
Started May 21 03:11:44 PM PDT 24
Finished May 21 03:12:46 PM PDT 24
Peak memory 248848 kb
Host smart-555568f2-0d9e-4753-8989-641832843fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11891
93689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1189193689
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3576900762
Short name T548
Test name
Test status
Simulation time 804212315 ps
CPU time 12.81 seconds
Started May 21 03:11:39 PM PDT 24
Finished May 21 03:11:52 PM PDT 24
Peak memory 248804 kb
Host smart-760baf3a-6605-45d2-a9d9-3808bca1cfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
00762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3576900762
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4274326306
Short name T333
Test name
Test status
Simulation time 47223345949 ps
CPU time 2858.54 seconds
Started May 21 03:11:47 PM PDT 24
Finished May 21 03:59:26 PM PDT 24
Peak memory 281648 kb
Host smart-5a022e96-5aa2-46c3-9171-761277490a85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274326306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4274326306
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4205141036
Short name T214
Test name
Test status
Simulation time 165057767745 ps
CPU time 2515.06 seconds
Started May 21 03:11:57 PM PDT 24
Finished May 21 03:53:53 PM PDT 24
Peak memory 272420 kb
Host smart-92aa9757-e303-460c-8307-573c283535a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205141036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4205141036
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2407896078
Short name T579
Test name
Test status
Simulation time 3222674393 ps
CPU time 135.2 seconds
Started May 21 03:11:40 PM PDT 24
Finished May 21 03:13:56 PM PDT 24
Peak memory 253092 kb
Host smart-ab112940-53a3-46ed-8186-1f17d12f27f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407896078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2407896078
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.132617461
Short name T386
Test name
Test status
Simulation time 199928618 ps
CPU time 21.22 seconds
Started May 21 03:11:37 PM PDT 24
Finished May 21 03:11:58 PM PDT 24
Peak memory 256928 kb
Host smart-958ad819-f4ec-4aaf-9d6a-0a8ed6cca719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
7461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.132617461
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3612077840
Short name T668
Test name
Test status
Simulation time 316405060 ps
CPU time 11.58 seconds
Started May 21 03:11:38 PM PDT 24
Finished May 21 03:11:49 PM PDT 24
Peak memory 254976 kb
Host smart-17c66380-b6e2-440d-bd94-410b62c4f839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
77840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3612077840
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2770963493
Short name T257
Test name
Test status
Simulation time 77589282133 ps
CPU time 2337.3 seconds
Started May 21 03:11:43 PM PDT 24
Finished May 21 03:50:41 PM PDT 24
Peak memory 289572 kb
Host smart-bcf8f77e-e10c-4f84-9bdd-bb8c9086d8f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770963493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2770963493
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.902040415
Short name T708
Test name
Test status
Simulation time 66953316116 ps
CPU time 5441.4 seconds
Started May 21 03:11:44 PM PDT 24
Finished May 21 04:42:26 PM PDT 24
Peak memory 321868 kb
Host smart-34832ed7-bbb8-41f5-8175-a453ccc4f114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902040415 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.902040415
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1202472990
Short name T607
Test name
Test status
Simulation time 11612605247 ps
CPU time 43.77 seconds
Started May 21 03:04:47 PM PDT 24
Finished May 21 03:05:33 PM PDT 24
Peak memory 248784 kb
Host smart-49458c51-fb3f-478f-9ce0-4ce0d5d4a391
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1202472990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1202472990
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.525845033
Short name T677
Test name
Test status
Simulation time 898411950 ps
CPU time 24.86 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:05:13 PM PDT 24
Peak memory 247460 kb
Host smart-665303b1-93c6-4bbf-b64c-e10781c0550d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52584
5033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.525845033
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3339683171
Short name T490
Test name
Test status
Simulation time 1843109481 ps
CPU time 30.58 seconds
Started May 21 03:04:46 PM PDT 24
Finished May 21 03:05:19 PM PDT 24
Peak memory 255964 kb
Host smart-79f36997-5a01-4a0b-9cff-a7772b7a5d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33396
83171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3339683171
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.152191880
Short name T320
Test name
Test status
Simulation time 87569472951 ps
CPU time 1402.5 seconds
Started May 21 03:04:49 PM PDT 24
Finished May 21 03:28:13 PM PDT 24
Peak memory 272936 kb
Host smart-e96ee6c6-a628-40bf-9f58-d85194bb0524
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152191880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.152191880
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2021852309
Short name T40
Test name
Test status
Simulation time 37394743225 ps
CPU time 1130.33 seconds
Started May 21 03:04:50 PM PDT 24
Finished May 21 03:23:42 PM PDT 24
Peak memory 272876 kb
Host smart-8db3e997-c799-4693-972b-e030e22517b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021852309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2021852309
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3055699820
Short name T298
Test name
Test status
Simulation time 8162046729 ps
CPU time 83.49 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:06:12 PM PDT 24
Peak memory 248256 kb
Host smart-8a5eb0f8-c4d6-4973-926e-afc900684bc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055699820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3055699820
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3834061804
Short name T670
Test name
Test status
Simulation time 399743513 ps
CPU time 37.45 seconds
Started May 21 03:04:49 PM PDT 24
Finished May 21 03:05:28 PM PDT 24
Peak memory 248776 kb
Host smart-8c8c912e-ef25-490b-a7fc-538b6309777f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
61804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3834061804
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1978514822
Short name T92
Test name
Test status
Simulation time 432291483 ps
CPU time 39.49 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:05:28 PM PDT 24
Peak memory 247544 kb
Host smart-03de6c0b-c351-43ce-8eb3-55794976bdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19785
14822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1978514822
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4003454718
Short name T586
Test name
Test status
Simulation time 341243162 ps
CPU time 6.86 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:04:55 PM PDT 24
Peak memory 250920 kb
Host smart-6ba10ae1-c3d2-477b-a0e9-3af2646dbe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40034
54718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4003454718
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2296916835
Short name T447
Test name
Test status
Simulation time 1586309034 ps
CPU time 65.81 seconds
Started May 21 03:04:45 PM PDT 24
Finished May 21 03:05:54 PM PDT 24
Peak memory 248792 kb
Host smart-3cb016f5-b59c-42e2-8ba4-a7ba5b48c7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22969
16835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2296916835
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3867192779
Short name T51
Test name
Test status
Simulation time 17017400589 ps
CPU time 915.39 seconds
Started May 21 03:04:46 PM PDT 24
Finished May 21 03:20:04 PM PDT 24
Peak memory 268316 kb
Host smart-a62e060a-d7d2-4dd3-81a4-d0e7e3ee9ecd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867192779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3867192779
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3303895944
Short name T204
Test name
Test status
Simulation time 114333443 ps
CPU time 3.25 seconds
Started May 21 03:04:55 PM PDT 24
Finished May 21 03:05:00 PM PDT 24
Peak memory 248868 kb
Host smart-f8435872-5466-4a23-8b53-4fc79c0099c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3303895944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3303895944
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2919120192
Short name T404
Test name
Test status
Simulation time 44249448967 ps
CPU time 1295.81 seconds
Started May 21 03:04:53 PM PDT 24
Finished May 21 03:26:30 PM PDT 24
Peak memory 281580 kb
Host smart-546e4c76-21b8-4c87-849c-9a4280a06942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919120192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2919120192
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.90008547
Short name T554
Test name
Test status
Simulation time 439838905 ps
CPU time 12.27 seconds
Started May 21 03:04:52 PM PDT 24
Finished May 21 03:05:06 PM PDT 24
Peak memory 248756 kb
Host smart-22ae9ac6-5616-4585-b008-141708002717
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=90008547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.90008547
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3080397664
Short name T457
Test name
Test status
Simulation time 10126587121 ps
CPU time 246.85 seconds
Started May 21 03:04:55 PM PDT 24
Finished May 21 03:09:03 PM PDT 24
Peak memory 257020 kb
Host smart-20a2fb7e-7b0f-48d1-8b86-61990ab3c0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30803
97664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3080397664
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1012384033
Short name T86
Test name
Test status
Simulation time 62969959 ps
CPU time 10.31 seconds
Started May 21 03:04:52 PM PDT 24
Finished May 21 03:05:04 PM PDT 24
Peak memory 248804 kb
Host smart-8e84de45-b496-46ed-aada-c1e1f56ab9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
84033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1012384033
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.823755858
Short name T323
Test name
Test status
Simulation time 65744170891 ps
CPU time 1441.2 seconds
Started May 21 03:04:53 PM PDT 24
Finished May 21 03:28:55 PM PDT 24
Peak memory 283280 kb
Host smart-ee064f04-ed72-443c-bf81-30a6e32545c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823755858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.823755858
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2192119456
Short name T87
Test name
Test status
Simulation time 19146034983 ps
CPU time 769.83 seconds
Started May 21 03:04:51 PM PDT 24
Finished May 21 03:17:42 PM PDT 24
Peak memory 267352 kb
Host smart-4e2d84b7-213e-46e7-bc54-e3054b5327f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192119456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2192119456
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3941859968
Short name T685
Test name
Test status
Simulation time 11810224748 ps
CPU time 430.81 seconds
Started May 21 03:04:55 PM PDT 24
Finished May 21 03:12:08 PM PDT 24
Peak memory 247928 kb
Host smart-9d5584c4-0429-4cd7-84a8-80985494104d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941859968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3941859968
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3948626315
Short name T274
Test name
Test status
Simulation time 60478299 ps
CPU time 4.99 seconds
Started May 21 03:04:51 PM PDT 24
Finished May 21 03:04:57 PM PDT 24
Peak memory 240588 kb
Host smart-cedd361b-436a-4fb1-92c1-8d7774bfd9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486
26315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3948626315
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3927249995
Short name T573
Test name
Test status
Simulation time 422746111 ps
CPU time 21.47 seconds
Started May 21 03:04:49 PM PDT 24
Finished May 21 03:05:12 PM PDT 24
Peak memory 247620 kb
Host smart-155c3666-7230-4a11-8068-4070a2995813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
49995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3927249995
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.480071328
Short name T515
Test name
Test status
Simulation time 90383126 ps
CPU time 12.87 seconds
Started May 21 03:04:54 PM PDT 24
Finished May 21 03:05:09 PM PDT 24
Peak memory 253840 kb
Host smart-7465669a-6555-4529-914b-cf7d8dd0d27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48007
1328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.480071328
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3314439577
Short name T452
Test name
Test status
Simulation time 225601445 ps
CPU time 14.1 seconds
Started May 21 03:04:49 PM PDT 24
Finished May 21 03:05:05 PM PDT 24
Peak memory 248768 kb
Host smart-0440ded8-ecbb-42ca-9d7c-0b44f633eea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
39577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3314439577
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2747062042
Short name T48
Test name
Test status
Simulation time 17446856123 ps
CPU time 1708.7 seconds
Started May 21 03:04:55 PM PDT 24
Finished May 21 03:33:26 PM PDT 24
Peak memory 289720 kb
Host smart-9f885d7f-5d56-43da-af36-bdb26ac9ac3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747062042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2747062042
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.429449831
Short name T205
Test name
Test status
Simulation time 16042327 ps
CPU time 2.43 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:05:02 PM PDT 24
Peak memory 248936 kb
Host smart-509150ed-3df4-4449-9636-7d54a4bd2358
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429449831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.429449831
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.88258014
Short name T411
Test name
Test status
Simulation time 31841934830 ps
CPU time 1957.2 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:37:38 PM PDT 24
Peak memory 289348 kb
Host smart-fca484ff-ddb6-47cc-be69-a5c416d0af13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88258014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.88258014
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2087584464
Short name T417
Test name
Test status
Simulation time 3742123963 ps
CPU time 41.44 seconds
Started May 21 03:05:00 PM PDT 24
Finished May 21 03:05:45 PM PDT 24
Peak memory 248816 kb
Host smart-5e16539c-8ddd-45e0-86e1-fc6f5713a40d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2087584464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2087584464
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2543820025
Short name T589
Test name
Test status
Simulation time 566244485 ps
CPU time 48.92 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:05:51 PM PDT 24
Peak memory 256868 kb
Host smart-be0444b7-30aa-456b-b7df-8a41f1aafaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
20025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2543820025
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2909445560
Short name T376
Test name
Test status
Simulation time 183998043 ps
CPU time 26.19 seconds
Started May 21 03:04:55 PM PDT 24
Finished May 21 03:05:23 PM PDT 24
Peak memory 256064 kb
Host smart-8ab2f202-0d74-4011-9234-5a5d9ae78b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094
45560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2909445560
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.814514116
Short name T331
Test name
Test status
Simulation time 39391440989 ps
CPU time 2640.58 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:49:01 PM PDT 24
Peak memory 289776 kb
Host smart-8056102c-4b06-46d7-bf5a-3e59cb1e17ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814514116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.814514116
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.718222849
Short name T462
Test name
Test status
Simulation time 38241883554 ps
CPU time 2445.75 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:45:48 PM PDT 24
Peak memory 289604 kb
Host smart-93b7c447-01c7-4c49-9476-58726de079af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718222849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.718222849
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2941002316
Short name T489
Test name
Test status
Simulation time 60710221233 ps
CPU time 409.44 seconds
Started May 21 03:05:00 PM PDT 24
Finished May 21 03:11:53 PM PDT 24
Peak memory 247972 kb
Host smart-b0181f82-a003-4607-bdff-0333ebdcdf6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941002316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2941002316
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.315514424
Short name T483
Test name
Test status
Simulation time 891542743 ps
CPU time 36.93 seconds
Started May 21 03:04:53 PM PDT 24
Finished May 21 03:05:32 PM PDT 24
Peak memory 248776 kb
Host smart-ef5e92ca-ecfd-487e-b552-4d3475384ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551
4424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.315514424
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.836464123
Short name T396
Test name
Test status
Simulation time 98886423 ps
CPU time 8.42 seconds
Started May 21 03:04:52 PM PDT 24
Finished May 21 03:05:02 PM PDT 24
Peak memory 252404 kb
Host smart-035f5fc8-265b-4a78-a0ea-9b4d85b0c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83646
4123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.836464123
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3365012912
Short name T545
Test name
Test status
Simulation time 114021844 ps
CPU time 10.99 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:05:11 PM PDT 24
Peak memory 256124 kb
Host smart-dd5eff29-c590-445e-96f4-ff1077c2974a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33650
12912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3365012912
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4175795960
Short name T222
Test name
Test status
Simulation time 276531442 ps
CPU time 24.73 seconds
Started May 21 03:04:53 PM PDT 24
Finished May 21 03:05:19 PM PDT 24
Peak memory 256432 kb
Host smart-6083f413-d2ca-4abe-8af0-f7495a010be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41757
95960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4175795960
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.672739634
Short name T104
Test name
Test status
Simulation time 31768942832 ps
CPU time 506.75 seconds
Started May 21 03:04:58 PM PDT 24
Finished May 21 03:13:27 PM PDT 24
Peak memory 256984 kb
Host smart-cc546580-5c5b-44ec-b995-db1d81cd5fb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672739634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.672739634
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1470446289
Short name T453
Test name
Test status
Simulation time 26141071197 ps
CPU time 736.14 seconds
Started May 21 03:04:58 PM PDT 24
Finished May 21 03:17:17 PM PDT 24
Peak memory 289852 kb
Host smart-d831ec81-5dc5-4a7f-a503-1c9d83a4d116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470446289 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1470446289
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3599506723
Short name T201
Test name
Test status
Simulation time 77710902 ps
CPU time 3.91 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:05:06 PM PDT 24
Peak memory 248936 kb
Host smart-a336744f-cb5a-4b23-b92d-9e3168353e03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3599506723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3599506723
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1483524351
Short name T72
Test name
Test status
Simulation time 112372936912 ps
CPU time 1661.22 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:32:42 PM PDT 24
Peak memory 273436 kb
Host smart-468ecc31-ad2e-4cb4-bcc8-6f662da5fcbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483524351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1483524351
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1716048810
Short name T526
Test name
Test status
Simulation time 450109198 ps
CPU time 20.24 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:05:19 PM PDT 24
Peak memory 248796 kb
Host smart-b478849c-1dd7-4336-9953-c1a62ea1e32f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1716048810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1716048810
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.32997747
Short name T544
Test name
Test status
Simulation time 4727287156 ps
CPU time 66.99 seconds
Started May 21 03:04:58 PM PDT 24
Finished May 21 03:06:08 PM PDT 24
Peak memory 256996 kb
Host smart-541717dd-04a8-4cc2-a761-fa52ab8ec0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.32997747
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.483574425
Short name T454
Test name
Test status
Simulation time 760852810 ps
CPU time 52.26 seconds
Started May 21 03:05:03 PM PDT 24
Finished May 21 03:05:57 PM PDT 24
Peak memory 256076 kb
Host smart-7f69f59c-4ef0-44dc-bcc8-ad13675fa99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48357
4425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.483574425
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3408018919
Short name T219
Test name
Test status
Simulation time 44799214370 ps
CPU time 1338.99 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:27:22 PM PDT 24
Peak memory 265256 kb
Host smart-a3c46992-b1e6-4154-a97d-740bba73c12d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408018919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3408018919
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2733158293
Short name T101
Test name
Test status
Simulation time 20331140179 ps
CPU time 1212.85 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:25:12 PM PDT 24
Peak memory 273128 kb
Host smart-926d754f-0cdd-45e3-ba0a-0a190bee65ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733158293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2733158293
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2852142247
Short name T304
Test name
Test status
Simulation time 13718129298 ps
CPU time 546 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:14:08 PM PDT 24
Peak memory 248052 kb
Host smart-cfb21065-7c5d-49d9-8208-4ad90039631d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852142247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2852142247
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1082073785
Short name T397
Test name
Test status
Simulation time 889378747 ps
CPU time 13.16 seconds
Started May 21 03:04:58 PM PDT 24
Finished May 21 03:05:14 PM PDT 24
Peak memory 248776 kb
Host smart-af9fe00d-e961-4a71-8a1e-810d380af952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
73785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1082073785
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3341575664
Short name T45
Test name
Test status
Simulation time 3101919090 ps
CPU time 26.27 seconds
Started May 21 03:04:57 PM PDT 24
Finished May 21 03:05:26 PM PDT 24
Peak memory 248872 kb
Host smart-9e735ff6-cc62-4780-b9f8-9c39e8618d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33415
75664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3341575664
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.755435766
Short name T644
Test name
Test status
Simulation time 3329097518 ps
CPU time 43.71 seconds
Started May 21 03:04:56 PM PDT 24
Finished May 21 03:05:42 PM PDT 24
Peak memory 248880 kb
Host smart-f1907c82-6bf5-4dc1-984f-3eb49f80eb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75543
5766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.755435766
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2405287677
Short name T478
Test name
Test status
Simulation time 70799302 ps
CPU time 5.19 seconds
Started May 21 03:05:01 PM PDT 24
Finished May 21 03:05:09 PM PDT 24
Peak memory 240588 kb
Host smart-09babf11-9646-46f5-b73a-db2b92b41fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24052
87677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2405287677
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2007292120
Short name T259
Test name
Test status
Simulation time 242219875542 ps
CPU time 4392.12 seconds
Started May 21 03:05:00 PM PDT 24
Finished May 21 04:19:15 PM PDT 24
Peak memory 305556 kb
Host smart-801d91f2-c193-4372-9ab1-5b52955af864
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007292120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2007292120
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1541946295
Short name T251
Test name
Test status
Simulation time 83245821398 ps
CPU time 1365.78 seconds
Started May 21 03:04:59 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 286044 kb
Host smart-1efe888d-6eac-4178-b963-785d85e8cae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541946295 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1541946295
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1550546016
Short name T207
Test name
Test status
Simulation time 39230491 ps
CPU time 3.52 seconds
Started May 21 03:05:07 PM PDT 24
Finished May 21 03:05:13 PM PDT 24
Peak memory 248936 kb
Host smart-5b76c4b1-7337-4c92-ba50-2b0c2ac56670
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1550546016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1550546016
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2310480686
Short name T610
Test name
Test status
Simulation time 123930264283 ps
CPU time 1917.28 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:37:05 PM PDT 24
Peak memory 273376 kb
Host smart-276edf58-031a-4c89-b536-008e8714f93d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310480686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2310480686
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1051506582
Short name T698
Test name
Test status
Simulation time 107857012 ps
CPU time 6.91 seconds
Started May 21 03:05:05 PM PDT 24
Finished May 21 03:05:15 PM PDT 24
Peak memory 240576 kb
Host smart-429b1207-7d49-4eaa-a1f5-8d0dae8de880
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1051506582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1051506582
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3083836377
Short name T392
Test name
Test status
Simulation time 11813114253 ps
CPU time 311.63 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:10:20 PM PDT 24
Peak memory 256996 kb
Host smart-273b85a7-c449-4444-b5e0-1de538e35d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
36377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3083836377
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2929751279
Short name T563
Test name
Test status
Simulation time 1680525980 ps
CPU time 28.09 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:05:37 PM PDT 24
Peak memory 248772 kb
Host smart-e2265c55-0521-4ad3-b7aa-6ce2f80c2402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
51279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2929751279
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1442355668
Short name T4
Test name
Test status
Simulation time 68086880153 ps
CPU time 1273.36 seconds
Started May 21 03:05:05 PM PDT 24
Finished May 21 03:26:21 PM PDT 24
Peak memory 281620 kb
Host smart-2b9607c2-0bc7-4767-8b56-335e4ddfcdbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442355668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1442355668
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.442653022
Short name T692
Test name
Test status
Simulation time 31411303166 ps
CPU time 1826.86 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:35:36 PM PDT 24
Peak memory 289460 kb
Host smart-62276898-2ae0-46b2-aefe-67caaa581c21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442653022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.442653022
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2018073150
Short name T8
Test name
Test status
Simulation time 27119325209 ps
CPU time 285.35 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:09:54 PM PDT 24
Peak memory 247868 kb
Host smart-f415a13b-6d47-4f54-b802-7f851fce8224
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018073150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2018073150
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3313324113
Short name T492
Test name
Test status
Simulation time 185312558 ps
CPU time 6.66 seconds
Started May 21 03:05:05 PM PDT 24
Finished May 21 03:05:13 PM PDT 24
Peak memory 240560 kb
Host smart-515607a6-d1d4-4bf6-8ad4-e6b6cbb7cd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
24113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3313324113
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1798540036
Short name T491
Test name
Test status
Simulation time 535488354 ps
CPU time 44.9 seconds
Started May 21 03:05:07 PM PDT 24
Finished May 21 03:05:54 PM PDT 24
Peak memory 248556 kb
Host smart-fb4dc9da-0436-48b2-8c10-a8d5df0d0165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
40036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1798540036
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1102870730
Short name T246
Test name
Test status
Simulation time 830412498 ps
CPU time 50.89 seconds
Started May 21 03:05:05 PM PDT 24
Finished May 21 03:05:58 PM PDT 24
Peak memory 255344 kb
Host smart-2f432457-fa25-46b9-b8c0-c9cbea26f2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
70730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1102870730
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.848389437
Short name T588
Test name
Test status
Simulation time 165502608 ps
CPU time 10.96 seconds
Started May 21 03:05:04 PM PDT 24
Finished May 21 03:05:17 PM PDT 24
Peak memory 248812 kb
Host smart-2828444c-71fd-489d-92e9-5530fef80c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84838
9437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.848389437
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1867394648
Short name T29
Test name
Test status
Simulation time 93010220244 ps
CPU time 1322.33 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 269488 kb
Host smart-81206fc2-af2b-4e75-82de-11b657be646b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867394648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1867394648
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.787854947
Short name T231
Test name
Test status
Simulation time 28580427725 ps
CPU time 1785.2 seconds
Started May 21 03:05:06 PM PDT 24
Finished May 21 03:34:54 PM PDT 24
Peak memory 282284 kb
Host smart-512d6e7e-d5f9-4bd3-b447-332edc45aea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787854947 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.787854947
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%