Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	53099	1			T4	14		T9	10		T70	5
class_i[0x1]	57867	1			T20	395		T10	2		T49	7
class_i[0x2]	76260	1			T4	2760		T20	137		T9	5
class_i[0x3]	64434	1			T20	10		T10	1		T15	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63831	1			T4	714		T20	390		T9	7
alert[0x1]	64023	1			T4	669		T20	7		T9	5
alert[0x2]	60131	1			T4	726		T20	136		T10	2
alert[0x3]	63675	1			T4	665		T20	9		T9	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

251375

1

T4

2774

T20

542

T9

10

esc_ping_fail

285

1

T9

5

T10

2

T11

10

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63759	1			T4	714		T20	390		T9	5
esc_integrity_fail	alert[0x1]	63935	1			T4	669		T20	7		T9	3
esc_integrity_fail	alert[0x2]	60064	1			T4	726		T20	136		T10	1
esc_integrity_fail	alert[0x3]	63617	1			T4	665		T20	9		T9	2
esc_ping_fail	alert[0x0]	72	1			T9	2		T11	3		T117	1
esc_ping_fail	alert[0x1]	88	1			T9	2		T11	4		T140	2
esc_ping_fail	alert[0x2]	67	1			T10	1		T11	2		T117	1
esc_ping_fail	alert[0x3]	58	1			T9	1		T10	1		T11	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	53024	1			T4	14		T9	10		T70	5
esc_integrity_fail	class_i[0x1]	57828	1			T20	395		T10	2		T49	7
esc_integrity_fail	class_i[0x2]	76171	1			T4	2760		T20	137		T15	295
esc_integrity_fail	class_i[0x3]	64352	1			T20	10		T15	2		T49	3
esc_ping_fail	class_i[0x0]	75	1			T127	4		T230	9		T333	4
esc_ping_fail	class_i[0x1]	39	1			T230	1		T79	1		T336	1
esc_ping_fail	class_i[0x2]	89	1			T9	5		T10	1		T117	2
esc_ping_fail	class_i[0x3]	82	1			T10	1		T11	10		T127	1