Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	690202553	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	690202553	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	690202553	690030765	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	690202553	690030765	0	0
tb.dut.EdnKnownO_A	0	0	690202553	690030765	0	0
tb.dut.EscPKnownO_A	0	0	690202553	690030765	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	690202553	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	690202553	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	690202553	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	690202553	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	690202553	80	0	0
tb.dut.IrqAKnownO_A	0	0	690202553	690030765	0	0
tb.dut.IrqBKnownO_A	0	0	690202553	690030765	0	0
tb.dut.IrqCKnownO_A	0	0	690202553	690030765	0	0
tb.dut.IrqDKnownO_A	0	0	690202553	690030765	0	0
tb.dut.TlAReadyKnownO_A	0	0	690202553	690030765	0	0
tb.dut.TlDValidKnownO_A	0	0	690202553	690030765	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	713113257	3258860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	713113257	6562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	713113257	6422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	713113257	6253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	713113257	5364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	713113257	5252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	713113257	5047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	713113257	4818	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	713113257	6131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	713113257	5031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	713113257	5100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	713113257	5187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	713113257	6365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	713113257	6355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	713113257	6446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	713113257	6261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	713113257	5201	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	713113257	5411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	713113257	5287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	713113257	5401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	713113257	5978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	713113257	5154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	713113257	4812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	713113257	6566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	713113257	6261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	713113257	6408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	713113257	5036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	713113257	5134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	713113257	6430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	713113257	5031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	713113257	6408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	713113257	4880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	713113257	6436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	713113257	5337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	713113257	6511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	713113257	6509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	713113257	5360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	713113257	5287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	713113257	4712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	713113257	5388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	713113257	5218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	713113257	5186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	713113257	5014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	713113257	6419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	713113257	6293	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	713113257	7342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	713113257	6127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	713113257	4991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	713113257	5423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	713113257	5096	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	713113257	7281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	713113257	7489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	713113257	7360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	713113257	6181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	713113257	5018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	713113257	5261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	713113257	5024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	713113257	6434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	713113257	5419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	713113257	5401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	713113257	5161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	713113257	5289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	713113257	7327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	713113257	6294	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	713113257	6511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	713113257	5261	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	713113257	5092	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	713113257	5048	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	713113257	5225	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	713113257	5066	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	713113257	8713	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	713113257	5105	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	713113257	5241	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	713113257	6462	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	713113257	6101	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	713113257	5209	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	713113257	5024	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	713113257	6332	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	713113257	5036	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	690202553	2025	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	690202553	225567	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	690202553	348791182	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	690202553	274	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	690202553	826	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	690202553	50	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	690202553	419	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	689906150	262990694	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	690202553	916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	690202553	896	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	690202553	868	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	690202553	848	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	690202553	1281	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	690202553	152160	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	690202553	1170	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	690202553	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	690202553	1455	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	690202553	1215	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	689904891	689835172	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	690202553	690030765	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	690202553	3045	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	690202553	217936	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	690202553	355339044	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	690202553	301	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	690202553	516	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	690202553	32	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	690202553	229	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	689906150	253299749	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	690202553	590	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	690202553	584	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	690202553	569	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	690202553	562	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	690202553	655	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	690202553	73301	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	690202553	570	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	690202553	53	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	690202553	1433	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	690202553	1193	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	689904891	689835172	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	690202553	690030765	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	690202553	1912	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	690202553	194972	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	690202553	404909533	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	690202553	283	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	690202553	473	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	690202553	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	690202553	201	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	689906150	318344347	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	690202553	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	690202553	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	690202553	524	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	690202553	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	690202553	1513	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	690202553	177445	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	690202553	1444	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	690202553	51	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	690202553	1460	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	690202553	1220	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	689904891	689835172	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	690202553	690030765	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	690202553	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	690202553	6852	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	690202553	230307	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	690202553	351184375	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	690202553	269	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	690202553	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	690202553	20	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	690202553	233	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	689906150	277580484	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	690202553	611	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	690202553	599	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	690202553	592	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	690202553	582	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	690202553	814	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	690202553	106982	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	690202553	737	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	690202553	56	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	690202553	1428	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	690202553	1188	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	689904891	689835172	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	690202553	690030765	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	713113257	136959817	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	713113257	712415511	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	713113257	712415511	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	713113257	196175991	0	0
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