Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T6	1		T22	1		T29	1
class_index[0x1]	53	1			T49	1		T79	1		T29	1
class_index[0x2]	51	1			T4	1		T49	1		T76	1
class_index[0x3]	56	1			T79	2		T30	1		T54	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T4	1		T22	1		T79	2
intr_timeout_cnt[1]	48	1			T6	1		T49	1		T85	1
intr_timeout_cnt[2]	12	1			T49	1		T54	1		T87	1
intr_timeout_cnt[3]	13	1			T79	1		T86	1		T88	1
intr_timeout_cnt[4]	9	1			T54	1		T91	1		T61	1
intr_timeout_cnt[5]	3	1			T76	1		T54	1		T274	1
intr_timeout_cnt[6]	9	1			T86	1		T96	1		T120	1
intr_timeout_cnt[7]	5	1			T89	1		T90	1		T116	1
intr_timeout_cnt[8]	7	1			T29	1		T89	2		T90	1
intr_timeout_cnt[9]	5	1			T29	1		T275	1		T276	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0] , class_index[0x1]]	[intr_timeout_cnt[5]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T22	1		T52	1		T59	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T6	1		T89	2		T92	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T277	1		T123	1		T270	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T88	1		T94	1		T278	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T91	1		T61	1		T279	1
class_index[0x0]	intr_timeout_cnt[6]	5	1			T96	1		T120	1		T259	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T89	1		T90	1		T280	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T29	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T281	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T30	1		T23	1		T94	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T49	1		T89	1		T92	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T87	1		T259	1		T282	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T79	1		T93	1		T283	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T100	1		T284	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T86	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T116	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T62	1		T122	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T29	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T4	1		T52	1		T112	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T85	1		T89	1		T42	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T49	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	3	1			T86	1		T91	1		T286	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T287	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T76	1		T54	1		T274	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T288	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T268	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T89	1		T90	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	31	1			T79	2		T30	1		T128	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T89	1		T289	1		T290	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T54	1		T130	1		T277	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T94	1		T291	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T54	1		T292	1		T293	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T121	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T89	1		T120	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T275	1		T276	1		T122	1