Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354856	1			T1	875		T2	408		T3	37
all_values[1]	354856	1			T1	875		T2	408		T3	37
all_values[2]	354856	1			T1	875		T2	408		T3	37
all_values[3]	354856	1			T1	875		T2	408		T3	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704657

1

T1

1697

T2

847

T3

81

auto[1]

714767

1

T1

1803

T2

785

T3

67

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

846451

1

T1

1785

T2

865

T3

78

auto[1]

572973

1

T1

1715

T2

767

T3

70

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102572	1			T1	214		T2	101		T3	12
all_values[0]	auto[0]	auto[1]	73138	1			T1	210		T2	95		T3	11
all_values[0]	auto[1]	auto[0]	105303	1			T1	227		T2	113		T3	7
all_values[0]	auto[1]	auto[1]	73843	1			T1	224		T2	99		T3	7
all_values[1]	auto[0]	auto[0]	105248	1			T1	213		T2	111		T3	9
all_values[1]	auto[0]	auto[1]	71831	1			T1	198		T2	97		T3	9
all_values[1]	auto[1]	auto[0]	105816	1			T1	238		T2	107		T3	11
all_values[1]	auto[1]	auto[1]	71961	1			T1	226		T2	93		T3	8
all_values[2]	auto[0]	auto[0]	107339	1			T1	242		T2	117		T3	9
all_values[2]	auto[0]	auto[1]	68622	1			T1	221		T2	98		T3	9
all_values[2]	auto[1]	auto[0]	109648	1			T1	210		T2	101		T3	11
all_values[2]	auto[1]	auto[1]	69247	1			T1	202		T2	92		T3	8
all_values[3]	auto[0]	auto[0]	104263	1			T1	202		T2	121		T3	11
all_values[3]	auto[0]	auto[1]	71644	1			T1	197		T2	107		T3	11
all_values[3]	auto[1]	auto[0]	106262	1			T1	239		T2	94		T3	8
all_values[3]	auto[1]	auto[1]	72687	1			T1	237		T2	86		T3	7