Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	354856	1			T1	875		T2	408		T3	37
all_pins[1]	354856	1			T1	875		T2	408		T3	37
all_pins[2]	354856	1			T1	875		T2	408		T3	37
all_pins[3]	354856	1			T1	875		T2	408		T3	37

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1131686	1			T1	2611		T2	1262		T3	118
values[0x1]	287738	1			T1	889		T2	370		T3	30
transitions[0x0=>0x1]	191239	1			T1	561		T2	233		T3	22
transitions[0x1=>0x0]	191489	1			T1	562		T2	233		T3	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	281013	1			T1	651		T2	309		T3	30
all_pins[0]	values[0x1]	73843	1			T1	224		T2	99		T3	7
all_pins[0]	transitions[0x0=>0x1]	73229	1			T1	223		T2	99		T3	7
all_pins[0]	transitions[0x1=>0x0]	72323	1			T1	237		T2	86		T3	7
all_pins[1]	values[0x0]	282895	1			T1	649		T2	315		T3	29
all_pins[1]	values[0x1]	71961	1			T1	226		T2	93		T3	8
all_pins[1]	transitions[0x0=>0x1]	40051	1			T1	113		T2	42		T3	6
all_pins[1]	transitions[0x1=>0x0]	41933	1			T1	111		T2	48		T3	5
all_pins[2]	values[0x0]	285609	1			T1	673		T2	316		T3	29
all_pins[2]	values[0x1]	69247	1			T1	202		T2	92		T3	8
all_pins[2]	transitions[0x0=>0x1]	37477	1			T1	102		T2	46		T3	6
all_pins[2]	transitions[0x1=>0x0]	40191	1			T1	126		T2	47		T3	6
all_pins[3]	values[0x0]	282169	1			T1	638		T2	322		T3	30
all_pins[3]	values[0x1]	72687	1			T1	237		T2	86		T3	7
all_pins[3]	transitions[0x0=>0x1]	40482	1			T1	123		T2	46		T3	3
all_pins[3]	transitions[0x1=>0x0]	37042	1			T1	88		T2	52		T3	4