Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T183	4		T184	7		T185	4
all_values[1]	266	1			T183	4		T184	7		T185	4
all_values[2]	266	1			T183	4		T184	7		T185	4
all_values[3]	266	1			T183	4		T184	7		T185	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588

1

T183

9

T184

13

T185

9

auto[1]

476

1

T183

7

T184

15

T185

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

399

1

T183

3

T184

8

T185

6

auto[1]

665

1

T183

13

T184

20

T185

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T183

9

T184

14

T185

10

auto[1]

448

1

T183

7

T184

14

T185

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T183

1

T184

1

T366

3

all_values[0]

auto[0]

auto[0]

auto[1]

28

1

T183

1

T185

2

T367

1

all_values[0]

auto[0]

auto[1]

auto[0]

47

1

T184

2

T366

2

T368

3

all_values[0]

auto[0]

auto[1]

auto[1]

29

1

T183

1

T366

1

T369

1

all_values[0]

auto[1]

auto[0]

auto[1]

59

1

T183

1

T184

4

T185

1

all_values[0]

auto[1]

auto[1]

auto[1]

44

1

T185

1

T366

1

T368

1

all_values[1]

auto[0]

auto[0]

auto[0]

56

1

T184

1

T370

3

T371

1

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T366

1

T372

1

T370

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T183

1

T184

2

T185

2

all_values[1]

auto[0]

auto[1]

auto[1]

33

1

T183

1

T184

1

T185

1

all_values[1]

auto[1]

auto[0]

auto[1]

70

1

T183

1

T184

1

T185

1

all_values[1]

auto[1]

auto[1]

auto[1]

46

1

T183

1

T184

2

T368

2

all_values[2]

auto[0]

auto[0]

auto[0]

66

1

T184

1

T368

1

T372

2

all_values[2]

auto[0]

auto[0]

auto[1]

20

1

T183

1

T184

1

T185

1

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T185

1

T366

5

T370

1

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T184

2

T368

2

T370

1

all_values[2]

auto[1]

auto[0]

auto[1]

66

1

T183

3

T184

2

T185

1

all_values[2]

auto[1]

auto[1]

auto[1]

47

1

T184

1

T185

1

T366

1

all_values[3]

auto[0]

auto[0]

auto[0]

52

1

T185

2

T372

2

T371

1

all_values[3]

auto[0]

auto[0]

auto[1]

31

1

T184

1

T366

1

T370

1

all_values[3]

auto[0]

auto[1]

auto[0]

39

1

T183

1

T184

1

T185

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T183

2

T184

1

T366

2

all_values[3]

auto[1]

auto[0]

auto[1]

58

1

T183

1

T184

1

T185

1

all_values[3]

auto[1]

auto[1]

auto[1]

58

1

T184

3

T366

3

T368

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal