Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	109155	1			T1	61		T4	568		T16	641
accum_cnt_1000	239195	1			T1	540		T2	177		T4	1456
accum_cnt_100	26484	1			T1	32		T2	77		T4	134
accum_cnt_50	70365	1			T1	670		T2	300		T6	22
accum_cnt_10	173645	1			T1	30		T2	265		T6	32
accum_cnt_0	383267	1			T1	1327		T2	125		T3	144

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262297	1			T1	665		T2	236		T3	36
class_index[0x1]	262297	1			T1	665		T2	236		T3	36
class_index[0x2]	262297	1			T1	665		T2	236		T3	36
class_index[0x3]	262297	1			T1	665		T2	236		T3	36

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	30183	1			T1	61		T16	641		T18	111
class_index[0x0]	accum_cnt_1000	62733	1			T1	540		T2	89		T20	10
class_index[0x0]	accum_cnt_100	8522	1			T1	32		T2	39		T20	49
class_index[0x0]	accum_cnt_50	14496	1			T1	22		T2	37		T6	14
class_index[0x0]	accum_cnt_10	44981	1			T1	8		T2	58		T6	6
class_index[0x0]	accum_cnt_0	90079	1			T1	2		T2	13		T3	36
class_index[0x1]	accum_cnt_2000	25490	1			T4	224		T17	492		T79	628
class_index[0x1]	accum_cnt_1000	64035	1			T2	88		T4	566		T20	17
class_index[0x1]	accum_cnt_100	6785	1			T2	38		T4	48		T20	4
class_index[0x1]	accum_cnt_50	14376	1			T2	57		T4	35		T20	30
class_index[0x1]	accum_cnt_10	53341	1			T1	3		T2	37		T6	1
class_index[0x1]	accum_cnt_0	86330	1			T1	662		T2	16		T3	36
class_index[0x2]	accum_cnt_2000	25168	1			T4	258		T17	98		T18	11
class_index[0x2]	accum_cnt_1000	48464	1			T4	208		T20	26		T49	17
class_index[0x2]	accum_cnt_100	4737	1			T4	30		T20	20		T50	23
class_index[0x2]	accum_cnt_50	20904	1			T1	648		T2	15		T4	26
class_index[0x2]	accum_cnt_10	40778	1			T1	17		T2	154		T6	14
class_index[0x2]	accum_cnt_0	113403	1			T2	67		T3	36		T6	10
class_index[0x3]	accum_cnt_2000	28314	1			T4	86		T17	693		T51	627
class_index[0x3]	accum_cnt_1000	63963	1			T4	682		T8	1032		T17	693
class_index[0x3]	accum_cnt_100	6440	1			T4	56		T20	36		T8	168
class_index[0x3]	accum_cnt_50	20589	1			T2	191		T6	8		T4	52
class_index[0x3]	accum_cnt_10	34545	1			T1	2		T2	16		T6	11
class_index[0x3]	accum_cnt_0	93455	1			T1	663		T2	29		T3	36