Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5791	1			T4	79		T327	21		T52	892
alert[0x1]	6259	1			T9	1		T30	1		T113	212
alert[0x2]	5506	1			T15	1		T16	84		T11	1
alert[0x3]	8763	1			T16	343		T140	1		T118	244
alert[0x4]	11455	1			T4	103		T10	1		T16	6980
alert[0x5]	4789	1			T16	41		T140	1		T230	1
alert[0x6]	5172	1			T4	43		T16	350		T140	1
alert[0x7]	10863	1			T16	14		T140	1		T127	1
alert[0x8]	12867	1			T9	1		T15	6		T127	1
alert[0x9]	10322	1			T9	1		T30	6		T113	121
alert[0xa]	11288	1			T16	126		T30	6		T34	14
alert[0xb]	6492	1			T16	232		T127	1		T230	1
alert[0xc]	4775	1			T4	993		T16	88		T11	1
alert[0xd]	9579	1			T117	2		T113	53		T118	17
alert[0xe]	4317	1			T16	102		T11	1		T230	1
alert[0xf]	2772	1			T4	27		T34	8		T265	1
alert[0x10]	3752	1			T20	6		T11	1		T34	144
alert[0x11]	4266	1			T4	45		T11	1		T230	1
alert[0x12]	6359	1			T4	7		T15	4		T16	72
alert[0x13]	3174	1			T11	1		T140	1		T126	1
alert[0x14]	4141	1			T17	23		T26	7		T230	1
alert[0x15]	2931	1			T4	6		T16	328		T34	128
alert[0x16]	3693	1			T11	1		T127	1		T230	1
alert[0x17]	7199	1			T29	2		T30	8		T34	48
alert[0x18]	5997	1			T34	83		T113	7		T118	15
alert[0x19]	5987	1			T9	1		T220	1		T327	36
alert[0x1a]	8375	1			T4	26		T140	1		T26	1
alert[0x1b]	6578	1			T4	26		T20	2		T10	1
alert[0x1c]	2995	1			T4	76		T20	4		T16	156
alert[0x1d]	3394	1			T4	11		T10	1		T16	1
alert[0x1e]	2825	1			T4	20		T10	1		T16	61
alert[0x1f]	2718	1			T10	1		T29	1		T30	3
alert[0x20]	4948	1			T9	1		T16	187		T11	1
alert[0x21]	4167	1			T15	2		T117	1		T220	1
alert[0x22]	5551	1			T4	68		T9	1		T16	60
alert[0x23]	3522	1			T4	29		T16	565		T127	1
alert[0x24]	4470	1			T4	79		T113	101		T118	43
alert[0x25]	7070	1			T16	585		T11	1		T230	1
alert[0x26]	3438	1			T4	48		T117	1		T32	297
alert[0x27]	7894	1			T16	35		T11	1		T327	33
alert[0x28]	4770	1			T4	21		T16	37		T11	2
alert[0x29]	5552	1			T4	1448		T10	1		T15	3
alert[0x2a]	5716	1			T220	1		T30	4		T34	5
alert[0x2b]	2344	1			T9	2		T16	507		T34	81
alert[0x2c]	4173	1			T113	802		T327	37		T32	71
alert[0x2d]	11192	1			T15	12		T16	3593		T113	554
alert[0x2e]	7367	1			T4	55		T9	1		T16	41
alert[0x2f]	5518	1			T9	1		T16	39		T34	1915
alert[0x30]	3268	1			T15	13		T16	46		T117	1
alert[0x31]	12766	1			T9	1		T140	1		T26	17
alert[0x32]	9942	1			T9	1		T140	1		T89	8
alert[0x33]	6729	1			T4	31		T10	1		T16	393
alert[0x34]	9352	1			T4	32		T10	1		T140	1
alert[0x35]	2570	1			T4	4		T16	17		T30	4
alert[0x36]	7459	1			T4	187		T16	71		T140	1
alert[0x37]	4717	1			T4	29		T140	1		T113	449
alert[0x38]	5896	1			T4	25		T16	37		T11	1
alert[0x39]	4770	1			T15	1		T16	9		T113	12
alert[0x3a]	3733	1			T10	1		T15	3		T16	19
alert[0x3b]	2649	1			T4	30		T16	1		T11	1
alert[0x3c]	11626	1			T140	2		T34	263		T327	14
alert[0x3d]	6116	1			T127	1		T54	289		T90	7
alert[0x3e]	3839	1			T16	20		T140	2		T34	59
alert[0x3f]	4317	1			T4	16		T16	2023		T118	27
alert[0x40]	4081	1			T4	224		T16	234		T11	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	98367	1			T4	3788		T9	12		T15	16
class_i[0x1]	110466	1			T20	3		T10	1		T15	19
class_i[0x2]	96034	1			T20	9		T10	8		T11	1
class_i[0x3]	82049	1			T15	10		T16	10		T70	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

386223

1

T4

3788

T20

12

T15

45

alert_ping_fail

693

1

T9

12

T10

9

T11

18

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5784	1			T4	79		T327	21		T52	892
alert_integrity_fail	alert[0x1]	6251	1			T30	1		T113	212		T327	142
alert_integrity_fail	alert[0x2]	5496	1			T15	1		T16	84		T26	4
alert_integrity_fail	alert[0x3]	8757	1			T16	343		T118	244		T52	175
alert_integrity_fail	alert[0x4]	11444	1			T4	103		T16	6980		T34	450
alert_integrity_fail	alert[0x5]	4770	1			T16	41		T34	17		T118	362
alert_integrity_fail	alert[0x6]	5152	1			T4	43		T16	350		T29	3
alert_integrity_fail	alert[0x7]	10846	1			T16	14		T34	39		T118	280
alert_integrity_fail	alert[0x8]	12852	1			T15	6		T30	12		T327	5
alert_integrity_fail	alert[0x9]	10313	1			T30	6		T113	121		T327	1137
alert_integrity_fail	alert[0xa]	11270	1			T16	126		T30	6		T34	14
alert_integrity_fail	alert[0xb]	6485	1			T16	232		T118	73		T327	70
alert_integrity_fail	alert[0xc]	4768	1			T4	993		T16	88		T34	36
alert_integrity_fail	alert[0xd]	9569	1			T113	53		T118	17		T32	9
alert_integrity_fail	alert[0xe]	4311	1			T16	102		T34	128		T52	23
alert_integrity_fail	alert[0xf]	2763	1			T4	27		T34	8		T89	4
alert_integrity_fail	alert[0x10]	3743	1			T20	6		T34	144		T118	31
alert_integrity_fail	alert[0x11]	4258	1			T4	45		T118	205		T32	264
alert_integrity_fail	alert[0x12]	6352	1			T4	7		T15	4		T16	72
alert_integrity_fail	alert[0x13]	3161	1			T113	42		T118	15		T136	1383
alert_integrity_fail	alert[0x14]	4125	1			T17	23		T26	7		T34	782
alert_integrity_fail	alert[0x15]	2921	1			T4	6		T16	328		T34	128
alert_integrity_fail	alert[0x16]	3683	1			T29	2		T118	49		T327	4
alert_integrity_fail	alert[0x17]	7187	1			T29	2		T30	8		T34	48
alert_integrity_fail	alert[0x18]	5988	1			T34	83		T113	7		T118	15
alert_integrity_fail	alert[0x19]	5976	1			T327	36		T32	19		T52	468
alert_integrity_fail	alert[0x1a]	8366	1			T4	26		T26	1		T34	1452
alert_integrity_fail	alert[0x1b]	6568	1			T4	26		T20	2		T34	24
alert_integrity_fail	alert[0x1c]	2983	1			T4	76		T20	4		T16	156
alert_integrity_fail	alert[0x1d]	3384	1			T4	11		T16	1		T76	1
alert_integrity_fail	alert[0x1e]	2812	1			T4	20		T16	61		T113	146
alert_integrity_fail	alert[0x1f]	2708	1			T29	1		T30	3		T54	2
alert_integrity_fail	alert[0x20]	4935	1			T16	187		T118	63		T54	34
alert_integrity_fail	alert[0x21]	4155	1			T15	2		T34	39		T327	58
alert_integrity_fail	alert[0x22]	5535	1			T4	68		T16	60		T34	84
alert_integrity_fail	alert[0x23]	3512	1			T4	29		T16	565		T113	10
alert_integrity_fail	alert[0x24]	4467	1			T4	79		T113	101		T118	43
alert_integrity_fail	alert[0x25]	7060	1			T16	585		T34	131		T327	39
alert_integrity_fail	alert[0x26]	3428	1			T4	48		T32	297		T52	4
alert_integrity_fail	alert[0x27]	7887	1			T16	35		T327	33		T54	24
alert_integrity_fail	alert[0x28]	4751	1			T4	21		T16	37		T52	33
alert_integrity_fail	alert[0x29]	5540	1			T4	1448		T15	3		T113	25
alert_integrity_fail	alert[0x2a]	5703	1			T30	4		T34	5		T113	2381
alert_integrity_fail	alert[0x2b]	2330	1			T16	507		T34	81		T118	38
alert_integrity_fail	alert[0x2c]	4163	1			T113	802		T327	37		T32	71
alert_integrity_fail	alert[0x2d]	11180	1			T15	12		T16	3593		T113	554
alert_integrity_fail	alert[0x2e]	7354	1			T4	55		T16	41		T34	12
alert_integrity_fail	alert[0x2f]	5508	1			T16	39		T34	1915		T113	21
alert_integrity_fail	alert[0x30]	3260	1			T15	13		T16	46		T29	1
alert_integrity_fail	alert[0x31]	12752	1			T26	17		T34	78		T113	335
alert_integrity_fail	alert[0x32]	9936	1			T89	8		T328	66		T329	3
alert_integrity_fail	alert[0x33]	6714	1			T4	31		T16	393		T327	16
alert_integrity_fail	alert[0x34]	9340	1			T4	32		T118	257		T327	15
alert_integrity_fail	alert[0x35]	2563	1			T4	4		T16	17		T30	4
alert_integrity_fail	alert[0x36]	7449	1			T4	187		T16	71		T327	88
alert_integrity_fail	alert[0x37]	4705	1			T4	29		T113	449		T327	35
alert_integrity_fail	alert[0x38]	5891	1			T4	25		T16	37		T29	7
alert_integrity_fail	alert[0x39]	4759	1			T15	1		T16	9		T113	12
alert_integrity_fail	alert[0x3a]	3723	1			T15	3		T16	19		T34	346
alert_integrity_fail	alert[0x3b]	2639	1			T4	30		T16	1		T113	206
alert_integrity_fail	alert[0x3c]	11612	1			T34	263		T327	14		T52	24
alert_integrity_fail	alert[0x3d]	6107	1			T54	289		T90	7		T59	1
alert_integrity_fail	alert[0x3e]	3833	1			T16	20		T34	59		T113	5
alert_integrity_fail	alert[0x3f]	4313	1			T4	16		T16	2023		T118	27
alert_integrity_fail	alert[0x40]	4073	1			T4	224		T16	234		T34	62
alert_ping_fail	alert[0x0]	7	1			T265	1		T330	1		T331	1
alert_ping_fail	alert[0x1]	8	1			T9	1		T265	1		T332	1
alert_ping_fail	alert[0x2]	10	1			T11	1		T230	2		T333	1
alert_ping_fail	alert[0x3]	6	1			T140	1		T334	1		T211	1
alert_ping_fail	alert[0x4]	11	1			T10	1		T11	1		T220	1
alert_ping_fail	alert[0x5]	19	1			T140	1		T230	1		T265	1
alert_ping_fail	alert[0x6]	20	1			T140	1		T126	1		T303	1
alert_ping_fail	alert[0x7]	17	1			T140	1		T127	1		T220	1
alert_ping_fail	alert[0x8]	15	1			T9	1		T127	1		T220	1
alert_ping_fail	alert[0x9]	9	1			T9	1		T333	1		T335	1
alert_ping_fail	alert[0xa]	18	1			T324	1		T336	1		T337	1
alert_ping_fail	alert[0xb]	7	1			T127	1		T230	1		T220	1
alert_ping_fail	alert[0xc]	7	1			T11	1		T230	1		T338	1
alert_ping_fail	alert[0xd]	10	1			T117	2		T334	1		T339	1
alert_ping_fail	alert[0xe]	6	1			T11	1		T230	1		T340	1
alert_ping_fail	alert[0xf]	9	1			T265	1		T330	1		T340	1
alert_ping_fail	alert[0x10]	9	1			T11	1		T265	1		T339	1
alert_ping_fail	alert[0x11]	8	1			T11	1		T230	1		T335	1
alert_ping_fail	alert[0x12]	7	1			T334	1		T335	1		T330	1
alert_ping_fail	alert[0x13]	13	1			T11	1		T140	1		T126	1
alert_ping_fail	alert[0x14]	16	1			T230	1		T265	1		T341	3
alert_ping_fail	alert[0x15]	10	1			T265	1		T337	1		T320	1
alert_ping_fail	alert[0x16]	10	1			T11	1		T127	1		T230	1
alert_ping_fail	alert[0x17]	12	1			T333	2		T211	1		T342	1
alert_ping_fail	alert[0x18]	9	1			T332	1		T330	1		T343	1
alert_ping_fail	alert[0x19]	11	1			T9	1		T220	1		T334	1
alert_ping_fail	alert[0x1a]	9	1			T140	1		T337	1		T344	1
alert_ping_fail	alert[0x1b]	10	1			T10	1		T11	1		T140	1
alert_ping_fail	alert[0x1c]	12	1			T230	1		T340	2		T320	1
alert_ping_fail	alert[0x1d]	10	1			T10	1		T230	1		T335	1
alert_ping_fail	alert[0x1e]	13	1			T10	1		T140	1		T230	1
alert_ping_fail	alert[0x1f]	10	1			T10	1		T263	1		T334	1
alert_ping_fail	alert[0x20]	13	1			T9	1		T11	1		T265	1
alert_ping_fail	alert[0x21]	12	1			T117	1		T220	1		T303	1
alert_ping_fail	alert[0x22]	16	1			T9	1		T11	1		T333	1
alert_ping_fail	alert[0x23]	10	1			T127	1		T230	1		T336	1
alert_ping_fail	alert[0x24]	3	1			T345	1		T346	1		T347	1
alert_ping_fail	alert[0x25]	10	1			T11	1		T230	1		T332	1
alert_ping_fail	alert[0x26]	10	1			T117	1		T332	2		T348	1
alert_ping_fail	alert[0x27]	7	1			T11	1		T333	1		T331	1
alert_ping_fail	alert[0x28]	19	1			T11	2		T333	1		T334	1
alert_ping_fail	alert[0x29]	12	1			T10	1		T127	1		T220	2
alert_ping_fail	alert[0x2a]	13	1			T220	1		T334	1		T211	1
alert_ping_fail	alert[0x2b]	14	1			T9	2		T265	2		T337	1
alert_ping_fail	alert[0x2c]	10	1			T333	1		T339	2		T330	1
alert_ping_fail	alert[0x2d]	12	1			T324	1		T336	1		T337	1
alert_ping_fail	alert[0x2e]	13	1			T9	1		T220	1		T98	1
alert_ping_fail	alert[0x2f]	10	1			T9	1		T337	1		T331	1
alert_ping_fail	alert[0x30]	8	1			T117	1		T339	1		T349	2
alert_ping_fail	alert[0x31]	14	1			T9	1		T140	1		T331	1
alert_ping_fail	alert[0x32]	6	1			T9	1		T140	1		T335	1
alert_ping_fail	alert[0x33]	15	1			T10	1		T117	1		T140	1
alert_ping_fail	alert[0x34]	12	1			T10	1		T140	1		T265	2
alert_ping_fail	alert[0x35]	7	1			T334	1		T339	1		T350	1
alert_ping_fail	alert[0x36]	10	1			T140	1		T330	1		T331	1
alert_ping_fail	alert[0x37]	12	1			T140	1		T335	1		T339	1
alert_ping_fail	alert[0x38]	5	1			T11	1		T230	1		T265	1
alert_ping_fail	alert[0x39]	11	1			T211	1		T345	1		T348	1
alert_ping_fail	alert[0x3a]	10	1			T10	1		T127	1		T334	1
alert_ping_fail	alert[0x3b]	10	1			T11	1		T265	1		T320	1
alert_ping_fail	alert[0x3c]	14	1			T140	2		T265	1		T333	2
alert_ping_fail	alert[0x3d]	9	1			T127	1		T211	1		T348	1
alert_ping_fail	alert[0x3e]	6	1			T140	2		T337	1		T345	1
alert_ping_fail	alert[0x3f]	4	1			T265	1		T333	1		T339	1
alert_ping_fail	alert[0x40]	8	1			T11	1		T220	1		T334	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	98210	1			T4	3788		T15	16		T17	23
alert_integrity_fail	class_i[0x1]	110284	1			T20	3		T15	19		T16	17487
alert_integrity_fail	class_i[0x2]	95885	1			T20	9		T76	1		T29	3
alert_integrity_fail	class_i[0x3]	81844	1			T15	10		T16	10		T70	1
alert_ping_fail	class_i[0x0]	157	1			T9	12		T11	3		T127	6
alert_ping_fail	class_i[0x1]	182	1			T10	1		T117	1		T127	1
alert_ping_fail	class_i[0x2]	149	1			T10	8		T11	1		T117	3
alert_ping_fail	class_i[0x3]	205	1			T11	14		T117	2		T140	18