Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.67 99.97 100.00 100.00 99.38 99.52


Total test records in report: 826
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T771 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2398494149 May 23 03:45:28 PM PDT 24 May 23 03:45:51 PM PDT 24 7837685 ps
T772 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1815505857 May 23 03:44:14 PM PDT 24 May 23 03:44:31 PM PDT 24 61626443 ps
T773 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.433852548 May 23 03:44:46 PM PDT 24 May 23 03:45:42 PM PDT 24 662588091 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.785397426 May 23 03:44:36 PM PDT 24 May 23 03:45:03 PM PDT 24 211584698 ps
T168 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1696850079 May 23 03:44:12 PM PDT 24 May 23 03:55:49 PM PDT 24 13838032392 ps
T775 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1719449451 May 23 03:45:04 PM PDT 24 May 23 03:45:32 PM PDT 24 62651732 ps
T201 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.283746763 May 23 03:45:31 PM PDT 24 May 23 03:46:13 PM PDT 24 2142731254 ps
T776 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1848442531 May 23 03:45:31 PM PDT 24 May 23 03:45:54 PM PDT 24 14518602 ps
T166 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.582326294 May 23 03:45:21 PM PDT 24 May 23 03:51:07 PM PDT 24 5563486982 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3897783035 May 23 03:45:12 PM PDT 24 May 23 03:55:30 PM PDT 24 14899930700 ps
T777 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.169326045 May 23 03:45:37 PM PDT 24 May 23 03:46:05 PM PDT 24 10684493 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1624003842 May 23 03:44:28 PM PDT 24 May 23 03:48:56 PM PDT 24 13319604711 ps
T779 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4038669752 May 23 03:45:30 PM PDT 24 May 23 03:45:53 PM PDT 24 20055361 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3124761273 May 23 03:44:33 PM PDT 24 May 23 03:44:56 PM PDT 24 378098658 ps
T781 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1105167761 May 23 03:45:21 PM PDT 24 May 23 03:46:00 PM PDT 24 332866734 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.733618822 May 23 03:45:03 PM PDT 24 May 23 03:45:24 PM PDT 24 23990198 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2758177585 May 23 03:44:42 PM PDT 24 May 23 03:45:05 PM PDT 24 135037528 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3705381550 May 23 03:45:05 PM PDT 24 May 23 03:45:32 PM PDT 24 295248894 ps
T785 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2314719785 May 23 03:45:16 PM PDT 24 May 23 03:45:46 PM PDT 24 365123718 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.651793374 May 23 03:44:21 PM PDT 24 May 23 03:44:35 PM PDT 24 127489235 ps
T787 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1498040347 May 23 03:45:01 PM PDT 24 May 23 03:45:40 PM PDT 24 3223440335 ps
T171 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.203431894 May 23 03:45:03 PM PDT 24 May 23 03:49:20 PM PDT 24 4781907162 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4211007393 May 23 03:45:07 PM PDT 24 May 23 03:45:28 PM PDT 24 263013622 ps
T789 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1494318989 May 23 03:44:36 PM PDT 24 May 23 03:44:51 PM PDT 24 9300977 ps
T167 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2532600879 May 23 03:44:45 PM PDT 24 May 23 03:51:14 PM PDT 24 5664451410 ps
T175 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3477669483 May 23 03:44:45 PM PDT 24 May 23 03:50:22 PM PDT 24 8337630774 ps
T195 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2038547117 May 23 03:44:56 PM PDT 24 May 23 03:45:17 PM PDT 24 33258732 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.929262144 May 23 03:45:20 PM PDT 24 May 23 03:45:52 PM PDT 24 91101334 ps
T791 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3872916875 May 23 03:45:20 PM PDT 24 May 23 03:46:27 PM PDT 24 728466773 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1630349624 May 23 03:44:31 PM PDT 24 May 23 03:44:49 PM PDT 24 99212948 ps
T793 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2214423572 May 23 03:45:26 PM PDT 24 May 23 03:45:48 PM PDT 24 24036385 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1289811897 May 23 03:45:29 PM PDT 24 May 23 03:46:02 PM PDT 24 823380814 ps
T795 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1956929289 May 23 03:45:34 PM PDT 24 May 23 03:45:58 PM PDT 24 11966757 ps
T796 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3801449299 May 23 03:45:05 PM PDT 24 May 23 03:45:24 PM PDT 24 10157111 ps
T797 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.280697448 May 23 03:45:24 PM PDT 24 May 23 03:45:46 PM PDT 24 27152218 ps
T798 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.970050084 May 23 03:45:12 PM PDT 24 May 23 03:45:37 PM PDT 24 359993022 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3769595102 May 23 03:44:38 PM PDT 24 May 23 03:45:54 PM PDT 24 569825017 ps
T193 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3671384312 May 23 03:44:58 PM PDT 24 May 23 03:45:57 PM PDT 24 2392937379 ps
T800 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.601512748 May 23 03:45:29 PM PDT 24 May 23 03:45:53 PM PDT 24 10127553 ps
T165 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3181549966 May 23 03:45:10 PM PDT 24 May 23 03:58:48 PM PDT 24 18573933449 ps
T801 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1133911138 May 23 03:45:15 PM PDT 24 May 23 03:45:42 PM PDT 24 519967096 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2532107188 May 23 03:45:26 PM PDT 24 May 23 03:45:56 PM PDT 24 520739464 ps
T803 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.209863664 May 23 03:45:33 PM PDT 24 May 23 03:45:57 PM PDT 24 9047510 ps
T172 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3492941795 May 23 03:45:03 PM PDT 24 May 23 03:46:53 PM PDT 24 3091132136 ps
T804 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4205533834 May 23 03:45:33 PM PDT 24 May 23 03:45:57 PM PDT 24 24490373 ps
T177 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3217112688 May 23 03:44:34 PM PDT 24 May 23 03:47:10 PM PDT 24 3772158543 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.367093739 May 23 03:44:55 PM PDT 24 May 23 03:45:19 PM PDT 24 34914801 ps
T806 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2359716113 May 23 03:44:51 PM PDT 24 May 23 03:45:10 PM PDT 24 8121810 ps
T379 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1409717435 May 23 03:45:16 PM PDT 24 May 23 04:03:16 PM PDT 24 48347260888 ps
T807 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2685637044 May 23 03:44:37 PM PDT 24 May 23 03:45:00 PM PDT 24 247688256 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.346267393 May 23 03:44:24 PM PDT 24 May 23 03:44:37 PM PDT 24 33488035 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4288198595 May 23 03:45:23 PM PDT 24 May 23 03:45:48 PM PDT 24 24894281 ps
T810 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4284962026 May 23 03:44:34 PM PDT 24 May 23 03:44:50 PM PDT 24 73797960 ps
T811 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1919796225 May 23 03:45:31 PM PDT 24 May 23 03:45:54 PM PDT 24 15524854 ps
T164 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.112040251 May 23 03:45:07 PM PDT 24 May 23 03:48:24 PM PDT 24 2863924209 ps
T812 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2284349719 May 23 03:45:30 PM PDT 24 May 23 03:45:58 PM PDT 24 266879355 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2562791766 May 23 03:44:42 PM PDT 24 May 23 03:45:10 PM PDT 24 818329931 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4197694187 May 23 03:45:09 PM PDT 24 May 23 03:45:39 PM PDT 24 321760468 ps
T815 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1638242866 May 23 03:45:29 PM PDT 24 May 23 03:46:15 PM PDT 24 1562933307 ps
T188 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1459478415 May 23 03:45:04 PM PDT 24 May 23 03:45:55 PM PDT 24 2259139537 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2318081120 May 23 03:44:46 PM PDT 24 May 23 03:49:02 PM PDT 24 7122530349 ps
T174 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4268951730 May 23 03:44:57 PM PDT 24 May 23 03:47:19 PM PDT 24 1920727893 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.297614979 May 23 03:44:47 PM PDT 24 May 23 03:45:13 PM PDT 24 258395079 ps
T818 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.31447264 May 23 03:45:07 PM PDT 24 May 23 03:45:26 PM PDT 24 9815833 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1153877945 May 23 03:44:53 PM PDT 24 May 23 03:45:12 PM PDT 24 10131477 ps
T176 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2357481277 May 23 03:44:47 PM PDT 24 May 23 03:48:05 PM PDT 24 6565691030 ps
T820 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1464125439 May 23 03:44:46 PM PDT 24 May 23 03:45:12 PM PDT 24 185538660 ps
T179 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1786093633 May 23 03:45:18 PM PDT 24 May 23 03:49:32 PM PDT 24 3484707268 ps
T821 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1616444005 May 23 03:44:49 PM PDT 24 May 23 03:45:14 PM PDT 24 113207031 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.288758005 May 23 03:45:02 PM PDT 24 May 23 03:45:22 PM PDT 24 11343950 ps
T194 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3192926676 May 23 03:44:47 PM PDT 24 May 23 03:45:05 PM PDT 24 40239832 ps
T823 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1426876634 May 23 03:45:26 PM PDT 24 May 23 03:45:53 PM PDT 24 252003873 ps
T824 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3701713286 May 23 03:45:31 PM PDT 24 May 23 03:45:54 PM PDT 24 9837305 ps
T825 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2712919356 May 23 03:45:07 PM PDT 24 May 23 03:45:32 PM PDT 24 358372110 ps
T190 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3884663730 May 23 03:44:16 PM PDT 24 May 23 03:44:29 PM PDT 24 194107831 ps
T826 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1634677734 May 23 03:45:07 PM PDT 24 May 23 03:45:29 PM PDT 24 108847502 ps

Test location /workspace/coverage/default/44.alert_handler_stress_all.1569184762
Short name T4
Test name
Test status
Simulation time 52515826886 ps
CPU time 1254.07 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 02:59:39 PM PDT 24
Peak memory 286584 kb
Host smart-c3e51817-351d-49d9-a2c7-5825cbbd9209
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569184762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1569184762
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.884216218
Short name T12
Test name
Test status
Simulation time 1343183443 ps
CPU time 29.23 seconds
Started May 23 02:28:52 PM PDT 24
Finished May 23 02:29:22 PM PDT 24
Peak memory 270184 kb
Host smart-894a5bc0-d1f7-4133-82f0-8638d1a47fe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=884216218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.884216218
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3502134373
Short name T94
Test name
Test status
Simulation time 134314119044 ps
CPU time 8895.71 seconds
Started May 23 02:38:06 PM PDT 24
Finished May 23 05:06:23 PM PDT 24
Peak memory 338504 kb
Host smart-e8005332-675b-49ec-9e94-5417adfbf4b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502134373 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3502134373
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3160642435
Short name T16
Test name
Test status
Simulation time 186960961432 ps
CPU time 2849.46 seconds
Started May 23 02:32:56 PM PDT 24
Finished May 23 03:20:26 PM PDT 24
Peak memory 281624 kb
Host smart-9230d03c-b00a-4470-9b8c-a56ca8eedcb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160642435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3160642435
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1154393603
Short name T180
Test name
Test status
Simulation time 545404327 ps
CPU time 33.22 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 236772 kb
Host smart-cd92cc45-067f-46a2-9ea4-810b2297a68d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1154393603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1154393603
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3126586223
Short name T34
Test name
Test status
Simulation time 53445678647 ps
CPU time 1453.87 seconds
Started May 23 02:39:35 PM PDT 24
Finished May 23 03:03:50 PM PDT 24
Peak memory 288508 kb
Host smart-3f5542a5-4801-4b6b-89f9-b25f82addbc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126586223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3126586223
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3984414990
Short name T89
Test name
Test status
Simulation time 3231246821 ps
CPU time 423.15 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:43:11 PM PDT 24
Peak memory 256996 kb
Host smart-28282226-7a31-4b5b-9660-730ed4e1a563
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984414990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3984414990
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4005492454
Short name T23
Test name
Test status
Simulation time 11845956598 ps
CPU time 966.06 seconds
Started May 23 02:39:06 PM PDT 24
Finished May 23 02:55:12 PM PDT 24
Peak memory 273412 kb
Host smart-b065377d-8448-42a4-9401-13a1b61afac6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005492454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4005492454
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.759907901
Short name T126
Test name
Test status
Simulation time 48920440359 ps
CPU time 2932.95 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 03:22:55 PM PDT 24
Peak memory 281604 kb
Host smart-a6a65637-ce67-4ec8-931d-6917fb058471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759907901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.759907901
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2405910724
Short name T156
Test name
Test status
Simulation time 12899193232 ps
CPU time 715.94 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:56:57 PM PDT 24
Peak memory 265156 kb
Host smart-3fc37b3b-8592-4393-9d14-414059c58f53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405910724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2405910724
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3031437558
Short name T79
Test name
Test status
Simulation time 174775585239 ps
CPU time 2485.41 seconds
Started May 23 02:33:22 PM PDT 24
Finished May 23 03:14:48 PM PDT 24
Peak memory 289200 kb
Host smart-1465a5fa-8513-4aba-a33e-bfe147d29b1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031437558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3031437558
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2236679058
Short name T136
Test name
Test status
Simulation time 37054066036 ps
CPU time 2266.01 seconds
Started May 23 02:37:24 PM PDT 24
Finished May 23 03:15:11 PM PDT 24
Peak memory 289832 kb
Host smart-b0170017-5bab-4cff-ad98-62e451271283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236679058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2236679058
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2046787526
Short name T151
Test name
Test status
Simulation time 3569496448 ps
CPU time 200.6 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:48:11 PM PDT 24
Peak memory 264484 kb
Host smart-b89bb2c9-a0a5-4435-b12f-461aab2d2c3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2046787526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2046787526
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2866484005
Short name T150
Test name
Test status
Simulation time 12347729135 ps
CPU time 997.01 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 04:01:27 PM PDT 24
Peak memory 265252 kb
Host smart-5691ea55-a0fc-4051-968f-12e01c36284a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866484005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2866484005
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2838942913
Short name T96
Test name
Test status
Simulation time 395799177790 ps
CPU time 4372.14 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 305724 kb
Host smart-05c1f782-eb17-4106-991c-61ccf08b4175
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838942913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2838942913
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2113733060
Short name T122
Test name
Test status
Simulation time 44951528757 ps
CPU time 3063.2 seconds
Started May 23 02:37:11 PM PDT 24
Finished May 23 03:28:15 PM PDT 24
Peak memory 299696 kb
Host smart-e8a23652-bfff-4f46-b207-2c2b2ea40a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113733060 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2113733060
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3856520971
Short name T155
Test name
Test status
Simulation time 13945914261 ps
CPU time 664.26 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:56:36 PM PDT 24
Peak memory 265096 kb
Host smart-0320ce9a-4f15-4df0-ae36-27745447d3de
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856520971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3856520971
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3803142543
Short name T20
Test name
Test status
Simulation time 17374105229 ps
CPU time 1623.8 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 03:05:27 PM PDT 24
Peak memory 289544 kb
Host smart-7e599bfc-5d78-47b5-9d1a-7aad704ed541
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803142543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3803142543
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3420430127
Short name T354
Test name
Test status
Simulation time 187841466477 ps
CPU time 2585.27 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 03:13:33 PM PDT 24
Peak memory 280908 kb
Host smart-4b0c3edc-df25-47d4-a0cd-0a7fa848a0ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420430127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3420430127
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2001132901
Short name T11
Test name
Test status
Simulation time 12533078633 ps
CPU time 544.65 seconds
Started May 23 02:36:44 PM PDT 24
Finished May 23 02:45:49 PM PDT 24
Peak memory 256156 kb
Host smart-a7451731-7873-4cb2-abba-e8ab5ae69279
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001132901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2001132901
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.952479623
Short name T184
Test name
Test status
Simulation time 38321989 ps
CPU time 1.38 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:47 PM PDT 24
Peak memory 236568 kb
Host smart-05cd7a8e-12ee-4cf5-8562-1a00d78d98a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=952479623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.952479623
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2357481277
Short name T176
Test name
Test status
Simulation time 6565691030 ps
CPU time 182.45 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:48:05 PM PDT 24
Peak memory 266136 kb
Host smart-6c2d0460-b0c6-43ac-ab8c-dac250341d15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2357481277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2357481277
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.309460528
Short name T140
Test name
Test status
Simulation time 148035425978 ps
CPU time 470 seconds
Started May 23 02:33:54 PM PDT 24
Finished May 23 02:41:44 PM PDT 24
Peak memory 248200 kb
Host smart-d831110a-daa3-48c2-a5b6-bf41f4d10e9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309460528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.309460528
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4087136803
Short name T137
Test name
Test status
Simulation time 341910644221 ps
CPU time 2772.47 seconds
Started May 23 02:36:33 PM PDT 24
Finished May 23 03:22:46 PM PDT 24
Peak memory 289304 kb
Host smart-53039760-ef28-4240-a97a-9cfcd8f5261f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087136803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4087136803
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2135451931
Short name T154
Test name
Test status
Simulation time 7901825178 ps
CPU time 318.12 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:50:47 PM PDT 24
Peak memory 272576 kb
Host smart-35703c39-2316-4a0b-ab7e-9853ba958f94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135451931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2135451931
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2738066932
Short name T550
Test name
Test status
Simulation time 13939715642 ps
CPU time 546.84 seconds
Started May 23 02:31:46 PM PDT 24
Finished May 23 02:40:53 PM PDT 24
Peak memory 248036 kb
Host smart-f701e352-1a22-4118-a1c9-3d6e77ac2143
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738066932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2738066932
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.705700921
Short name T5
Test name
Test status
Simulation time 5191654871 ps
CPU time 58.82 seconds
Started May 23 02:31:56 PM PDT 24
Finished May 23 02:32:56 PM PDT 24
Peak memory 248832 kb
Host smart-329e53f2-b080-479d-8e93-732c9c1ec55d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=705700921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.705700921
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2619868380
Short name T158
Test name
Test status
Simulation time 3392883320 ps
CPU time 347.21 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:50:52 PM PDT 24
Peak memory 265112 kb
Host smart-4c4c6b6b-5d3c-43aa-a4b0-b16536a5738c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619868380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2619868380
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3108522297
Short name T54
Test name
Test status
Simulation time 59746808104 ps
CPU time 1839.02 seconds
Started May 23 02:31:56 PM PDT 24
Finished May 23 03:02:37 PM PDT 24
Peak memory 285952 kb
Host smart-9eee072b-fe3c-4277-b251-0ebd2a943e47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108522297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3108522297
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1534677532
Short name T146
Test name
Test status
Simulation time 26178781697 ps
CPU time 1085.38 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 04:03:48 PM PDT 24
Peak memory 265160 kb
Host smart-e46e387d-3d02-403b-b3cf-eb58ef3ff584
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534677532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1534677532
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.738458475
Short name T357
Test name
Test status
Simulation time 162993359296 ps
CPU time 2494.17 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 03:14:07 PM PDT 24
Peak memory 284244 kb
Host smart-f9864eb8-b48c-44fe-b9c5-0aeaad0cde29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738458475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.738458475
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2783638742
Short name T220
Test name
Test status
Simulation time 23124324023 ps
CPU time 245.55 seconds
Started May 23 02:29:01 PM PDT 24
Finished May 23 02:33:07 PM PDT 24
Peak memory 248068 kb
Host smart-0d0e8bc7-c126-4fe2-982b-c57a6afc85bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783638742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2783638742
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3907755856
Short name T348
Test name
Test status
Simulation time 51782525758 ps
CPU time 532.95 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:42:14 PM PDT 24
Peak memory 247112 kb
Host smart-4c4a321b-4e89-4f0d-800a-12bfda1c0297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907755856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3907755856
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3098777396
Short name T341
Test name
Test status
Simulation time 71963532701 ps
CPU time 2556.66 seconds
Started May 23 02:37:22 PM PDT 24
Finished May 23 03:20:00 PM PDT 24
Peak memory 289608 kb
Host smart-b16964c4-eade-4ba2-b276-e8486e64b106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098777396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3098777396
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3157786413
Short name T367
Test name
Test status
Simulation time 36432214 ps
CPU time 1.51 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 235648 kb
Host smart-95e9fd29-0461-4c57-83f0-b58d839306bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157786413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3157786413
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2025205433
Short name T29
Test name
Test status
Simulation time 40641374111 ps
CPU time 379.43 seconds
Started May 23 02:32:20 PM PDT 24
Finished May 23 02:38:40 PM PDT 24
Peak memory 256988 kb
Host smart-3b3de2e5-5978-4a00-8332-20d78f621580
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025205433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2025205433
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4275853852
Short name T142
Test name
Test status
Simulation time 10648227915 ps
CPU time 81.66 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 256928 kb
Host smart-182ca678-3630-4593-8dea-cc6ae29fdebe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4275853852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4275853852
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2525412885
Short name T355
Test name
Test status
Simulation time 74398135731 ps
CPU time 1590.04 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 03:05:39 PM PDT 24
Peak memory 288896 kb
Host smart-8716e5fa-70c0-43fe-beb7-440fb2a5e4f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525412885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2525412885
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1409717435
Short name T379
Test name
Test status
Simulation time 48347260888 ps
CPU time 1061.36 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 04:03:16 PM PDT 24
Peak memory 265268 kb
Host smart-3be49489-f9b9-4980-bc27-dafc902d0219
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409717435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1409717435
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2707897140
Short name T186
Test name
Test status
Simulation time 2706271477 ps
CPU time 37.98 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 239416 kb
Host smart-4384554b-b08d-408a-b5fd-5cf09d372507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2707897140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2707897140
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3595006758
Short name T222
Test name
Test status
Simulation time 6643098495 ps
CPU time 138.97 seconds
Started May 23 02:29:49 PM PDT 24
Finished May 23 02:32:09 PM PDT 24
Peak memory 256964 kb
Host smart-ce1c1915-3da3-408a-871e-f0d8edd90cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
06758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3595006758
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1300481658
Short name T149
Test name
Test status
Simulation time 15812085256 ps
CPU time 312.22 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:50:50 PM PDT 24
Peak memory 265124 kb
Host smart-70561eb7-fc5d-4b1d-b885-220394921339
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1300481658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1300481658
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.409810665
Short name T333
Test name
Test status
Simulation time 19187336924 ps
CPU time 395.67 seconds
Started May 23 02:35:16 PM PDT 24
Finished May 23 02:41:52 PM PDT 24
Peak memory 248092 kb
Host smart-98a6e80c-8f0a-43a6-9136-1ecf8734fab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409810665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.409810665
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1480535384
Short name T347
Test name
Test status
Simulation time 30249693494 ps
CPU time 630.89 seconds
Started May 23 02:31:07 PM PDT 24
Finished May 23 02:41:39 PM PDT 24
Peak memory 254664 kb
Host smart-c573466d-9781-4e49-9227-de27f81dadbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480535384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1480535384
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3267267172
Short name T318
Test name
Test status
Simulation time 15914271952 ps
CPU time 672.95 seconds
Started May 23 02:32:43 PM PDT 24
Finished May 23 02:43:57 PM PDT 24
Peak memory 265252 kb
Host smart-f0077d7e-5b5d-4599-9968-0151bae033e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267267172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3267267172
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.963717001
Short name T91
Test name
Test status
Simulation time 89517205623 ps
CPU time 1740.58 seconds
Started May 23 02:30:39 PM PDT 24
Finished May 23 02:59:41 PM PDT 24
Peak memory 301592 kb
Host smart-949323ed-b084-4911-ad1c-85d2bd9be178
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963717001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.963717001
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3126285718
Short name T148
Test name
Test status
Simulation time 8905657302 ps
CPU time 307.23 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:49:33 PM PDT 24
Peak memory 265084 kb
Host smart-71d2e0b2-7634-4dcd-95c3-93ff37ce349c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3126285718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3126285718
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3519595964
Short name T191
Test name
Test status
Simulation time 111686727 ps
CPU time 2.72 seconds
Started May 23 03:45:23 PM PDT 24
Finished May 23 03:45:47 PM PDT 24
Peak memory 236592 kb
Host smart-946f12b3-c4fc-4755-b566-0f4dde8da69a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3519595964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3519595964
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.740289305
Short name T247
Test name
Test status
Simulation time 277837176 ps
CPU time 2.52 seconds
Started May 23 02:28:24 PM PDT 24
Finished May 23 02:28:27 PM PDT 24
Peak memory 248952 kb
Host smart-aa7a9ac6-a99d-4589-9c22-a0fe5faae74e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=740289305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.740289305
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2204968078
Short name T242
Test name
Test status
Simulation time 184482238 ps
CPU time 4.52 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 02:31:32 PM PDT 24
Peak memory 248916 kb
Host smart-c6d391a8-2c79-4f2e-aab5-a4f067e6ff25
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2204968078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2204968078
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2660133263
Short name T235
Test name
Test status
Simulation time 114156774 ps
CPU time 3.31 seconds
Started May 23 02:31:58 PM PDT 24
Finished May 23 02:32:02 PM PDT 24
Peak memory 248940 kb
Host smart-a10b3a54-2a69-463b-ae7b-11bb256bc8af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2660133263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2660133263
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1385723140
Short name T246
Test name
Test status
Simulation time 79030751 ps
CPU time 3.57 seconds
Started May 23 02:32:25 PM PDT 24
Finished May 23 02:32:29 PM PDT 24
Peak memory 248920 kb
Host smart-432fb96c-85e0-4e2d-9f24-7701908b8c17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1385723140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1385723140
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.613139055
Short name T112
Test name
Test status
Simulation time 1200163098 ps
CPU time 42.59 seconds
Started May 23 02:31:44 PM PDT 24
Finished May 23 02:32:27 PM PDT 24
Peak memory 256128 kb
Host smart-3e69de2f-d5b6-4cab-aa85-2528cc466d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61313
9055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.613139055
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2863774107
Short name T270
Test name
Test status
Simulation time 208115924798 ps
CPU time 3227.66 seconds
Started May 23 02:38:20 PM PDT 24
Finished May 23 03:32:09 PM PDT 24
Peak memory 306016 kb
Host smart-e776d67b-ec34-4ae4-a5a5-db5c82522a67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863774107 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2863774107
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.721258833
Short name T121
Test name
Test status
Simulation time 16187734198 ps
CPU time 1636.19 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:58:09 PM PDT 24
Peak memory 305708 kb
Host smart-d60d24c5-9bd5-4569-9f82-247464709a50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721258833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.721258833
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.269188420
Short name T30
Test name
Test status
Simulation time 11967225371 ps
CPU time 1297.71 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 03:00:35 PM PDT 24
Peak memory 289460 kb
Host smart-53bc3643-38c5-49d9-9ade-f3e71a435b10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269188420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.269188420
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3477669483
Short name T175
Test name
Test status
Simulation time 8337630774 ps
CPU time 321.82 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:50:22 PM PDT 24
Peak memory 273048 kb
Host smart-48b20053-b138-4bc2-8446-8e9c2d01ebeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477669483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3477669483
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.203431894
Short name T171
Test name
Test status
Simulation time 4781907162 ps
CPU time 239.19 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:49:20 PM PDT 24
Peak memory 265128 kb
Host smart-8d2c213a-11d1-4a57-b465-2a02d3602f9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=203431894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.203431894
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3314758492
Short name T8
Test name
Test status
Simulation time 104748029544 ps
CPU time 3253.18 seconds
Started May 23 02:38:06 PM PDT 24
Finished May 23 03:32:20 PM PDT 24
Peak memory 288224 kb
Host smart-60f900e8-df64-4656-ace9-e9e1d0dba143
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314758492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3314758492
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1064393978
Short name T104
Test name
Test status
Simulation time 18338110076 ps
CPU time 1536.11 seconds
Started May 23 02:28:39 PM PDT 24
Finished May 23 02:54:15 PM PDT 24
Peak memory 288792 kb
Host smart-586cd71d-db61-44c6-ab05-c6e68805e478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064393978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1064393978
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.817286289
Short name T605
Test name
Test status
Simulation time 81411565465 ps
CPU time 2464.51 seconds
Started May 23 02:28:36 PM PDT 24
Finished May 23 03:09:41 PM PDT 24
Peak memory 289060 kb
Host smart-0ca768de-3e68-478b-9a9a-0b2b8c326ee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817286289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.817286289
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3425571831
Short name T587
Test name
Test status
Simulation time 61283742266 ps
CPU time 620.25 seconds
Started May 23 02:31:16 PM PDT 24
Finished May 23 02:41:37 PM PDT 24
Peak memory 248252 kb
Host smart-c36361b9-3e92-4cd7-bd10-8a746f67f3dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425571831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3425571831
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.106309078
Short name T646
Test name
Test status
Simulation time 215071167 ps
CPU time 25.89 seconds
Started May 23 02:31:06 PM PDT 24
Finished May 23 02:31:32 PM PDT 24
Peak memory 256768 kb
Host smart-10f5f570-1273-41a2-8453-7125f1176e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
9078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.106309078
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3189982465
Short name T288
Test name
Test status
Simulation time 173072316402 ps
CPU time 4851.31 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 03:52:20 PM PDT 24
Peak memory 330784 kb
Host smart-ef561e3d-fb51-4907-b6cd-17b796655ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189982465 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3189982465
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.927669413
Short name T116
Test name
Test status
Simulation time 22242849361 ps
CPU time 2192.84 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 03:08:01 PM PDT 24
Peak memory 298156 kb
Host smart-f9d1724e-2fed-47a2-b2c3-a7a5488c01db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927669413 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.927669413
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2858021777
Short name T268
Test name
Test status
Simulation time 10291454442 ps
CPU time 666.47 seconds
Started May 23 02:32:21 PM PDT 24
Finished May 23 02:43:28 PM PDT 24
Peak memory 266336 kb
Host smart-725bdefa-4a68-42c5-95c3-dbe9548762c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858021777 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2858021777
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3479713670
Short name T86
Test name
Test status
Simulation time 581102324 ps
CPU time 42.39 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:33:03 PM PDT 24
Peak memory 247424 kb
Host smart-e7c65534-b0b8-4614-8007-7b30f41865d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34797
13670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3479713670
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1404161732
Short name T351
Test name
Test status
Simulation time 204947014546 ps
CPU time 3155.6 seconds
Started May 23 02:32:54 PM PDT 24
Finished May 23 03:25:31 PM PDT 24
Peak memory 281612 kb
Host smart-d025e503-b7f6-421d-a68b-fb0bb00a94b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404161732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1404161732
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2906879344
Short name T287
Test name
Test status
Simulation time 182324661071 ps
CPU time 1180.36 seconds
Started May 23 02:29:00 PM PDT 24
Finished May 23 02:48:42 PM PDT 24
Peak memory 289836 kb
Host smart-a07e9ed6-01ba-401b-8859-9d994af4f14f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906879344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2906879344
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2157338853
Short name T286
Test name
Test status
Simulation time 57889620133 ps
CPU time 1595.25 seconds
Started May 23 02:33:33 PM PDT 24
Finished May 23 03:00:09 PM PDT 24
Peak memory 289244 kb
Host smart-93c92159-9acd-4591-8d0a-a72dc5b698dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157338853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2157338853
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3687277175
Short name T681
Test name
Test status
Simulation time 422119533 ps
CPU time 27.62 seconds
Started May 23 02:34:55 PM PDT 24
Finished May 23 02:35:24 PM PDT 24
Peak memory 255608 kb
Host smart-2a4c192f-c1dc-421a-b93d-e6cc7f0fd6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
77175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3687277175
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.258539062
Short name T308
Test name
Test status
Simulation time 12823024851 ps
CPU time 1183.25 seconds
Started May 23 02:35:38 PM PDT 24
Finished May 23 02:55:22 PM PDT 24
Peak memory 289384 kb
Host smart-cb8d0a81-be66-42cb-8e4a-f572f2b7b73b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258539062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.258539062
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1882098285
Short name T49
Test name
Test status
Simulation time 244832841 ps
CPU time 26.32 seconds
Started May 23 02:36:44 PM PDT 24
Finished May 23 02:37:11 PM PDT 24
Peak memory 255964 kb
Host smart-670deb84-2a61-4b32-8549-390cef1250f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
98285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1882098285
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1911115580
Short name T281
Test name
Test status
Simulation time 14578190504 ps
CPU time 1030.19 seconds
Started May 23 02:38:42 PM PDT 24
Finished May 23 02:55:52 PM PDT 24
Peak memory 265444 kb
Host smart-340762a0-2415-4f40-a79c-7b13f0d640b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911115580 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1911115580
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3288249153
Short name T100
Test name
Test status
Simulation time 295114349 ps
CPU time 15.72 seconds
Started May 23 02:39:34 PM PDT 24
Finished May 23 02:39:50 PM PDT 24
Peak memory 255604 kb
Host smart-d8c741b7-a05a-46af-bf0a-453d424e9d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32882
49153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3288249153
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3459782667
Short name T314
Test name
Test status
Simulation time 35998991790 ps
CPU time 2031.82 seconds
Started May 23 02:39:51 PM PDT 24
Finished May 23 03:13:43 PM PDT 24
Peak memory 287236 kb
Host smart-f2d8254d-3841-4aec-a461-e81990d588ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459782667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3459782667
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3799958079
Short name T13
Test name
Test status
Simulation time 693226843 ps
CPU time 25.19 seconds
Started May 23 02:28:25 PM PDT 24
Finished May 23 02:28:50 PM PDT 24
Peak memory 278784 kb
Host smart-fee4fcf2-5328-4b9a-8963-e5bd41a3a14e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3799958079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3799958079
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3275837327
Short name T162
Test name
Test status
Simulation time 12859847200 ps
CPU time 1099.43 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 04:03:39 PM PDT 24
Peak memory 271612 kb
Host smart-867da7e4-e788-48ae-9174-010061c67128
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275837327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3275837327
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3671384312
Short name T193
Test name
Test status
Simulation time 2392937379 ps
CPU time 40.69 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 240192 kb
Host smart-66d61e84-953f-40c2-8126-872710c293dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3671384312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3671384312
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2532600879
Short name T167
Test name
Test status
Simulation time 5664451410 ps
CPU time 373.23 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:51:14 PM PDT 24
Peak memory 265288 kb
Host smart-1f985242-4e47-4e50-9a26-092cf16043eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2532600879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2532600879
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2038547117
Short name T195
Test name
Test status
Simulation time 33258732 ps
CPU time 2.23 seconds
Started May 23 03:44:56 PM PDT 24
Finished May 23 03:45:17 PM PDT 24
Peak memory 236544 kb
Host smart-c47e9362-74cf-4b04-9d02-58d6a24e4160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2038547117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2038547117
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3192926676
Short name T194
Test name
Test status
Simulation time 40239832 ps
CPU time 2.12 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 236816 kb
Host smart-930882ae-d175-4da1-93ac-ceee1c8f8208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3192926676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3192926676
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3884663730
Short name T190
Test name
Test status
Simulation time 194107831 ps
CPU time 3.89 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 236640 kb
Host smart-6f2f200b-ae85-45e1-a804-bc0b3a3c75aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3884663730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3884663730
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1483452362
Short name T189
Test name
Test status
Simulation time 50280134 ps
CPU time 2.6 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:41 PM PDT 24
Peak memory 236808 kb
Host smart-e211a92a-01c8-4476-8d75-d8c6785bcbae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1483452362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1483452362
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3207203182
Short name T196
Test name
Test status
Simulation time 1207041338 ps
CPU time 40.28 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 239464 kb
Host smart-2e8c8361-6d60-4329-86c2-d2a2661a5ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3207203182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3207203182
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.410808086
Short name T192
Test name
Test status
Simulation time 33923920 ps
CPU time 2.4 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:19 PM PDT 24
Peak memory 236868 kb
Host smart-b2d48214-4a33-470d-ac85-7f98b243648d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=410808086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.410808086
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1647357783
Short name T202
Test name
Test status
Simulation time 1845594631 ps
CPU time 33.29 seconds
Started May 23 03:45:13 PM PDT 24
Finished May 23 03:46:04 PM PDT 24
Peak memory 236648 kb
Host smart-a4cdd26c-8859-4597-9c44-a706086ec232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647357783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1647357783
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1459478415
Short name T188
Test name
Test status
Simulation time 2259139537 ps
CPU time 33.49 seconds
Started May 23 03:45:04 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 236960 kb
Host smart-7366432c-61ac-4f87-ad33-a44e9f36e02c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1459478415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1459478415
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.133720545
Short name T203
Test name
Test status
Simulation time 219308433 ps
CPU time 4.05 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 236896 kb
Host smart-6755ec32-363b-43f1-a123-2b561f52e792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=133720545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.133720545
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2203339251
Short name T187
Test name
Test status
Simulation time 511277215 ps
CPU time 2.43 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:31 PM PDT 24
Peak memory 236984 kb
Host smart-a121ad02-395b-4543-a880-768dad74c96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2203339251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2203339251
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.283746763
Short name T201
Test name
Test status
Simulation time 2142731254 ps
CPU time 19.53 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:46:13 PM PDT 24
Peak memory 240092 kb
Host smart-49e44c89-2a5a-4630-872d-d26f3f8e595d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=283746763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.283746763
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3209573212
Short name T182
Test name
Test status
Simulation time 22506847 ps
CPU time 2.37 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236852 kb
Host smart-8b2c29ca-9323-4ea9-a7dc-a686257482fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3209573212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3209573212
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2077327107
Short name T181
Test name
Test status
Simulation time 302242329 ps
CPU time 19.48 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 236048 kb
Host smart-1301aec4-952a-475e-9ef2-bd4d6e0f7267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2077327107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2077327107
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.297948574
Short name T25
Test name
Test status
Simulation time 3515496938 ps
CPU time 73.76 seconds
Started May 23 02:30:04 PM PDT 24
Finished May 23 02:31:18 PM PDT 24
Peak memory 255552 kb
Host smart-0224cf3b-8233-4141-a707-1d674423288e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29794
8574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.297948574
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1624003842
Short name T778
Test name
Test status
Simulation time 13319604711 ps
CPU time 257.35 seconds
Started May 23 03:44:28 PM PDT 24
Finished May 23 03:48:56 PM PDT 24
Peak memory 240144 kb
Host smart-8af007d5-5e3a-42e0-911a-fcdbf9e398f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1624003842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1624003842
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3522045586
Short name T199
Test name
Test status
Simulation time 7577919031 ps
CPU time 215.4 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:48:20 PM PDT 24
Peak memory 240188 kb
Host smart-ada2f25c-26d5-417e-8f0e-7a9905ce1008
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3522045586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3522045586
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3244324721
Short name T216
Test name
Test status
Simulation time 55702454 ps
CPU time 5.26 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 240072 kb
Host smart-0f918180-77c7-41d1-b60a-383ce688eb54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3244324721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3244324721
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.651793374
Short name T786
Test name
Test status
Simulation time 127489235 ps
CPU time 4.49 seconds
Started May 23 03:44:21 PM PDT 24
Finished May 23 03:44:35 PM PDT 24
Peak memory 256356 kb
Host smart-4d2a5d5a-95a7-41aa-bab6-9cf21eadd1c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651793374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.651793374
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.620814748
Short name T762
Test name
Test status
Simulation time 213303207 ps
CPU time 4.64 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 235612 kb
Host smart-fbfb8bf0-d425-4e5e-9a8d-8b413a423880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=620814748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.620814748
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3521850335
Short name T747
Test name
Test status
Simulation time 20181243 ps
CPU time 1.46 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:48 PM PDT 24
Peak memory 235672 kb
Host smart-6e3e9a85-e48b-4f0d-a82c-9069556c0f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3521850335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3521850335
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1906386354
Short name T727
Test name
Test status
Simulation time 590860572 ps
CPU time 38.48 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 243844 kb
Host smart-6f2bed5a-e022-49e5-a0a9-dbb25eca0a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1906386354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1906386354
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1696850079
Short name T168
Test name
Test status
Simulation time 13838032392 ps
CPU time 690.76 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:55:49 PM PDT 24
Peak memory 273224 kb
Host smart-bfad45d4-5a88-43c8-b4e8-05e856291d71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696850079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1696850079
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3047623596
Short name T711
Test name
Test status
Simulation time 51186791 ps
CPU time 6.43 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 248376 kb
Host smart-43cb4904-f8b7-4e7d-a0f6-a437186b7b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3047623596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3047623596
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1536419435
Short name T740
Test name
Test status
Simulation time 2146499870 ps
CPU time 137.36 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 240156 kb
Host smart-115eb989-6643-4699-9b4b-d869bf64c5f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1536419435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1536419435
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.572046308
Short name T737
Test name
Test status
Simulation time 3269260267 ps
CPU time 206.44 seconds
Started May 23 03:44:24 PM PDT 24
Finished May 23 03:48:00 PM PDT 24
Peak memory 240088 kb
Host smart-29e0c77b-9be9-4039-93ec-9f720d62f018
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=572046308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.572046308
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1630349624
Short name T792
Test name
Test status
Simulation time 99212948 ps
CPU time 5.17 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 240088 kb
Host smart-ab7c1b2c-07b8-4855-9bdd-68db1218fbc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1630349624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1630349624
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4243833227
Short name T723
Test name
Test status
Simulation time 42233043 ps
CPU time 5.81 seconds
Started May 23 03:44:25 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 256512 kb
Host smart-d73e0a7d-4d3d-4ca5-baf2-fe3f5222aa4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243833227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4243833227
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.346267393
Short name T808
Test name
Test status
Simulation time 33488035 ps
CPU time 3.42 seconds
Started May 23 03:44:24 PM PDT 24
Finished May 23 03:44:37 PM PDT 24
Peak memory 239312 kb
Host smart-d898f8a4-f8c1-4e1e-83b6-5883a8b51940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=346267393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.346267393
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3124761273
Short name T780
Test name
Test status
Simulation time 378098658 ps
CPU time 10.76 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 243808 kb
Host smart-8d382303-0424-4bfe-99e6-ed5be08975f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3124761273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3124761273
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3217112688
Short name T177
Test name
Test status
Simulation time 3772158543 ps
CPU time 143.01 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 265148 kb
Host smart-521deb71-295b-440e-8774-2195fcc26d45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3217112688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3217112688
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.137144919
Short name T163
Test name
Test status
Simulation time 2071135005 ps
CPU time 292.6 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:49:12 PM PDT 24
Peak memory 265168 kb
Host smart-9f874fcf-da2b-4ecf-90ac-4ec5b7986e20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137144919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.137144919
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1815505857
Short name T772
Test name
Test status
Simulation time 61626443 ps
CPU time 8.43 seconds
Started May 23 03:44:14 PM PDT 24
Finished May 23 03:44:31 PM PDT 24
Peak memory 248388 kb
Host smart-7d9f15d2-b593-41cb-b789-1e241a3352d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815505857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1815505857
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1634677734
Short name T826
Test name
Test status
Simulation time 108847502 ps
CPU time 4.79 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 240176 kb
Host smart-baceb380-a0c5-482c-973e-91d11c2a90b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634677734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1634677734
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.733618822
Short name T782
Test name
Test status
Simulation time 23990198 ps
CPU time 3.4 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:45:24 PM PDT 24
Peak memory 239384 kb
Host smart-62d58c85-292d-4aa6-acc6-3407c73225f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=733618822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.733618822
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3075502102
Short name T371
Test name
Test status
Simulation time 7301874 ps
CPU time 1.38 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:24 PM PDT 24
Peak memory 236588 kb
Host smart-bbc07362-305d-4f4c-8d3a-862c798cbf3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3075502102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3075502102
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4141393011
Short name T736
Test name
Test status
Simulation time 296444458 ps
CPU time 11.86 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:36 PM PDT 24
Peak memory 244776 kb
Host smart-497b4bef-f0ad-47c7-bbb3-5c3c81193c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4141393011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4141393011
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4071904280
Short name T725
Test name
Test status
Simulation time 104056195 ps
CPU time 6.88 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 247812 kb
Host smart-aa2437c8-86ab-4a40-9fcd-435357f0c72f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4071904280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4071904280
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1719449451
Short name T775
Test name
Test status
Simulation time 62651732 ps
CPU time 9.78 seconds
Started May 23 03:45:04 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 256332 kb
Host smart-1eb00496-0139-41b3-a233-82b5e8bced19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719449451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1719449451
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1436426032
Short name T756
Test name
Test status
Simulation time 90169973 ps
CPU time 4.75 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 235656 kb
Host smart-91bf4f07-2be2-4b42-bc69-155d8e86bf80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1436426032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1436426032
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1264571998
Short name T713
Test name
Test status
Simulation time 7316943 ps
CPU time 1.44 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 234632 kb
Host smart-94d84879-48c2-434d-8021-93dfbf1c3b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1264571998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1264571998
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4197694187
Short name T814
Test name
Test status
Simulation time 321760468 ps
CPU time 12.69 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:39 PM PDT 24
Peak memory 244740 kb
Host smart-c71bda15-b735-4a75-aefb-ef4766dad2d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4197694187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4197694187
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.112040251
Short name T164
Test name
Test status
Simulation time 2863924209 ps
CPU time 180.01 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:48:24 PM PDT 24
Peak memory 265148 kb
Host smart-62b8fdb5-9694-491e-84f2-21b6f880c98f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112040251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.112040251
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.625791217
Short name T730
Test name
Test status
Simulation time 193562056 ps
CPU time 6.04 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 248304 kb
Host smart-d726747e-2b9e-4eaa-9092-74f676ba11de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=625791217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.625791217
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3240000896
Short name T759
Test name
Test status
Simulation time 86638267 ps
CPU time 3.63 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:35 PM PDT 24
Peak memory 239904 kb
Host smart-8de3b7c6-0d3a-400f-b922-e00efa840fb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240000896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3240000896
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1762556680
Short name T377
Test name
Test status
Simulation time 187816433 ps
CPU time 4.82 seconds
Started May 23 03:45:15 PM PDT 24
Finished May 23 03:45:38 PM PDT 24
Peak memory 236532 kb
Host smart-9102d74f-feb5-4ea2-ac68-77d27d616c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1762556680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1762556680
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2633163842
Short name T717
Test name
Test status
Simulation time 18127963 ps
CPU time 1.38 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 236608 kb
Host smart-56c5076a-77b6-432a-b62a-77f2cb9e8d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2633163842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2633163842
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.32121765
Short name T757
Test name
Test status
Simulation time 490439783 ps
CPU time 17.49 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 244744 kb
Host smart-2638afb7-8a46-4373-9c35-5adc41dfd5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=32121765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outs
tanding.32121765
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3181549966
Short name T165
Test name
Test status
Simulation time 18573933449 ps
CPU time 794.09 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:58:48 PM PDT 24
Peak memory 273284 kb
Host smart-dbabea5b-8403-4ada-ac3e-47a2c14e173e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181549966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3181549966
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1105167761
Short name T781
Test name
Test status
Simulation time 332866734 ps
CPU time 18.01 seconds
Started May 23 03:45:21 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 247492 kb
Host smart-5d3d926f-a90a-4c10-afe8-323838a9608f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1105167761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1105167761
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3893345101
Short name T734
Test name
Test status
Simulation time 77994385 ps
CPU time 5.86 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 240144 kb
Host smart-1a72821c-9f40-4f5a-af97-770ea255e403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893345101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3893345101
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3396751517
Short name T218
Test name
Test status
Simulation time 22296030 ps
CPU time 3.6 seconds
Started May 23 03:45:17 PM PDT 24
Finished May 23 03:45:40 PM PDT 24
Peak memory 236564 kb
Host smart-ed559092-527f-45b3-b165-44d561d90c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3396751517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3396751517
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.288758005
Short name T822
Test name
Test status
Simulation time 11343950 ps
CPU time 1.79 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:45:22 PM PDT 24
Peak memory 236472 kb
Host smart-480eb6c5-50e5-4129-a658-d10513a4076a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=288758005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.288758005
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1115305525
Short name T728
Test name
Test status
Simulation time 463650800 ps
CPU time 13.21 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:44 PM PDT 24
Peak memory 244776 kb
Host smart-6d8b832e-8c62-41f4-8c0e-b37180e629a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1115305525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1115305525
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2040786425
Short name T152
Test name
Test status
Simulation time 3102533528 ps
CPU time 103 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:47:11 PM PDT 24
Peak memory 256924 kb
Host smart-3b0e2d43-6a97-41ab-a897-f19b42bdca13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040786425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2040786425
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3160657452
Short name T770
Test name
Test status
Simulation time 1704326912 ps
CPU time 16.23 seconds
Started May 23 03:45:15 PM PDT 24
Finished May 23 03:45:49 PM PDT 24
Peak memory 248420 kb
Host smart-5459a98c-e91c-4a39-a7bd-de76558d16f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3160657452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3160657452
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1920824864
Short name T738
Test name
Test status
Simulation time 465963801 ps
CPU time 31.11 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 236800 kb
Host smart-4a32a81d-542a-4b69-98d9-aae489764ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1920824864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1920824864
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4211007393
Short name T788
Test name
Test status
Simulation time 263013622 ps
CPU time 4.44 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 240156 kb
Host smart-aadf7ddb-ba32-4d41-bb6d-70bd028f7dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211007393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4211007393
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.970050084
Short name T798
Test name
Test status
Simulation time 359993022 ps
CPU time 8.09 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 236576 kb
Host smart-51c645e3-956e-4421-8c7c-17bcf519ae64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=970050084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.970050084
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.788579868
Short name T183
Test name
Test status
Simulation time 16196310 ps
CPU time 1.32 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 236624 kb
Host smart-0553a552-5859-41be-9b95-7e8d4643c3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=788579868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.788579868
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3872916875
Short name T791
Test name
Test status
Simulation time 728466773 ps
CPU time 46.06 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 244740 kb
Host smart-876be489-3d78-40ab-b054-242e1cc29c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3872916875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3872916875
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.872833671
Short name T153
Test name
Test status
Simulation time 4394593909 ps
CPU time 335.01 seconds
Started May 23 03:45:13 PM PDT 24
Finished May 23 03:51:06 PM PDT 24
Peak memory 265128 kb
Host smart-eba7ebb8-6423-4b48-920f-d5eaa4579d7d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872833671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.872833671
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.157074759
Short name T726
Test name
Test status
Simulation time 60568830 ps
CPU time 7.9 seconds
Started May 23 03:45:19 PM PDT 24
Finished May 23 03:45:47 PM PDT 24
Peak memory 252448 kb
Host smart-59c7e851-a7a4-40f7-9915-50a30e7b64c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=157074759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.157074759
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3705381550
Short name T784
Test name
Test status
Simulation time 295248894 ps
CPU time 8.92 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 256460 kb
Host smart-38bcd544-f62d-4080-8cf3-adeb2851d7fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705381550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3705381550
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3562870341
Short name T214
Test name
Test status
Simulation time 75900734 ps
CPU time 5.63 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 236528 kb
Host smart-bb229e15-06e4-410b-8947-8cec2d560e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3562870341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3562870341
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.280697448
Short name T797
Test name
Test status
Simulation time 27152218 ps
CPU time 1.23 seconds
Started May 23 03:45:24 PM PDT 24
Finished May 23 03:45:46 PM PDT 24
Peak memory 236356 kb
Host smart-40d19566-87eb-4521-a4b2-50aaa019391e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=280697448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.280697448
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4270623673
Short name T754
Test name
Test status
Simulation time 388324247 ps
CPU time 12.59 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 240112 kb
Host smart-ce57183e-de5b-4eab-8bb2-80f1a882c7c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270623673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4270623673
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.719027665
Short name T169
Test name
Test status
Simulation time 2073054316 ps
CPU time 135.34 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:47:43 PM PDT 24
Peak memory 265088 kb
Host smart-b6d625f3-1b1e-43e5-b73f-c1223571c227
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=719027665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.719027665
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.627732354
Short name T160
Test name
Test status
Simulation time 2366608575 ps
CPU time 361.43 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:51:23 PM PDT 24
Peak memory 266224 kb
Host smart-4fc6eef3-c152-439f-9a99-6fc38f56686a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627732354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.627732354
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.929262144
Short name T790
Test name
Test status
Simulation time 91101334 ps
CPU time 11.32 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 248172 kb
Host smart-e6aacf74-e4a9-4804-be74-29b044d11063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=929262144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.929262144
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2532107188
Short name T802
Test name
Test status
Simulation time 520739464 ps
CPU time 9.23 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 237624 kb
Host smart-a3419e43-ca27-4efe-9daf-3314c3d6e162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532107188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2532107188
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2284349719
Short name T812
Test name
Test status
Simulation time 266879355 ps
CPU time 5.79 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 239292 kb
Host smart-cadae3ab-2179-4f11-b048-c980233998ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2284349719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2284349719
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1094801858
Short name T718
Test name
Test status
Simulation time 18086241 ps
CPU time 1.4 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 236640 kb
Host smart-4ac8355b-a9af-4f30-beec-0ca94acf93f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1094801858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1094801858
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2314719785
Short name T785
Test name
Test status
Simulation time 365123718 ps
CPU time 11.68 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:46 PM PDT 24
Peak memory 243836 kb
Host smart-31e35074-606d-4d57-bfc6-1998b3a5ec5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2314719785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2314719785
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3350851549
Short name T141
Test name
Test status
Simulation time 4756188702 ps
CPU time 152.49 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:48:10 PM PDT 24
Peak memory 264760 kb
Host smart-292639ef-91cb-4bdd-b13c-f6fd6ebfac85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3350851549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3350851549
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.779566730
Short name T157
Test name
Test status
Simulation time 9324575011 ps
CPU time 580.9 seconds
Started May 23 03:45:00 PM PDT 24
Finished May 23 03:54:59 PM PDT 24
Peak memory 265012 kb
Host smart-5190d5e8-2efa-4674-a55d-0f320f49b5ba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779566730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.779566730
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4145555335
Short name T273
Test name
Test status
Simulation time 408726732 ps
CPU time 13.12 seconds
Started May 23 03:45:15 PM PDT 24
Finished May 23 03:45:47 PM PDT 24
Peak memory 248352 kb
Host smart-507f38ca-094b-46ec-9a11-e7bbbd1c7ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145555335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4145555335
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4288198595
Short name T809
Test name
Test status
Simulation time 24894281 ps
CPU time 3.79 seconds
Started May 23 03:45:23 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 239792 kb
Host smart-7d728504-24f2-41db-b8c9-f317a417b95b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288198595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4288198595
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1133911138
Short name T801
Test name
Test status
Simulation time 519967096 ps
CPU time 9.04 seconds
Started May 23 03:45:15 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 240100 kb
Host smart-af26a44b-af7e-4350-a75d-93274064c7ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1133911138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1133911138
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1338088855
Short name T368
Test name
Test status
Simulation time 16425944 ps
CPU time 1.31 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 235648 kb
Host smart-b0c869d0-afc0-40d8-b68b-303bd99fd926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1338088855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1338088855
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1638242866
Short name T815
Test name
Test status
Simulation time 1562933307 ps
CPU time 25.04 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:46:15 PM PDT 24
Peak memory 244776 kb
Host smart-85e008ee-1138-45c4-96da-9bcefd8ba470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1638242866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1638242866
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.582326294
Short name T166
Test name
Test status
Simulation time 5563486982 ps
CPU time 325.26 seconds
Started May 23 03:45:21 PM PDT 24
Finished May 23 03:51:07 PM PDT 24
Peak memory 271248 kb
Host smart-8d6499ba-369e-421e-95da-59d43ed5d4b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582326294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.582326294
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3897783035
Short name T178
Test name
Test status
Simulation time 14899930700 ps
CPU time 600.84 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:55:30 PM PDT 24
Peak memory 265124 kb
Host smart-2685bb91-6bc7-41a3-ab41-2e68c9483824
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897783035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3897783035
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3928151508
Short name T708
Test name
Test status
Simulation time 630402494 ps
CPU time 21.51 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 253824 kb
Host smart-1248fcda-1357-4327-8e10-b20243f7e3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928151508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3928151508
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.708064427
Short name T714
Test name
Test status
Simulation time 133037400 ps
CPU time 10.47 seconds
Started May 23 03:45:27 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 236992 kb
Host smart-a84772ae-c63e-4ead-b208-3faaa2e5fdab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708064427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.708064427
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.787614011
Short name T743
Test name
Test status
Simulation time 232344440 ps
CPU time 5.47 seconds
Started May 23 03:45:27 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236540 kb
Host smart-5ff6f7a8-9722-4a4e-a041-579d787eef48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=787614011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.787614011
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3916879809
Short name T716
Test name
Test status
Simulation time 8620025 ps
CPU time 1.53 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:39 PM PDT 24
Peak memory 236552 kb
Host smart-daf2aad7-4b13-40c2-acdc-f4d711dd4c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3916879809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3916879809
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1473596792
Short name T764
Test name
Test status
Simulation time 1040564733 ps
CPU time 18.57 seconds
Started May 23 03:45:19 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 239648 kb
Host smart-6e8962d1-2cce-44fd-a74b-9437442dc5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1473596792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1473596792
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1786093633
Short name T179
Test name
Test status
Simulation time 3484707268 ps
CPU time 233.26 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:49:32 PM PDT 24
Peak memory 264932 kb
Host smart-1ef43aed-4c81-41b8-aba9-625b321e996e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786093633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1786093633
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1289811897
Short name T794
Test name
Test status
Simulation time 823380814 ps
CPU time 11.03 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:46:02 PM PDT 24
Peak memory 251948 kb
Host smart-37910d98-a171-44c3-a157-a85aee717075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1289811897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1289811897
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2716881328
Short name T376
Test name
Test status
Simulation time 33870805 ps
CPU time 4.72 seconds
Started May 23 03:45:19 PM PDT 24
Finished May 23 03:45:45 PM PDT 24
Peak memory 240968 kb
Host smart-093aa96f-3db5-472f-8c5d-1b1fd0c060ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716881328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2716881328
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1426876634
Short name T823
Test name
Test status
Simulation time 252003873 ps
CPU time 5.18 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236564 kb
Host smart-0dae6b94-ab34-401a-a868-e337a28fb17b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1426876634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1426876634
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3558880238
Short name T185
Test name
Test status
Simulation time 12443308 ps
CPU time 1.38 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236612 kb
Host smart-bfd4495c-357d-43b1-aa03-9c9c8b86aa8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3558880238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3558880238
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3508305758
Short name T200
Test name
Test status
Simulation time 3164198588 ps
CPU time 45.41 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 244808 kb
Host smart-399a2ad4-bedf-4d94-85d6-1009b7071185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3508305758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3508305758
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2959007946
Short name T159
Test name
Test status
Simulation time 10044380408 ps
CPU time 322.69 seconds
Started May 23 03:45:19 PM PDT 24
Finished May 23 03:51:02 PM PDT 24
Peak memory 265092 kb
Host smart-1313952f-96fa-4770-8ecb-a21af7ced1c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959007946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2959007946
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.438682704
Short name T710
Test name
Test status
Simulation time 929659995 ps
CPU time 15.39 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 247572 kb
Host smart-6e1a5323-e3c8-4579-bce3-93d9a4ef914c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=438682704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.438682704
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3769595102
Short name T799
Test name
Test status
Simulation time 569825017 ps
CPU time 61.67 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 240088 kb
Host smart-a2df773a-c08e-49af-8105-0cd9712665e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3769595102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3769595102
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2389674305
Short name T374
Test name
Test status
Simulation time 8899997314 ps
CPU time 484.58 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:52:59 PM PDT 24
Peak memory 240160 kb
Host smart-fa10d8cc-bd95-4836-a017-a8d2684ac221
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2389674305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2389674305
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.122944702
Short name T763
Test name
Test status
Simulation time 54811389 ps
CPU time 4.59 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 240084 kb
Host smart-ead7710f-8754-43f2-b660-558f57474413
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=122944702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.122944702
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1964953214
Short name T373
Test name
Test status
Simulation time 633811074 ps
CPU time 9.21 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 256532 kb
Host smart-cbfd5ec4-4a89-4e92-839a-efdaa11c377d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964953214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1964953214
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.297614979
Short name T817
Test name
Test status
Simulation time 258395079 ps
CPU time 9.61 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:13 PM PDT 24
Peak memory 236572 kb
Host smart-8e88c103-9ec8-4fe6-bd51-f639a1e69795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=297614979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.297614979
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3910098279
Short name T765
Test name
Test status
Simulation time 8045779 ps
CPU time 1.44 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:52 PM PDT 24
Peak memory 234628 kb
Host smart-07268c54-7375-4f32-be0e-b24f43d187c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3910098279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3910098279
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3795671547
Short name T732
Test name
Test status
Simulation time 537336219 ps
CPU time 11.9 seconds
Started May 23 03:44:39 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 244760 kb
Host smart-4402a965-fa6a-43e0-a343-8689256c4ae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3795671547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3795671547
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3138787259
Short name T755
Test name
Test status
Simulation time 312676442 ps
CPU time 12.05 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 247964 kb
Host smart-e946cffd-c6fc-4589-8e20-a291362785aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3138787259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3138787259
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1958067781
Short name T719
Test name
Test status
Simulation time 19075120 ps
CPU time 1.38 seconds
Started May 23 03:45:27 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 235664 kb
Host smart-f4ff19e4-6563-4e5d-a2d2-eeffdf7b41ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1958067781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1958067781
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2398494149
Short name T771
Test name
Test status
Simulation time 7837685 ps
CPU time 1.24 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:51 PM PDT 24
Peak memory 235676 kb
Host smart-1f72b8dc-ef2c-4478-afaf-40edbe4e10b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2398494149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2398494149
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4245198757
Short name T745
Test name
Test status
Simulation time 11936513 ps
CPU time 1.44 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 236616 kb
Host smart-84c20469-9c67-42b7-a694-7ed68c1e1390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4245198757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4245198757
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1956929289
Short name T795
Test name
Test status
Simulation time 11966757 ps
CPU time 1.36 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 235668 kb
Host smart-89523e82-1bfb-4826-ac73-2c113b0e8145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1956929289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1956929289
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2789220744
Short name T739
Test name
Test status
Simulation time 12450148 ps
CPU time 1.44 seconds
Started May 23 03:45:27 PM PDT 24
Finished May 23 03:45:49 PM PDT 24
Peak memory 236584 kb
Host smart-de0331a5-1ece-4479-a36f-a88506a5274b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2789220744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2789220744
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3356484602
Short name T735
Test name
Test status
Simulation time 10510738 ps
CPU time 1.63 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:49 PM PDT 24
Peak memory 236588 kb
Host smart-07118958-3d9b-4be9-a8ed-d30fb201e62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3356484602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3356484602
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.946491786
Short name T768
Test name
Test status
Simulation time 8215028 ps
CPU time 1.51 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 236580 kb
Host smart-50a6af2c-eb48-48d7-bd38-d4f97fbc150c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=946491786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.946491786
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1667994799
Short name T748
Test name
Test status
Simulation time 11516568 ps
CPU time 1.36 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 235664 kb
Host smart-bad53dfd-b416-4688-8c2c-d321c05d0978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1667994799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1667994799
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1848442531
Short name T776
Test name
Test status
Simulation time 14518602 ps
CPU time 1.35 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 234608 kb
Host smart-c3f702ef-eeb4-4750-86aa-b2adb7da7234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1848442531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1848442531
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3299644412
Short name T724
Test name
Test status
Simulation time 28309849 ps
CPU time 1.54 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 235648 kb
Host smart-c6c20e48-f486-4a94-86f8-71f7451a5fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3299644412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3299644412
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1183314536
Short name T758
Test name
Test status
Simulation time 2303434678 ps
CPU time 142.18 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 236660 kb
Host smart-ff6dd778-ed79-4991-9526-e6b27137e02e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1183314536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1183314536
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3588612061
Short name T217
Test name
Test status
Simulation time 13605806863 ps
CPU time 226.26 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:48:35 PM PDT 24
Peak memory 240184 kb
Host smart-490e27ea-b61a-446b-8496-7426ac04da3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3588612061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3588612061
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4284962026
Short name T810
Test name
Test status
Simulation time 73797960 ps
CPU time 3.97 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:44:50 PM PDT 24
Peak memory 240124 kb
Host smart-3d509f14-924d-4699-91b8-b38f0090f05c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4284962026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4284962026
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2970519563
Short name T769
Test name
Test status
Simulation time 208707613 ps
CPU time 5.16 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 239508 kb
Host smart-a1a66940-af2c-49a8-848a-be5873462d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970519563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2970519563
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2685637044
Short name T807
Test name
Test status
Simulation time 247688256 ps
CPU time 9.11 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 236560 kb
Host smart-fe97c38a-fd71-4f10-b8b1-3c808d2f356f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2685637044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2685637044
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1494318989
Short name T789
Test name
Test status
Simulation time 9300977 ps
CPU time 1.19 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:51 PM PDT 24
Peak memory 236540 kb
Host smart-3da2278e-cbf5-43ce-8716-e15d4eab5925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1494318989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1494318989
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.719384051
Short name T219
Test name
Test status
Simulation time 337727508 ps
CPU time 20.21 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 244780 kb
Host smart-8379674c-ae76-4971-963f-e8bc1b3b27c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=719384051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.719384051
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1552702180
Short name T170
Test name
Test status
Simulation time 3420506478 ps
CPU time 216.66 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:48:32 PM PDT 24
Peak memory 265180 kb
Host smart-b2f0d97b-2c46-4529-9541-02787a8456da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1552702180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1552702180
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1814828706
Short name T145
Test name
Test status
Simulation time 6334919387 ps
CPU time 462.17 seconds
Started May 23 03:44:41 PM PDT 24
Finished May 23 03:52:38 PM PDT 24
Peak memory 265092 kb
Host smart-42f49fd0-9a86-4737-8427-53cb59a9cb82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814828706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1814828706
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.785397426
Short name T774
Test name
Test status
Simulation time 211584698 ps
CPU time 12.91 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 256208 kb
Host smart-956af516-bd34-4859-972b-cd1a51b88fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=785397426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.785397426
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1844540632
Short name T766
Test name
Test status
Simulation time 94889460 ps
CPU time 3.94 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 236524 kb
Host smart-0226e20a-aaa8-425f-aced-21d10df68161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1844540632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1844540632
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3701713286
Short name T824
Test name
Test status
Simulation time 9837305 ps
CPU time 1.57 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 236572 kb
Host smart-0bc3f536-332d-4b93-8e73-4d1de0669351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3701713286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3701713286
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4174833470
Short name T742
Test name
Test status
Simulation time 9828242 ps
CPU time 1.53 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 234652 kb
Host smart-e3af4084-c17b-4f0d-80b5-2d684b0995f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4174833470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4174833470
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.229386944
Short name T760
Test name
Test status
Simulation time 8644728 ps
CPU time 1.5 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 236616 kb
Host smart-992a6e3b-4673-4c02-b312-003f8b1576d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229386944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.229386944
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1546712315
Short name T372
Test name
Test status
Simulation time 9647408 ps
CPU time 1.49 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 236584 kb
Host smart-4010fe56-d9c8-47da-8563-513a055b8042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546712315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1546712315
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.169326045
Short name T777
Test name
Test status
Simulation time 10684493 ps
CPU time 1.28 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 236536 kb
Host smart-ffe23436-11c3-486c-8a29-bdef4c2609d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=169326045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.169326045
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4121965956
Short name T370
Test name
Test status
Simulation time 8683598 ps
CPU time 1.51 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 235660 kb
Host smart-89286291-3db1-4417-99a7-bd17d539ab0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4121965956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4121965956
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1919796225
Short name T811
Test name
Test status
Simulation time 15524854 ps
CPU time 1.43 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 235656 kb
Host smart-88b42f51-71bd-42f3-bd3d-a4aeff3bd8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1919796225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1919796225
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.209863664
Short name T803
Test name
Test status
Simulation time 9047510 ps
CPU time 1.48 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 236584 kb
Host smart-6e64391d-a3a7-46fc-a25e-42ba53a8f881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=209863664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.209863664
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.601512748
Short name T800
Test name
Test status
Simulation time 10127553 ps
CPU time 1.5 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 234664 kb
Host smart-2e01c456-c93e-472d-a9ea-fc52b28daf29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=601512748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.601512748
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2318081120
Short name T816
Test name
Test status
Simulation time 7122530349 ps
CPU time 239.95 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:49:02 PM PDT 24
Peak memory 240192 kb
Host smart-3e376475-5bed-4977-a504-ad934d07b777
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2318081120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2318081120
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2655385620
Short name T197
Test name
Test status
Simulation time 18579528726 ps
CPU time 264.5 seconds
Started May 23 03:45:00 PM PDT 24
Finished May 23 03:49:42 PM PDT 24
Peak memory 236652 kb
Host smart-7ae55b11-0189-459a-9cf2-0b7213f47533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2655385620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2655385620
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2758177585
Short name T783
Test name
Test status
Simulation time 135037528 ps
CPU time 9.13 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 240132 kb
Host smart-c5ee0e92-5df7-416d-a8e7-7a4662a4ef5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2758177585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2758177585
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4294960366
Short name T750
Test name
Test status
Simulation time 79099895 ps
CPU time 6.73 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 240120 kb
Host smart-918726e3-88cb-41e0-9c5b-e9dfa5bf4b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294960366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4294960366
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.367093739
Short name T805
Test name
Test status
Simulation time 34914801 ps
CPU time 4.92 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:19 PM PDT 24
Peak memory 235612 kb
Host smart-03984e9b-e4e8-46fd-b9c8-eda43b090aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=367093739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.367093739
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2453305364
Short name T744
Test name
Test status
Simulation time 10919880 ps
CPU time 1.23 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 235624 kb
Host smart-702aa42c-167d-46ba-99e9-cb8e2b21d23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2453305364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2453305364
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3107145225
Short name T741
Test name
Test status
Simulation time 262029977 ps
CPU time 17.01 seconds
Started May 23 03:44:53 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 248324 kb
Host smart-d1513400-ed52-4a2e-89c1-d40bfd15343e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107145225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3107145225
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.953830744
Short name T147
Test name
Test status
Simulation time 2607399151 ps
CPU time 248.39 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:49:04 PM PDT 24
Peak memory 271664 kb
Host smart-fd1a3fd6-e4f0-43b6-856e-768717cb7101
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=953830744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.953830744
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2562791766
Short name T813
Test name
Test status
Simulation time 818329931 ps
CPU time 14.01 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 247020 kb
Host smart-da78b6e6-f612-469a-82fa-0058276710c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562791766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2562791766
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2573351766
Short name T366
Test name
Test status
Simulation time 19242439 ps
CPU time 1.39 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 236608 kb
Host smart-b3ce03bb-6a89-43ea-9084-32c6bab6268c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2573351766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2573351766
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4177983402
Short name T761
Test name
Test status
Simulation time 9618606 ps
CPU time 1.25 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 236612 kb
Host smart-e1656d53-8815-477e-bff5-a798c47e7309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4177983402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4177983402
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1568750259
Short name T767
Test name
Test status
Simulation time 12509860 ps
CPU time 1.24 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236640 kb
Host smart-0b25be42-17b1-4ea4-8235-7991b385a3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568750259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1568750259
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4282890166
Short name T712
Test name
Test status
Simulation time 10072984 ps
CPU time 1.37 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 235700 kb
Host smart-cd3d7edc-1b1c-462e-b73a-2a81f07033f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4282890166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4282890166
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2462747356
Short name T733
Test name
Test status
Simulation time 8255542 ps
CPU time 1.54 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 236616 kb
Host smart-b63b62b3-6a39-45d0-a915-328eef63d2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2462747356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2462747356
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2214423572
Short name T793
Test name
Test status
Simulation time 24036385 ps
CPU time 1.26 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 236588 kb
Host smart-7074986a-6ed4-4a54-8edd-ac738a9e3b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2214423572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2214423572
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.256134443
Short name T715
Test name
Test status
Simulation time 11940349 ps
CPU time 1.41 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:51 PM PDT 24
Peak memory 236580 kb
Host smart-a0437594-4316-4112-a929-e92660e2a119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=256134443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.256134443
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4205533834
Short name T804
Test name
Test status
Simulation time 24490373 ps
CPU time 1.51 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 236608 kb
Host smart-f4c5add8-046c-4235-b35a-19eb06089b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205533834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4205533834
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4038669752
Short name T779
Test name
Test status
Simulation time 20055361 ps
CPU time 1.37 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:53 PM PDT 24
Peak memory 236608 kb
Host smart-d9ec9d8d-8b8e-4389-bbfa-7d71b8566c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4038669752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4038669752
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1272549562
Short name T369
Test name
Test status
Simulation time 7262036 ps
CPU time 1.36 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 234672 kb
Host smart-2451dffa-0c15-4860-9317-17334b35e578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1272549562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1272549562
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1884323762
Short name T749
Test name
Test status
Simulation time 547738477 ps
CPU time 12.75 seconds
Started May 23 03:44:57 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 251656 kb
Host smart-5e99ac7d-7077-4177-b9e8-c9c72aaae720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884323762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1884323762
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4098495504
Short name T752
Test name
Test status
Simulation time 332808039 ps
CPU time 4.54 seconds
Started May 23 03:44:50 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 238400 kb
Host smart-9b1eb7e1-09a6-49f7-a749-8b84cfff914b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4098495504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4098495504
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1153877945
Short name T819
Test name
Test status
Simulation time 10131477 ps
CPU time 1.3 seconds
Started May 23 03:44:53 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 235648 kb
Host smart-d9ec8cc4-48ad-45f8-93e9-aa789f9ee6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153877945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1153877945
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.433852548
Short name T773
Test name
Test status
Simulation time 662588091 ps
CPU time 39.69 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 244784 kb
Host smart-2050126a-d754-41bc-a7ee-0bb3cfba2481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=433852548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.433852548
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3492941795
Short name T172
Test name
Test status
Simulation time 3091132136 ps
CPU time 92.36 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 265148 kb
Host smart-b554fd23-937b-4df7-baeb-4caf631663bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3492941795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3492941795
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1915111774
Short name T173
Test name
Test status
Simulation time 86533938671 ps
CPU time 1091.08 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 04:03:34 PM PDT 24
Peak memory 271252 kb
Host smart-91b3e921-604c-47da-8f78-61337fc80e00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915111774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1915111774
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1451747350
Short name T709
Test name
Test status
Simulation time 56192373 ps
CPU time 7.59 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 248224 kb
Host smart-d764f463-3274-44f0-b49d-34e16d1e1961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1451747350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1451747350
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3231503283
Short name T294
Test name
Test status
Simulation time 612605413 ps
CPU time 20.67 seconds
Started May 23 03:45:04 PM PDT 24
Finished May 23 03:45:43 PM PDT 24
Peak memory 236544 kb
Host smart-c1b0b317-d8b8-42ee-b64e-7bcc5cee981a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3231503283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3231503283
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3936477426
Short name T198
Test name
Test status
Simulation time 692826810 ps
CPU time 11.36 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:16 PM PDT 24
Peak memory 243812 kb
Host smart-3b3e2c36-6052-4c82-83a5-1198f4e73b48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936477426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3936477426
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3556654692
Short name T751
Test name
Test status
Simulation time 25236545 ps
CPU time 3.4 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:17 PM PDT 24
Peak memory 238284 kb
Host smart-8cbf9f1f-7de1-4661-b1c6-2ee5cdb9ed18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3556654692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3556654692
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2359716113
Short name T806
Test name
Test status
Simulation time 8121810 ps
CPU time 1.48 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 234620 kb
Host smart-c7a4b49f-85fc-4759-8ca7-1290e8e2c542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2359716113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2359716113
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2223980268
Short name T729
Test name
Test status
Simulation time 2088491264 ps
CPU time 20.88 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:22 PM PDT 24
Peak memory 244764 kb
Host smart-ca48d694-96a6-430a-ad06-8b6b8e6242da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2223980268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2223980268
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1464125439
Short name T820
Test name
Test status
Simulation time 185538660 ps
CPU time 11.37 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 252148 kb
Host smart-131625a9-e414-4be0-b752-0315767263f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1464125439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1464125439
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3577490561
Short name T375
Test name
Test status
Simulation time 296422674 ps
CPU time 11.96 seconds
Started May 23 03:45:04 PM PDT 24
Finished May 23 03:45:33 PM PDT 24
Peak memory 256388 kb
Host smart-99cde548-e8f8-4ecf-97ce-50b70ba54177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577490561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3577490561
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1616444005
Short name T821
Test name
Test status
Simulation time 113207031 ps
CPU time 7.68 seconds
Started May 23 03:44:49 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 235636 kb
Host smart-522eeb44-5783-4a1e-b614-497068b568be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1616444005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1616444005
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3801449299
Short name T796
Test name
Test status
Simulation time 10157111 ps
CPU time 1.3 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:24 PM PDT 24
Peak memory 234644 kb
Host smart-17c3f100-61c8-47dc-8402-e07da1d09216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3801449299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3801449299
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.864831782
Short name T213
Test name
Test status
Simulation time 400250749 ps
CPU time 20.64 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 240104 kb
Host smart-fa222bc5-0288-4e44-bc08-19c7ca45729f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=864831782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.864831782
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3283956914
Short name T161
Test name
Test status
Simulation time 49593112989 ps
CPU time 1078.37 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 04:03:23 PM PDT 24
Peak memory 265116 kb
Host smart-571dd52b-bf9b-423c-9112-7322fc1bdbfb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283956914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3283956914
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1768335134
Short name T720
Test name
Test status
Simulation time 388564743 ps
CPU time 12.3 seconds
Started May 23 03:44:56 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 252620 kb
Host smart-c5f7b73a-1b57-43f4-8519-a7adc8e2b033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768335134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1768335134
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3871882038
Short name T731
Test name
Test status
Simulation time 114259581 ps
CPU time 4.18 seconds
Started May 23 03:44:57 PM PDT 24
Finished May 23 03:45:20 PM PDT 24
Peak memory 239484 kb
Host smart-201e66e7-88a9-478b-9f2c-3a48688f21c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871882038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3871882038
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3909185658
Short name T215
Test name
Test status
Simulation time 93564654 ps
CPU time 7.91 seconds
Started May 23 03:44:54 PM PDT 24
Finished May 23 03:45:20 PM PDT 24
Peak memory 236552 kb
Host smart-0c6ceb9b-9e2a-40bf-80c4-5847685c0dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3909185658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3909185658
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1071916396
Short name T722
Test name
Test status
Simulation time 15185235 ps
CPU time 1.43 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 235728 kb
Host smart-dce9ef82-c29d-4edd-8b32-ebb6a21c39af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1071916396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1071916396
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1498040347
Short name T787
Test name
Test status
Simulation time 3223440335 ps
CPU time 21.18 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:40 PM PDT 24
Peak memory 244740 kb
Host smart-756dad10-04d7-4e14-8c1a-8fafc5f4f929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1498040347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1498040347
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3053013318
Short name T144
Test name
Test status
Simulation time 4366065040 ps
CPU time 291.32 seconds
Started May 23 03:44:56 PM PDT 24
Finished May 23 03:50:06 PM PDT 24
Peak memory 265132 kb
Host smart-790bc60e-b39e-46a8-910a-666231bb9f44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053013318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3053013318
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.828280047
Short name T746
Test name
Test status
Simulation time 1091420007 ps
CPU time 21.77 seconds
Started May 23 03:44:54 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 254852 kb
Host smart-1a2ef22f-36ec-4473-a4ba-29fd13d8067c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=828280047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.828280047
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2842672223
Short name T378
Test name
Test status
Simulation time 69064048 ps
CPU time 5.95 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 248420 kb
Host smart-f99592ca-b67c-4ba8-ab1d-01818a08a36e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842672223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2842672223
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2712919356
Short name T825
Test name
Test status
Simulation time 358372110 ps
CPU time 7.57 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 240016 kb
Host smart-215b47b9-c97b-46fb-aebd-a133b5f96f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2712919356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2712919356
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.31447264
Short name T818
Test name
Test status
Simulation time 9815833 ps
CPU time 1.23 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 234580 kb
Host smart-5bd15fc1-e7c7-45bb-bea9-ca3f3f826256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=31447264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.31447264
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.684301242
Short name T753
Test name
Test status
Simulation time 3423436199 ps
CPU time 33.56 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:35 PM PDT 24
Peak memory 244796 kb
Host smart-c6989a33-b95a-44b3-a4e1-10cfa6f850cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=684301242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.684301242
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4268951730
Short name T174
Test name
Test status
Simulation time 1920727893 ps
CPU time 123.99 seconds
Started May 23 03:44:57 PM PDT 24
Finished May 23 03:47:19 PM PDT 24
Peak memory 256772 kb
Host smart-f271ec32-1c93-439b-a37e-8a0b38874584
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4268951730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4268951730
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.677175399
Short name T143
Test name
Test status
Simulation time 7318745913 ps
CPU time 483.07 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:53:05 PM PDT 24
Peak memory 265076 kb
Host smart-4d0148f0-84b8-450e-88c8-9a813b60f18d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677175399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.677175399
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1390489107
Short name T721
Test name
Test status
Simulation time 645235032 ps
CPU time 10.74 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 247872 kb
Host smart-306b4b0f-b754-4f40-969e-5a0cb9b42fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1390489107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1390489107
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1764857504
Short name T653
Test name
Test status
Simulation time 210331247425 ps
CPU time 3421.92 seconds
Started May 23 02:28:13 PM PDT 24
Finished May 23 03:25:16 PM PDT 24
Peak memory 289436 kb
Host smart-6264bb44-144d-4ee3-8ff1-c3ca6b50af34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764857504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1764857504
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.521105867
Short name T420
Test name
Test status
Simulation time 986388123 ps
CPU time 24.18 seconds
Started May 23 02:28:26 PM PDT 24
Finished May 23 02:28:51 PM PDT 24
Peak memory 248812 kb
Host smart-24e5aed0-51a6-47b1-bb6c-f7e17d74bf27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=521105867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.521105867
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.149302699
Short name T492
Test name
Test status
Simulation time 1299370281 ps
CPU time 85.24 seconds
Started May 23 02:28:12 PM PDT 24
Finished May 23 02:29:38 PM PDT 24
Peak memory 256796 kb
Host smart-67b583ab-0063-4810-8948-b3701a7ce1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
2699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.149302699
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2288704471
Short name T128
Test name
Test status
Simulation time 1736997125 ps
CPU time 66.09 seconds
Started May 23 02:28:12 PM PDT 24
Finished May 23 02:29:19 PM PDT 24
Peak memory 248768 kb
Host smart-8a4f9612-4e1a-48c7-973c-4cc18eb2ab24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
04471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2288704471
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1272353062
Short name T323
Test name
Test status
Simulation time 34208880962 ps
CPU time 713.24 seconds
Started May 23 02:28:25 PM PDT 24
Finished May 23 02:40:19 PM PDT 24
Peak memory 267332 kb
Host smart-57a03afc-5668-486d-bed7-e23b4e840a8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272353062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1272353062
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3830813191
Short name T512
Test name
Test status
Simulation time 13737906900 ps
CPU time 924.99 seconds
Started May 23 02:28:30 PM PDT 24
Finished May 23 02:43:55 PM PDT 24
Peak memory 272972 kb
Host smart-fa01f1ce-5b99-4647-ba44-1d93db667586
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830813191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3830813191
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4000874292
Short name T578
Test name
Test status
Simulation time 2781422431 ps
CPU time 62.21 seconds
Started May 23 02:28:14 PM PDT 24
Finished May 23 02:29:17 PM PDT 24
Peak memory 252400 kb
Host smart-3b3cd308-0299-4c8e-9e02-52a22818ea4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000874292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4000874292
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3019393869
Short name T261
Test name
Test status
Simulation time 716126255 ps
CPU time 32.87 seconds
Started May 23 02:28:13 PM PDT 24
Finished May 23 02:28:47 PM PDT 24
Peak memory 248780 kb
Host smart-14e54e59-fdfe-46f0-993a-0ee5e62d9d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30193
93869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3019393869
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3880723102
Short name T390
Test name
Test status
Simulation time 434592433 ps
CPU time 9.2 seconds
Started May 23 02:28:11 PM PDT 24
Finished May 23 02:28:21 PM PDT 24
Peak memory 248792 kb
Host smart-6962e094-0dce-451c-aada-ac8842c601bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
23102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3880723102
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1696032296
Short name T293
Test name
Test status
Simulation time 1452076757 ps
CPU time 50.65 seconds
Started May 23 02:28:13 PM PDT 24
Finished May 23 02:29:04 PM PDT 24
Peak memory 247724 kb
Host smart-5da02785-f9af-46ce-bbc8-095e51ad257d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16960
32296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1696032296
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4083042836
Short name T441
Test name
Test status
Simulation time 1783834810 ps
CPU time 17.91 seconds
Started May 23 02:28:14 PM PDT 24
Finished May 23 02:28:33 PM PDT 24
Peak memory 248768 kb
Host smart-99d84bb8-395a-4112-9a8c-5a43d49996c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
42836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4083042836
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2258946549
Short name T292
Test name
Test status
Simulation time 3270577539 ps
CPU time 190.94 seconds
Started May 23 02:28:29 PM PDT 24
Finished May 23 02:31:40 PM PDT 24
Peak memory 257016 kb
Host smart-c49a61f4-9e6d-4e31-b728-97494f1ab42c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258946549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2258946549
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.728588272
Short name T205
Test name
Test status
Simulation time 98796824192 ps
CPU time 944.24 seconds
Started May 23 02:28:25 PM PDT 24
Finished May 23 02:44:09 PM PDT 24
Peak memory 283308 kb
Host smart-1b38f6e4-b49f-464e-b822-cd94424f2138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728588272 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.728588272
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2763126682
Short name T236
Test name
Test status
Simulation time 82717644 ps
CPU time 3.49 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:28:54 PM PDT 24
Peak memory 248936 kb
Host smart-1d402951-e54a-47f8-a427-f9d8bb58ee0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2763126682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2763126682
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.964248241
Short name T597
Test name
Test status
Simulation time 137563609 ps
CPU time 8.83 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:28:58 PM PDT 24
Peak memory 248796 kb
Host smart-4a816dc4-63f7-4506-bdaa-707203c46d50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=964248241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.964248241
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1592941431
Short name T457
Test name
Test status
Simulation time 11562212259 ps
CPU time 101.15 seconds
Started May 23 02:28:37 PM PDT 24
Finished May 23 02:30:19 PM PDT 24
Peak memory 256860 kb
Host smart-2e364f0a-4953-4b0d-89bc-712692071920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15929
41431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1592941431
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3227015962
Short name T131
Test name
Test status
Simulation time 301843627 ps
CPU time 25.05 seconds
Started May 23 02:28:37 PM PDT 24
Finished May 23 02:29:02 PM PDT 24
Peak memory 256944 kb
Host smart-ae99965c-47ea-49f4-aed5-ceeae58d718c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
15962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3227015962
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1976429444
Short name T591
Test name
Test status
Simulation time 235297757601 ps
CPU time 2452.47 seconds
Started May 23 02:28:47 PM PDT 24
Finished May 23 03:09:40 PM PDT 24
Peak memory 281612 kb
Host smart-add960ea-c993-4a61-89b9-d6a84c17627e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976429444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1976429444
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2664647852
Short name T343
Test name
Test status
Simulation time 4454920799 ps
CPU time 184.62 seconds
Started May 23 02:28:36 PM PDT 24
Finished May 23 02:31:42 PM PDT 24
Peak memory 255932 kb
Host smart-cab53bd4-b855-451a-8663-f2f4096fd9e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664647852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2664647852
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1262812043
Short name T408
Test name
Test status
Simulation time 427523888 ps
CPU time 18.41 seconds
Started May 23 02:28:29 PM PDT 24
Finished May 23 02:28:47 PM PDT 24
Peak memory 248784 kb
Host smart-404aebb3-d542-4224-932e-064e4fa75d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12628
12043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1262812043
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1857762144
Short name T601
Test name
Test status
Simulation time 589258695 ps
CPU time 37.01 seconds
Started May 23 02:28:36 PM PDT 24
Finished May 23 02:29:13 PM PDT 24
Peak memory 255536 kb
Host smart-8fba20c2-e389-4624-ab0c-31f6be573263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18577
62144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1857762144
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1631998407
Short name T76
Test name
Test status
Simulation time 3294425141 ps
CPU time 21.38 seconds
Started May 23 02:28:36 PM PDT 24
Finished May 23 02:28:58 PM PDT 24
Peak memory 248396 kb
Host smart-a3615ee2-7c35-4f7d-96c6-000fe85f52b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
98407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1631998407
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.243393946
Short name T411
Test name
Test status
Simulation time 665265747 ps
CPU time 44.97 seconds
Started May 23 02:28:23 PM PDT 24
Finished May 23 02:29:09 PM PDT 24
Peak memory 248796 kb
Host smart-b548b183-74dd-4620-a2fd-737a4cfcd795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24339
3946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.243393946
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1175616895
Short name T227
Test name
Test status
Simulation time 103454096863 ps
CPU time 2978.51 seconds
Started May 23 02:28:52 PM PDT 24
Finished May 23 03:18:32 PM PDT 24
Peak memory 289664 kb
Host smart-d5326a8c-c3b0-4379-bebb-697bfbcc126f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175616895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1175616895
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.482047773
Short name T210
Test name
Test status
Simulation time 125147778 ps
CPU time 3.45 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:31:08 PM PDT 24
Peak memory 248932 kb
Host smart-40d38df2-a21a-4c36-b213-d49bbfc0e510
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=482047773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.482047773
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3680006973
Short name T109
Test name
Test status
Simulation time 79309186481 ps
CPU time 1609.36 seconds
Started May 23 02:31:06 PM PDT 24
Finished May 23 02:57:56 PM PDT 24
Peak memory 281624 kb
Host smart-f16de573-eaae-4939-8cf2-2380a1cd90a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680006973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3680006973
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3717984054
Short name T407
Test name
Test status
Simulation time 1330080983 ps
CPU time 17.08 seconds
Started May 23 02:31:07 PM PDT 24
Finished May 23 02:31:25 PM PDT 24
Peak memory 248752 kb
Host smart-4efc0248-3ab5-4ba5-8640-85def6479d51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3717984054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3717984054
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1627908516
Short name T50
Test name
Test status
Simulation time 19693650621 ps
CPU time 272.72 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:35:38 PM PDT 24
Peak memory 256984 kb
Host smart-5f6bad5b-578b-4e7d-9992-bd48dc6a41d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
08516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1627908516
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4172932987
Short name T83
Test name
Test status
Simulation time 1440500287 ps
CPU time 49.93 seconds
Started May 23 02:31:05 PM PDT 24
Finished May 23 02:31:55 PM PDT 24
Peak memory 248760 kb
Host smart-40ea3ee5-02fb-4934-a5d3-b17bd2812d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41729
32987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4172932987
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2347034552
Short name T353
Test name
Test status
Simulation time 95968454802 ps
CPU time 1572.43 seconds
Started May 23 02:31:09 PM PDT 24
Finished May 23 02:57:23 PM PDT 24
Peak memory 289000 kb
Host smart-0f44b11a-1a24-4216-bd91-faa38c3c4cd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347034552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2347034552
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3466593788
Short name T526
Test name
Test status
Simulation time 62106787876 ps
CPU time 1191.94 seconds
Started May 23 02:31:06 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 273256 kb
Host smart-9673b7d5-25ad-45c9-92b5-de93ee46c1ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466593788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3466593788
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4057578303
Short name T454
Test name
Test status
Simulation time 511401324 ps
CPU time 38.34 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:31:43 PM PDT 24
Peak memory 248840 kb
Host smart-d32ce5e0-ae4c-41ac-a7eb-5503937944c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40575
78303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4057578303
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.118125112
Short name T111
Test name
Test status
Simulation time 1317962350 ps
CPU time 40.89 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:31:46 PM PDT 24
Peak memory 248764 kb
Host smart-3885fadb-57e4-4352-b8f5-22b32cdb2771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
5112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.118125112
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2100321546
Short name T508
Test name
Test status
Simulation time 411450667 ps
CPU time 26.28 seconds
Started May 23 02:31:05 PM PDT 24
Finished May 23 02:31:32 PM PDT 24
Peak memory 255544 kb
Host smart-34efc37e-44a6-43fb-9993-f12438f7662a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21003
21546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2100321546
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2032507353
Short name T507
Test name
Test status
Simulation time 16708076 ps
CPU time 3.3 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:30:56 PM PDT 24
Peak memory 240568 kb
Host smart-e17d0ab7-4a6b-423d-af0a-ef7686c89464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325
07353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2032507353
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3207885951
Short name T99
Test name
Test status
Simulation time 19484425754 ps
CPU time 1234.2 seconds
Started May 23 02:31:05 PM PDT 24
Finished May 23 02:51:40 PM PDT 24
Peak memory 272592 kb
Host smart-1de68063-8203-41d2-9496-1473288917e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207885951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3207885951
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3323804794
Short name T593
Test name
Test status
Simulation time 15102802816 ps
CPU time 1645.61 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:58:31 PM PDT 24
Peak memory 300384 kb
Host smart-14cf7df0-8901-4ea7-80fc-bb0152664666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323804794 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3323804794
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2927212201
Short name T245
Test name
Test status
Simulation time 38437183 ps
CPU time 3.65 seconds
Started May 23 02:31:15 PM PDT 24
Finished May 23 02:31:19 PM PDT 24
Peak memory 248932 kb
Host smart-2a710eb6-192e-4c6c-94cf-46f74c84757c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2927212201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2927212201
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4244006039
Short name T534
Test name
Test status
Simulation time 19576474581 ps
CPU time 994.62 seconds
Started May 23 02:31:16 PM PDT 24
Finished May 23 02:47:51 PM PDT 24
Peak memory 272792 kb
Host smart-72f3c557-8b3f-4486-a366-8f4c6fbebe1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244006039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4244006039
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3128759583
Short name T667
Test name
Test status
Simulation time 547044032 ps
CPU time 24.59 seconds
Started May 23 02:31:15 PM PDT 24
Finished May 23 02:31:40 PM PDT 24
Peak memory 248740 kb
Host smart-c18e6be3-b092-4c98-9be9-950b37f4987f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3128759583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3128759583
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1145598668
Short name T434
Test name
Test status
Simulation time 5363293768 ps
CPU time 91.96 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:32:37 PM PDT 24
Peak memory 256952 kb
Host smart-8c03def7-86e5-4adb-af8a-b758e17d6ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
98668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1145598668
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3148578232
Short name T565
Test name
Test status
Simulation time 630862211 ps
CPU time 24.4 seconds
Started May 23 02:31:06 PM PDT 24
Finished May 23 02:31:31 PM PDT 24
Peak memory 248924 kb
Host smart-634d4ade-96c3-4dfb-96a9-f7d3d738243d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
78232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3148578232
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1522512524
Short name T304
Test name
Test status
Simulation time 31232422340 ps
CPU time 1326.11 seconds
Started May 23 02:31:16 PM PDT 24
Finished May 23 02:53:23 PM PDT 24
Peak memory 281564 kb
Host smart-89fc8aed-aeed-4a88-adbe-93cee28128e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522512524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1522512524
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3464425059
Short name T97
Test name
Test status
Simulation time 39672300846 ps
CPU time 2145.28 seconds
Started May 23 02:31:16 PM PDT 24
Finished May 23 03:07:03 PM PDT 24
Peak memory 285220 kb
Host smart-4c2f8bde-7613-4c3b-8cb1-777a7f383b7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464425059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3464425059
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1771944056
Short name T691
Test name
Test status
Simulation time 683137762 ps
CPU time 11.04 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:31:16 PM PDT 24
Peak memory 248784 kb
Host smart-93043ca8-411b-49a7-967e-3aac4fc7ff8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
44056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1771944056
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2364325324
Short name T24
Test name
Test status
Simulation time 840201253 ps
CPU time 56.53 seconds
Started May 23 02:31:05 PM PDT 24
Finished May 23 02:32:02 PM PDT 24
Peak memory 255608 kb
Host smart-c35fd481-656e-4331-87c2-5455e997a30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
25324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2364325324
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1450041963
Short name T256
Test name
Test status
Simulation time 1192548198 ps
CPU time 29.57 seconds
Started May 23 02:31:04 PM PDT 24
Finished May 23 02:31:35 PM PDT 24
Peak memory 255944 kb
Host smart-03dbbdaf-71cd-4846-9c2f-29b4f706e760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14500
41963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1450041963
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3470104275
Short name T634
Test name
Test status
Simulation time 15600646886 ps
CPU time 448.21 seconds
Started May 23 02:31:16 PM PDT 24
Finished May 23 02:38:45 PM PDT 24
Peak memory 257004 kb
Host smart-13ae25ee-860e-4cab-a7fa-be23fadfba1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470104275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3470104275
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3831867381
Short name T113
Test name
Test status
Simulation time 243614193987 ps
CPU time 2574.92 seconds
Started May 23 02:31:26 PM PDT 24
Finished May 23 03:14:21 PM PDT 24
Peak memory 281668 kb
Host smart-dfdb8037-2cbf-4c61-a590-515504f54689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831867381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3831867381
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.268267416
Short name T417
Test name
Test status
Simulation time 2401868973 ps
CPU time 35.28 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 02:32:03 PM PDT 24
Peak memory 248856 kb
Host smart-bf13f8d8-0b83-4c5c-be22-adb99535cc7b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=268267416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.268267416
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1013446351
Short name T403
Test name
Test status
Simulation time 7754103272 ps
CPU time 269.02 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 02:35:56 PM PDT 24
Peak memory 251340 kb
Host smart-a9ba9fe1-4a0d-491f-b079-38bd1b601a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
46351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1013446351
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3106714
Short name T470
Test name
Test status
Simulation time 361310054 ps
CPU time 13.39 seconds
Started May 23 02:31:26 PM PDT 24
Finished May 23 02:31:41 PM PDT 24
Peak memory 252880 kb
Host smart-f0aba4a4-8263-4f8f-93fc-348c4191cb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
14 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3106714
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.55173841
Short name T360
Test name
Test status
Simulation time 90113498252 ps
CPU time 1245.48 seconds
Started May 23 02:31:26 PM PDT 24
Finished May 23 02:52:12 PM PDT 24
Peak memory 284128 kb
Host smart-ec289fc5-b46c-404c-af22-a4728fc26536
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55173841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.55173841
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1183833500
Short name T266
Test name
Test status
Simulation time 41873021063 ps
CPU time 817.02 seconds
Started May 23 02:31:30 PM PDT 24
Finished May 23 02:45:08 PM PDT 24
Peak memory 272208 kb
Host smart-15817fba-b3b5-42f6-a6c8-4c1d683e1b0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183833500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1183833500
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.940524266
Short name T699
Test name
Test status
Simulation time 177167725887 ps
CPU time 619.88 seconds
Started May 23 02:31:26 PM PDT 24
Finished May 23 02:41:47 PM PDT 24
Peak memory 248116 kb
Host smart-a670210b-9791-4483-aee4-32fafe3c4dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940524266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.940524266
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1216397948
Short name T60
Test name
Test status
Simulation time 719720532 ps
CPU time 48.15 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 02:32:16 PM PDT 24
Peak memory 248748 kb
Host smart-33734e02-4614-45a6-819f-abb1427583cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12163
97948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1216397948
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1292288801
Short name T65
Test name
Test status
Simulation time 1452070576 ps
CPU time 26.94 seconds
Started May 23 02:31:27 PM PDT 24
Finished May 23 02:31:55 PM PDT 24
Peak memory 254924 kb
Host smart-1a9d5ad2-085b-4917-89dd-2aec52eacc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
88801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1292288801
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2313630211
Short name T212
Test name
Test status
Simulation time 690778735 ps
CPU time 38.27 seconds
Started May 23 02:31:29 PM PDT 24
Finished May 23 02:32:08 PM PDT 24
Peak memory 248776 kb
Host smart-b9b3d676-b835-453a-b291-67ad978dbc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
30211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2313630211
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3193626424
Short name T483
Test name
Test status
Simulation time 1728188099 ps
CPU time 60.14 seconds
Started May 23 02:31:29 PM PDT 24
Finished May 23 02:32:30 PM PDT 24
Peak memory 248776 kb
Host smart-787f0ce2-0151-42c4-ac01-acc6fd6db5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
26424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3193626424
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1964471126
Short name T516
Test name
Test status
Simulation time 1059259136 ps
CPU time 126.2 seconds
Started May 23 02:31:28 PM PDT 24
Finished May 23 02:33:34 PM PDT 24
Peak memory 250212 kb
Host smart-7f3f45b8-94dc-4f40-b1a1-e3d4d5e19e93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964471126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1964471126
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1870045051
Short name T533
Test name
Test status
Simulation time 13074555807 ps
CPU time 1182.09 seconds
Started May 23 02:31:44 PM PDT 24
Finished May 23 02:51:26 PM PDT 24
Peak memory 289516 kb
Host smart-5192e830-b198-4dde-b0a6-8d7845236a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870045051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1870045051
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1975908512
Short name T391
Test name
Test status
Simulation time 904472625 ps
CPU time 13.12 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:32:11 PM PDT 24
Peak memory 248696 kb
Host smart-7b47bfcf-9d55-40ef-8a97-d6ce919ea89d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1975908512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1975908512
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3953768899
Short name T490
Test name
Test status
Simulation time 4295342149 ps
CPU time 66.02 seconds
Started May 23 02:31:43 PM PDT 24
Finished May 23 02:32:49 PM PDT 24
Peak memory 256864 kb
Host smart-215523e4-8008-469b-81d8-61a205ecab86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
68899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3953768899
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2474934039
Short name T356
Test name
Test status
Simulation time 10398008668 ps
CPU time 876.87 seconds
Started May 23 02:31:46 PM PDT 24
Finished May 23 02:46:24 PM PDT 24
Peak memory 266264 kb
Host smart-f6f48664-8cb4-4a82-a94e-d266f5f6a9ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474934039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2474934039
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1002609539
Short name T431
Test name
Test status
Simulation time 199293448476 ps
CPU time 2994.42 seconds
Started May 23 02:31:45 PM PDT 24
Finished May 23 03:21:40 PM PDT 24
Peak memory 281632 kb
Host smart-d8803993-abdc-4314-a243-b04f0ab40a0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002609539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1002609539
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.463270127
Short name T267
Test name
Test status
Simulation time 237278400 ps
CPU time 25.09 seconds
Started May 23 02:31:28 PM PDT 24
Finished May 23 02:31:54 PM PDT 24
Peak memory 248760 kb
Host smart-04f9a7f4-b592-4dd0-888e-ea03d3c8475c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46327
0127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.463270127
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1896617307
Short name T555
Test name
Test status
Simulation time 685625889 ps
CPU time 48.45 seconds
Started May 23 02:31:28 PM PDT 24
Finished May 23 02:32:17 PM PDT 24
Peak memory 255368 kb
Host smart-7c9a978e-1b00-4dbe-8896-2c7db28e6159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18966
17307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1896617307
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3045711848
Short name T643
Test name
Test status
Simulation time 3991002694 ps
CPU time 40.39 seconds
Started May 23 02:31:43 PM PDT 24
Finished May 23 02:32:24 PM PDT 24
Peak memory 248844 kb
Host smart-ca37884e-307d-46e8-ac59-9fb6b7e88830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
11848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3045711848
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3458459831
Short name T560
Test name
Test status
Simulation time 419190783 ps
CPU time 22.91 seconds
Started May 23 02:31:28 PM PDT 24
Finished May 23 02:31:51 PM PDT 24
Peak memory 248924 kb
Host smart-d452c188-c511-4425-887a-5923f74ba1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
59831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3458459831
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.4101676352
Short name T101
Test name
Test status
Simulation time 127709803956 ps
CPU time 3559.71 seconds
Started May 23 02:31:56 PM PDT 24
Finished May 23 03:31:17 PM PDT 24
Peak memory 321588 kb
Host smart-89827da6-6844-4253-8e01-3ec24d347bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101676352 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.4101676352
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.681140801
Short name T251
Test name
Test status
Simulation time 62980587 ps
CPU time 3.53 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:32:02 PM PDT 24
Peak memory 248956 kb
Host smart-94dd5414-e872-4313-a008-ceceeee09d55
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=681140801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.681140801
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2367087967
Short name T546
Test name
Test status
Simulation time 56989851545 ps
CPU time 1569.85 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:58:08 PM PDT 24
Peak memory 289352 kb
Host smart-21f8640d-d81c-4573-a18e-5513fc1a0001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367087967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2367087967
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3082729279
Short name T475
Test name
Test status
Simulation time 1604986693 ps
CPU time 33.58 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:32:32 PM PDT 24
Peak memory 256784 kb
Host smart-ababb0b3-d4a6-421c-9cbb-638423375723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30827
29279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3082729279
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2485344651
Short name T415
Test name
Test status
Simulation time 75432638 ps
CPU time 7.87 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:32:06 PM PDT 24
Peak memory 253672 kb
Host smart-f708475d-f35b-453c-a3f1-b43b592bde3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24853
44651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2485344651
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1683659454
Short name T584
Test name
Test status
Simulation time 31946801556 ps
CPU time 882.19 seconds
Started May 23 02:31:58 PM PDT 24
Finished May 23 02:46:41 PM PDT 24
Peak memory 267284 kb
Host smart-d98152ea-09ee-4573-aa10-3be06baf8556
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683659454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1683659454
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1352364611
Short name T556
Test name
Test status
Simulation time 29031290861 ps
CPU time 661.26 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:42:59 PM PDT 24
Peak memory 272592 kb
Host smart-81750112-e449-4aeb-871d-94bd85eb34c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352364611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1352364611
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.680541124
Short name T628
Test name
Test status
Simulation time 48170279148 ps
CPU time 506.79 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:40:25 PM PDT 24
Peak memory 248180 kb
Host smart-9edb3fdc-5d24-4ff1-aee1-c3c560fdcc7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680541124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.680541124
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.898597568
Short name T568
Test name
Test status
Simulation time 338790816 ps
CPU time 14.16 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:32:12 PM PDT 24
Peak memory 248588 kb
Host smart-64b28681-fe55-4c54-9305-1f0cec6ad1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89859
7568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.898597568
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1540490021
Short name T75
Test name
Test status
Simulation time 48900746 ps
CPU time 5.43 seconds
Started May 23 02:31:58 PM PDT 24
Finished May 23 02:32:05 PM PDT 24
Peak memory 240580 kb
Host smart-febc580a-3f1c-406a-b5a9-458232a41d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
90021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1540490021
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.867992876
Short name T105
Test name
Test status
Simulation time 2153214144 ps
CPU time 73.4 seconds
Started May 23 02:31:57 PM PDT 24
Finished May 23 02:33:12 PM PDT 24
Peak memory 256704 kb
Host smart-f91efac5-be06-41dc-a88b-82f9880a089f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86799
2876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.867992876
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.906383710
Short name T264
Test name
Test status
Simulation time 1583316045 ps
CPU time 50.26 seconds
Started May 23 02:31:58 PM PDT 24
Finished May 23 02:32:49 PM PDT 24
Peak memory 248772 kb
Host smart-45f67827-5851-45bb-8faf-3f9d8f0da6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90638
3710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.906383710
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3814971552
Short name T590
Test name
Test status
Simulation time 13293636234 ps
CPU time 1646.05 seconds
Started May 23 02:31:58 PM PDT 24
Finished May 23 02:59:25 PM PDT 24
Peak memory 289796 kb
Host smart-98a3a4ff-9c54-48f2-a542-6c58a64d006c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814971552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3814971552
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2578949332
Short name T680
Test name
Test status
Simulation time 38694125968 ps
CPU time 2182.62 seconds
Started May 23 02:32:08 PM PDT 24
Finished May 23 03:08:31 PM PDT 24
Peak memory 273460 kb
Host smart-49fa70a9-c98a-4ded-9b88-09b2d347bff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578949332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2578949332
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2314120274
Short name T596
Test name
Test status
Simulation time 3261895759 ps
CPU time 68.02 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:33:27 PM PDT 24
Peak memory 240636 kb
Host smart-354a2ede-4f35-445c-a3b8-3ae3b7ef73ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2314120274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2314120274
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3697603036
Short name T425
Test name
Test status
Simulation time 2308165619 ps
CPU time 118.44 seconds
Started May 23 02:32:07 PM PDT 24
Finished May 23 02:34:06 PM PDT 24
Peak memory 249956 kb
Host smart-aea4b18c-f5c5-4dff-89fc-95dc6b2d0b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
03036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3697603036
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.592311583
Short name T92
Test name
Test status
Simulation time 1343991646 ps
CPU time 40.87 seconds
Started May 23 02:32:07 PM PDT 24
Finished May 23 02:32:48 PM PDT 24
Peak memory 255592 kb
Host smart-7e4687d4-b8b3-4b78-8edd-68ff0fb3f099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59231
1583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.592311583
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3284087400
Short name T303
Test name
Test status
Simulation time 36883538306 ps
CPU time 2025.35 seconds
Started May 23 02:32:10 PM PDT 24
Finished May 23 03:05:56 PM PDT 24
Peak memory 269600 kb
Host smart-7f6f61cb-4dbd-4c7d-b434-cabbc7844093
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284087400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3284087400
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1931819764
Short name T253
Test name
Test status
Simulation time 38139787651 ps
CPU time 2452.22 seconds
Started May 23 02:32:06 PM PDT 24
Finished May 23 03:13:00 PM PDT 24
Peak memory 281636 kb
Host smart-dc608b8e-855e-48ed-a1f5-af591fb8ede3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931819764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1931819764
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1221922915
Short name T612
Test name
Test status
Simulation time 9300279365 ps
CPU time 122.26 seconds
Started May 23 02:32:07 PM PDT 24
Finished May 23 02:34:10 PM PDT 24
Peak memory 248784 kb
Host smart-70c6e77b-4cf1-4a73-8338-f66ea4b70f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221922915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1221922915
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.531832420
Short name T638
Test name
Test status
Simulation time 344792107 ps
CPU time 24.93 seconds
Started May 23 02:32:08 PM PDT 24
Finished May 23 02:32:33 PM PDT 24
Peak memory 248784 kb
Host smart-f6785978-0045-4980-9cbb-54016425d0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53183
2420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.531832420
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1601791885
Short name T542
Test name
Test status
Simulation time 545648963 ps
CPU time 31.78 seconds
Started May 23 02:32:06 PM PDT 24
Finished May 23 02:32:38 PM PDT 24
Peak memory 249160 kb
Host smart-dc74be5d-f83a-4395-b6e5-77793a11995a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16017
91885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1601791885
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1912595555
Short name T510
Test name
Test status
Simulation time 290228309 ps
CPU time 33.32 seconds
Started May 23 02:32:08 PM PDT 24
Finished May 23 02:32:42 PM PDT 24
Peak memory 256076 kb
Host smart-353e41f1-4059-45f8-b50e-6749d6872c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19125
95555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1912595555
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.682861982
Short name T488
Test name
Test status
Simulation time 1899453565 ps
CPU time 36.53 seconds
Started May 23 02:32:08 PM PDT 24
Finished May 23 02:32:45 PM PDT 24
Peak memory 248776 kb
Host smart-90b1f9d4-7357-430b-884c-58f4a7338d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68286
1982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.682861982
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3295811092
Short name T234
Test name
Test status
Simulation time 77008474 ps
CPU time 2.28 seconds
Started May 23 02:32:24 PM PDT 24
Finished May 23 02:32:27 PM PDT 24
Peak memory 248944 kb
Host smart-ee8553b6-b428-4b27-814a-e29093948e8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3295811092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3295811092
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1478880639
Short name T506
Test name
Test status
Simulation time 37251386878 ps
CPU time 1193.39 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:52:13 PM PDT 24
Peak memory 265216 kb
Host smart-ea4cab7b-455d-486a-8cd6-95dca08940d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478880639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1478880639
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1327487252
Short name T108
Test name
Test status
Simulation time 269698594 ps
CPU time 14.17 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:32:33 PM PDT 24
Peak memory 248744 kb
Host smart-d6d0d4fc-7a1a-4ea6-9f94-35c4db767781
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1327487252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1327487252
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4102518933
Short name T414
Test name
Test status
Simulation time 2030577915 ps
CPU time 100.98 seconds
Started May 23 02:32:20 PM PDT 24
Finished May 23 02:34:02 PM PDT 24
Peak memory 256812 kb
Host smart-152cbf8e-99b7-4408-82be-245f9b93d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025
18933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4102518933
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1300027183
Short name T71
Test name
Test status
Simulation time 56457997 ps
CPU time 3.45 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:32:23 PM PDT 24
Peak memory 240600 kb
Host smart-f5280954-cb1d-4c4b-ae50-ed639f5e91f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
27183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1300027183
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.584850448
Short name T623
Test name
Test status
Simulation time 25083383420 ps
CPU time 1282.64 seconds
Started May 23 02:32:18 PM PDT 24
Finished May 23 02:53:41 PM PDT 24
Peak memory 265204 kb
Host smart-270a6a47-ff66-4c67-a942-c25dcb943799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584850448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.584850448
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.408860362
Short name T386
Test name
Test status
Simulation time 57105626069 ps
CPU time 1070.26 seconds
Started May 23 02:32:20 PM PDT 24
Finished May 23 02:50:11 PM PDT 24
Peak memory 283136 kb
Host smart-2b89ed28-7a60-4008-aa0e-93428071104e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408860362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.408860362
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3945911473
Short name T663
Test name
Test status
Simulation time 15798849319 ps
CPU time 106.92 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:34:06 PM PDT 24
Peak memory 248204 kb
Host smart-a141c5b4-3714-431b-bb4e-e31305454f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945911473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3945911473
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4181727058
Short name T689
Test name
Test status
Simulation time 1234082989 ps
CPU time 24.98 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:32:45 PM PDT 24
Peak memory 248784 kb
Host smart-6b10b233-9295-4a03-827a-d9491ab8be50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41817
27058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4181727058
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1206686781
Short name T389
Test name
Test status
Simulation time 714652521 ps
CPU time 31.18 seconds
Started May 23 02:32:20 PM PDT 24
Finished May 23 02:32:51 PM PDT 24
Peak memory 254900 kb
Host smart-be0e7b06-5f94-4278-ae6a-7ec3c6951fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12066
86781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1206686781
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.910110834
Short name T537
Test name
Test status
Simulation time 1180877071 ps
CPU time 38.22 seconds
Started May 23 02:32:24 PM PDT 24
Finished May 23 02:33:03 PM PDT 24
Peak memory 248776 kb
Host smart-5cd7a5f3-51a3-440b-b844-c032740e9d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91011
0834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.910110834
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.295076384
Short name T445
Test name
Test status
Simulation time 302201869737 ps
CPU time 2452.65 seconds
Started May 23 02:32:20 PM PDT 24
Finished May 23 03:13:13 PM PDT 24
Peak memory 289556 kb
Host smart-31cad7bb-1cb9-48a6-8bf5-df79879862b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295076384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.295076384
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3988583164
Short name T250
Test name
Test status
Simulation time 85668357 ps
CPU time 3.75 seconds
Started May 23 02:32:31 PM PDT 24
Finished May 23 02:32:35 PM PDT 24
Peak memory 248920 kb
Host smart-fffcb4ba-d78d-46ba-82f2-f0b8fbfae73b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3988583164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3988583164
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.931912701
Short name T321
Test name
Test status
Simulation time 28688236742 ps
CPU time 993.85 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 02:49:07 PM PDT 24
Peak memory 273404 kb
Host smart-a92ee13d-86eb-40ca-89b6-9d07deff871c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931912701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.931912701
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1635461017
Short name T231
Test name
Test status
Simulation time 136490951 ps
CPU time 8.59 seconds
Started May 23 02:32:31 PM PDT 24
Finished May 23 02:32:40 PM PDT 24
Peak memory 248784 kb
Host smart-4f9cf8b5-b3b7-419b-927c-bd71b39a80dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635461017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1635461017
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1898634241
Short name T683
Test name
Test status
Simulation time 24685875291 ps
CPU time 228.38 seconds
Started May 23 02:32:31 PM PDT 24
Finished May 23 02:36:20 PM PDT 24
Peak memory 250924 kb
Host smart-313da4d8-f4d7-4fe1-9e29-85e9c70a990a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
34241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1898634241
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3946196794
Short name T632
Test name
Test status
Simulation time 4336150743 ps
CPU time 71.6 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 02:33:44 PM PDT 24
Peak memory 256860 kb
Host smart-95cb238e-0584-4c55-9b93-bdd9c302e315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39461
96794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3946196794
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.360458195
Short name T310
Test name
Test status
Simulation time 17524530085 ps
CPU time 890.34 seconds
Started May 23 02:32:31 PM PDT 24
Finished May 23 02:47:22 PM PDT 24
Peak memory 271776 kb
Host smart-ba0f328c-08ad-4238-beb3-6b4e7ea5dfa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360458195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.360458195
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1691667404
Short name T598
Test name
Test status
Simulation time 14189465954 ps
CPU time 486.59 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 02:40:39 PM PDT 24
Peak memory 248116 kb
Host smart-d3f54299-5f50-4691-b661-626ccff13d71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691667404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1691667404
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1252669849
Short name T576
Test name
Test status
Simulation time 929181568 ps
CPU time 40.2 seconds
Started May 23 02:32:33 PM PDT 24
Finished May 23 02:33:14 PM PDT 24
Peak memory 256408 kb
Host smart-89227283-cefd-43e5-94da-fdc0c9085354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12526
69849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1252669849
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1680610261
Short name T561
Test name
Test status
Simulation time 725824241 ps
CPU time 16.15 seconds
Started May 23 02:32:32 PM PDT 24
Finished May 23 02:32:49 PM PDT 24
Peak memory 249252 kb
Host smart-83f4e426-44bf-4e72-b023-debb165d540a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16806
10261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1680610261
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3361115242
Short name T595
Test name
Test status
Simulation time 1637741223 ps
CPU time 51.25 seconds
Started May 23 02:32:33 PM PDT 24
Finished May 23 02:33:25 PM PDT 24
Peak memory 247616 kb
Host smart-52fe71da-fb0b-49a5-b0dc-90416cecd5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
15242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3361115242
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1665983567
Short name T464
Test name
Test status
Simulation time 770071597 ps
CPU time 51.63 seconds
Started May 23 02:32:19 PM PDT 24
Finished May 23 02:33:12 PM PDT 24
Peak memory 248764 kb
Host smart-dca854cb-086c-4481-a5f0-c1a05aab18f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
83567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1665983567
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1459490587
Short name T237
Test name
Test status
Simulation time 113123353 ps
CPU time 3.76 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:32:47 PM PDT 24
Peak memory 248868 kb
Host smart-0e22abaa-9c4c-489d-bab3-a4d24d7a37cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459490587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1459490587
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3566954552
Short name T531
Test name
Test status
Simulation time 342077876 ps
CPU time 16.21 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:32:58 PM PDT 24
Peak memory 248772 kb
Host smart-2e287e01-7a82-4c37-97d1-3e9981d112a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3566954552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3566954552
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.679637460
Short name T649
Test name
Test status
Simulation time 4034200937 ps
CPU time 245.15 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:36:48 PM PDT 24
Peak memory 250984 kb
Host smart-952e9d72-ef64-4b5b-9c78-c4e0e7ada77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67963
7460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.679637460
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4062836681
Short name T625
Test name
Test status
Simulation time 265802963 ps
CPU time 29.08 seconds
Started May 23 02:32:41 PM PDT 24
Finished May 23 02:33:11 PM PDT 24
Peak memory 248788 kb
Host smart-d19cdcae-9282-4671-9d13-54db8d6d1969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
36681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4062836681
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2991970020
Short name T686
Test name
Test status
Simulation time 66762202337 ps
CPU time 1764.07 seconds
Started May 23 02:32:43 PM PDT 24
Finished May 23 03:02:08 PM PDT 24
Peak memory 266232 kb
Host smart-864b8352-2a98-4d36-af4e-c5bc66a42c48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991970020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2991970020
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2654192586
Short name T106
Test name
Test status
Simulation time 144686959063 ps
CPU time 1628.92 seconds
Started May 23 02:32:43 PM PDT 24
Finished May 23 02:59:52 PM PDT 24
Peak memory 272828 kb
Host smart-17031168-f82d-44e4-87db-2800caff5171
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654192586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2654192586
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1073061915
Short name T669
Test name
Test status
Simulation time 17339354950 ps
CPU time 349.16 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:38:32 PM PDT 24
Peak memory 254580 kb
Host smart-d412d359-9a22-4161-8fd8-2da9454c07f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073061915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1073061915
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.928208038
Short name T44
Test name
Test status
Simulation time 2864192242 ps
CPU time 52.12 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:33:35 PM PDT 24
Peak memory 248828 kb
Host smart-e4d6e01a-580f-4c6c-b22e-22e5bf907380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92820
8038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.928208038
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1396641129
Short name T588
Test name
Test status
Simulation time 63254333 ps
CPU time 3.57 seconds
Started May 23 02:32:44 PM PDT 24
Finished May 23 02:32:48 PM PDT 24
Peak memory 240564 kb
Host smart-6218a476-36dc-4a3f-84f0-935b683bf13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
41129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1396641129
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3549843417
Short name T275
Test name
Test status
Simulation time 1067693701 ps
CPU time 35.79 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:33:19 PM PDT 24
Peak memory 256068 kb
Host smart-9beaca38-7cef-4997-9aa3-d512ccf0ca63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35498
43417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3549843417
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3739449156
Short name T22
Test name
Test status
Simulation time 991299254 ps
CPU time 62.68 seconds
Started May 23 02:32:42 PM PDT 24
Finished May 23 02:33:46 PM PDT 24
Peak memory 248776 kb
Host smart-be94cf2a-730d-4268-bda5-cc63c3fb7234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
49156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3739449156
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3260143196
Short name T489
Test name
Test status
Simulation time 1196828884 ps
CPU time 68.28 seconds
Started May 23 02:32:43 PM PDT 24
Finished May 23 02:33:52 PM PDT 24
Peak memory 255424 kb
Host smart-19f82900-9262-481a-970b-1eaf60fb0b96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260143196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3260143196
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3595195431
Short name T41
Test name
Test status
Simulation time 113738320337 ps
CPU time 3053.52 seconds
Started May 23 02:32:43 PM PDT 24
Finished May 23 03:23:37 PM PDT 24
Peak memory 321416 kb
Host smart-00737384-573e-4dfa-812e-c00461b496fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595195431 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3595195431
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.289938286
Short name T238
Test name
Test status
Simulation time 24580474 ps
CPU time 2.37 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:33:11 PM PDT 24
Peak memory 248744 kb
Host smart-79375a41-b41e-4993-aee5-2f0cecf039ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289938286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.289938286
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3945123346
Short name T394
Test name
Test status
Simulation time 582449883 ps
CPU time 12.69 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:33:09 PM PDT 24
Peak memory 248772 kb
Host smart-37e67bea-5fc5-49c1-96c0-96c64e0a4bcd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3945123346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3945123346
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.142623791
Short name T419
Test name
Test status
Simulation time 3444155358 ps
CPU time 208.46 seconds
Started May 23 02:32:56 PM PDT 24
Finished May 23 02:36:25 PM PDT 24
Peak memory 256960 kb
Host smart-5f3803c1-33cf-4ebd-8cf0-243b9ed4ab50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
3791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.142623791
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3923025656
Short name T42
Test name
Test status
Simulation time 1014633530 ps
CPU time 37.23 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:33:33 PM PDT 24
Peak memory 248892 kb
Host smart-d1549aa1-28c2-455e-9135-45f2a8afa303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230
25656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3923025656
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1536989295
Short name T514
Test name
Test status
Simulation time 25132438812 ps
CPU time 1118.07 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:51:34 PM PDT 24
Peak memory 281176 kb
Host smart-cfdae52c-7eac-4bef-b3de-abdc4c03649d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536989295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1536989295
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2468399254
Short name T610
Test name
Test status
Simulation time 44133057333 ps
CPU time 452.74 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:40:29 PM PDT 24
Peak memory 254960 kb
Host smart-b6b1a325-d315-4cee-9279-806b47d57d19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468399254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2468399254
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2678191978
Short name T566
Test name
Test status
Simulation time 366008220 ps
CPU time 24.84 seconds
Started May 23 02:32:59 PM PDT 24
Finished May 23 02:33:24 PM PDT 24
Peak memory 248764 kb
Host smart-1fc1cbb5-180f-4734-b3a1-8a6f01d6adda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
91978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2678191978
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2526191243
Short name T701
Test name
Test status
Simulation time 1513461384 ps
CPU time 66.25 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:34:02 PM PDT 24
Peak memory 256200 kb
Host smart-280709a6-5e10-4c7c-b135-4cd1329a6400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
91243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2526191243
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3258917832
Short name T90
Test name
Test status
Simulation time 1091213572 ps
CPU time 41.53 seconds
Started May 23 02:32:56 PM PDT 24
Finished May 23 02:33:38 PM PDT 24
Peak memory 248744 kb
Host smart-6c4ee623-72d6-4f74-99b7-44e39823877e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
17832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3258917832
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.852103796
Short name T672
Test name
Test status
Simulation time 194294345 ps
CPU time 20.39 seconds
Started May 23 02:32:55 PM PDT 24
Finished May 23 02:33:16 PM PDT 24
Peak memory 248772 kb
Host smart-94570734-1aed-4867-a078-d9b0737193d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85210
3796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.852103796
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.850527797
Short name T19
Test name
Test status
Simulation time 1842781417 ps
CPU time 32.05 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:33:40 PM PDT 24
Peak memory 247988 kb
Host smart-da82a6a0-5935-4c1d-9405-c5da9cabea82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850527797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.850527797
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3444297085
Short name T249
Test name
Test status
Simulation time 24156109 ps
CPU time 2.8 seconds
Started May 23 02:29:00 PM PDT 24
Finished May 23 02:29:04 PM PDT 24
Peak memory 248764 kb
Host smart-067b03f2-a775-4a96-9914-2ee5e56bd031
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3444297085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3444297085
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1678045068
Short name T706
Test name
Test status
Simulation time 211257375858 ps
CPU time 2227.75 seconds
Started May 23 02:29:01 PM PDT 24
Finished May 23 03:06:11 PM PDT 24
Peak memory 287184 kb
Host smart-9165f137-8b2d-4cc1-9970-550f6443f18e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678045068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1678045068
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3774222113
Short name T614
Test name
Test status
Simulation time 940837451 ps
CPU time 10.38 seconds
Started May 23 02:29:00 PM PDT 24
Finished May 23 02:29:11 PM PDT 24
Peak memory 240580 kb
Host smart-443c32ad-3ae6-41d7-b955-a3e939850dd1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3774222113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3774222113
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1909047804
Short name T682
Test name
Test status
Simulation time 1847008636 ps
CPU time 34.06 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:29:24 PM PDT 24
Peak memory 255000 kb
Host smart-063f5ed2-fff3-4831-b492-0051adcec6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
47804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1909047804
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2274037096
Short name T3
Test name
Test status
Simulation time 1986328681 ps
CPU time 60.21 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:29:50 PM PDT 24
Peak memory 249088 kb
Host smart-b79aaab4-ce40-43f0-8a2d-3621acbb1c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22740
37096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2274037096
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4184068921
Short name T98
Test name
Test status
Simulation time 708745195358 ps
CPU time 2476.6 seconds
Started May 23 02:29:00 PM PDT 24
Finished May 23 03:10:18 PM PDT 24
Peak memory 288988 kb
Host smart-cbc551c2-eddc-4634-8cb5-a5e0a1a1c11d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184068921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4184068921
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1181847929
Short name T232
Test name
Test status
Simulation time 19493274087 ps
CPU time 713.96 seconds
Started May 23 02:29:00 PM PDT 24
Finished May 23 02:40:55 PM PDT 24
Peak memory 266412 kb
Host smart-eacb4bd4-3021-46e6-9e30-6b7e86cadf03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181847929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1181847929
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3147878866
Short name T459
Test name
Test status
Simulation time 9636388302 ps
CPU time 62.95 seconds
Started May 23 02:28:48 PM PDT 24
Finished May 23 02:29:51 PM PDT 24
Peak memory 248752 kb
Host smart-1a6078d6-78aa-4506-b37e-7afe8c10fc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
78866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3147878866
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3487288619
Short name T644
Test name
Test status
Simulation time 1213713178 ps
CPU time 36.4 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:29:26 PM PDT 24
Peak memory 254960 kb
Host smart-e8b173ff-cb80-42d7-a3ae-ee358095efdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34872
88619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3487288619
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2789495438
Short name T35
Test name
Test status
Simulation time 711131353 ps
CPU time 12.86 seconds
Started May 23 02:29:12 PM PDT 24
Finished May 23 02:29:26 PM PDT 24
Peak memory 265296 kb
Host smart-0ab5ac4a-4f21-4bba-9701-3071c4158193
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2789495438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2789495438
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3865008688
Short name T665
Test name
Test status
Simulation time 170903403 ps
CPU time 7.5 seconds
Started May 23 02:28:48 PM PDT 24
Finished May 23 02:28:56 PM PDT 24
Peak memory 251000 kb
Host smart-f8d9260b-42a5-42b9-b1b9-cdc7aaf25992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
08688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3865008688
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1717430151
Short name T635
Test name
Test status
Simulation time 254075876 ps
CPU time 25.39 seconds
Started May 23 02:28:49 PM PDT 24
Finished May 23 02:29:16 PM PDT 24
Peak memory 248748 kb
Host smart-6ea43093-1dc7-4e66-a0ea-da1a33d4bbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17174
30151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1717430151
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3555356344
Short name T277
Test name
Test status
Simulation time 116407192173 ps
CPU time 8016.96 seconds
Started May 23 02:29:12 PM PDT 24
Finished May 23 04:42:51 PM PDT 24
Peak memory 314556 kb
Host smart-0b3a2261-d3dc-4a01-914a-861a25690531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555356344 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3555356344
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3157449082
Short name T500
Test name
Test status
Simulation time 7763898150 ps
CPU time 956.77 seconds
Started May 23 02:33:06 PM PDT 24
Finished May 23 02:49:04 PM PDT 24
Peak memory 273392 kb
Host smart-7a47b110-1909-420b-b28c-dc62e7637dd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157449082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3157449082
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3271964960
Short name T95
Test name
Test status
Simulation time 21512548008 ps
CPU time 309.47 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:38:18 PM PDT 24
Peak memory 256664 kb
Host smart-9a9b49b5-5045-4198-a341-931b40e3b07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32719
64960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3271964960
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1183954463
Short name T382
Test name
Test status
Simulation time 768358419 ps
CPU time 54.7 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:34:03 PM PDT 24
Peak memory 248728 kb
Host smart-a148d998-1b90-40e5-933a-54f64501b281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11839
54463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1183954463
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.965143856
Short name T575
Test name
Test status
Simulation time 13866241369 ps
CPU time 1362.23 seconds
Started May 23 02:33:11 PM PDT 24
Finished May 23 02:55:54 PM PDT 24
Peak memory 273416 kb
Host smart-5b51ef13-0f20-4877-939f-10c8ed7e2cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965143856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.965143856
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1590361291
Short name T702
Test name
Test status
Simulation time 20923223870 ps
CPU time 1045.89 seconds
Started May 23 02:33:19 PM PDT 24
Finished May 23 02:50:46 PM PDT 24
Peak memory 273424 kb
Host smart-3a9ab551-91e1-4a82-b944-97cb09972363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590361291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1590361291
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3896871412
Short name T338
Test name
Test status
Simulation time 6085687546 ps
CPU time 251.51 seconds
Started May 23 02:33:09 PM PDT 24
Finished May 23 02:37:21 PM PDT 24
Peak memory 248816 kb
Host smart-6141c0cd-6a79-471c-be1b-1ecb94aa388b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896871412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3896871412
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1035603566
Short name T639
Test name
Test status
Simulation time 662924452 ps
CPU time 30.87 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:33:39 PM PDT 24
Peak memory 248744 kb
Host smart-983990d0-0350-4693-b79a-c1c92083260f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10356
03566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1035603566
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3684100669
Short name T655
Test name
Test status
Simulation time 1733691400 ps
CPU time 10.25 seconds
Started May 23 02:33:11 PM PDT 24
Finished May 23 02:33:22 PM PDT 24
Peak memory 251132 kb
Host smart-e5fb4124-8408-4f96-a287-2b4ba302c8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841
00669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3684100669
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1662859561
Short name T88
Test name
Test status
Simulation time 1087892240 ps
CPU time 67.08 seconds
Started May 23 02:33:07 PM PDT 24
Finished May 23 02:34:15 PM PDT 24
Peak memory 254816 kb
Host smart-6183618f-e66f-4337-af9d-b00064cd8760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
59561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1662859561
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2469555481
Short name T466
Test name
Test status
Simulation time 2230809423 ps
CPU time 68.06 seconds
Started May 23 02:33:06 PM PDT 24
Finished May 23 02:34:15 PM PDT 24
Peak memory 248820 kb
Host smart-625d9fa9-9f95-4f24-b7b2-4ccf7fb77a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24695
55481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2469555481
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3849179139
Short name T640
Test name
Test status
Simulation time 10551858275 ps
CPU time 1516 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:58:37 PM PDT 24
Peak memory 281660 kb
Host smart-24119804-df50-4bee-9293-adefbfe5ae21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849179139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3849179139
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2565500582
Short name T524
Test name
Test status
Simulation time 502050485 ps
CPU time 8.14 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:33:29 PM PDT 24
Peak memory 251148 kb
Host smart-5eb7eea6-5f91-402a-a1aa-6b723d355fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
00582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2565500582
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3737591265
Short name T511
Test name
Test status
Simulation time 935821318 ps
CPU time 13.11 seconds
Started May 23 02:33:21 PM PDT 24
Finished May 23 02:33:35 PM PDT 24
Peak memory 248764 kb
Host smart-34b33fa0-0274-41ef-baae-86d719ebf8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
91265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3737591265
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1723486151
Short name T609
Test name
Test status
Simulation time 81180573264 ps
CPU time 2685.5 seconds
Started May 23 02:33:19 PM PDT 24
Finished May 23 03:18:05 PM PDT 24
Peak memory 289092 kb
Host smart-f73da4dd-4252-4202-ba62-85672902a6a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723486151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1723486151
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3278323166
Short name T252
Test name
Test status
Simulation time 14884236365 ps
CPU time 1382.46 seconds
Started May 23 02:33:42 PM PDT 24
Finished May 23 02:56:46 PM PDT 24
Peak memory 289172 kb
Host smart-d9bf8141-1098-4942-8827-af6b5b38dcdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278323166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3278323166
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3242394101
Short name T670
Test name
Test status
Simulation time 107613647 ps
CPU time 12.11 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:33:33 PM PDT 24
Peak memory 248752 kb
Host smart-b602f134-43a1-4f5d-a520-b2957b37b1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32423
94101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3242394101
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2153008581
Short name T552
Test name
Test status
Simulation time 228554119 ps
CPU time 6.82 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:33:27 PM PDT 24
Peak memory 248780 kb
Host smart-138d2b5b-5bfe-47bd-9b1c-502ce8003a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
08581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2153008581
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.64688497
Short name T255
Test name
Test status
Simulation time 348586601 ps
CPU time 35.79 seconds
Started May 23 02:33:21 PM PDT 24
Finished May 23 02:33:58 PM PDT 24
Peak memory 255608 kb
Host smart-c77da444-bb09-455a-887c-0ef9edd945b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64688
497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.64688497
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3464344916
Short name T432
Test name
Test status
Simulation time 1157971409 ps
CPU time 65.85 seconds
Started May 23 02:33:20 PM PDT 24
Finished May 23 02:34:27 PM PDT 24
Peak memory 248788 kb
Host smart-29c6a89d-2bd1-4fa6-99b2-5ade99eddfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
44916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3464344916
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2285413084
Short name T1
Test name
Test status
Simulation time 20740687906 ps
CPU time 1233.04 seconds
Started May 23 02:33:40 PM PDT 24
Finished May 23 02:54:14 PM PDT 24
Peak memory 265236 kb
Host smart-78afe40f-f0b5-4594-a174-4856f040589d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285413084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2285413084
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2104681210
Short name T224
Test name
Test status
Simulation time 3700611149 ps
CPU time 207.76 seconds
Started May 23 02:33:37 PM PDT 24
Finished May 23 02:37:05 PM PDT 24
Peak memory 257008 kb
Host smart-4a04280f-8f5f-4a76-9284-73e95177c855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046
81210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2104681210
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4064319913
Short name T448
Test name
Test status
Simulation time 6061572409 ps
CPU time 20 seconds
Started May 23 02:33:42 PM PDT 24
Finished May 23 02:34:03 PM PDT 24
Peak memory 255232 kb
Host smart-2df24c00-4f93-4f1b-a5f8-62b4b05eda63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40643
19913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4064319913
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1382124224
Short name T325
Test name
Test status
Simulation time 107383673821 ps
CPU time 1000.03 seconds
Started May 23 02:33:44 PM PDT 24
Finished May 23 02:50:25 PM PDT 24
Peak memory 272624 kb
Host smart-78d4c48e-655a-4866-b77a-79c3d79a01a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382124224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1382124224
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3258717748
Short name T51
Test name
Test status
Simulation time 194650426145 ps
CPU time 3031.92 seconds
Started May 23 02:33:34 PM PDT 24
Finished May 23 03:24:07 PM PDT 24
Peak memory 289748 kb
Host smart-d89ec7ba-5232-4fe4-90e5-8adf524fe8ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258717748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3258717748
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2975846550
Short name T350
Test name
Test status
Simulation time 76481117458 ps
CPU time 356.53 seconds
Started May 23 02:33:37 PM PDT 24
Finished May 23 02:39:34 PM PDT 24
Peak memory 255120 kb
Host smart-a712c3a8-9a0f-4811-8cdf-73ae5260a2cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975846550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2975846550
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2989136560
Short name T690
Test name
Test status
Simulation time 291010320 ps
CPU time 23.22 seconds
Started May 23 02:33:37 PM PDT 24
Finished May 23 02:34:01 PM PDT 24
Peak memory 256944 kb
Host smart-8d360960-1024-4bbe-8b8a-9766f66e8a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
36560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2989136560
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.32679499
Short name T134
Test name
Test status
Simulation time 2730155173 ps
CPU time 29.08 seconds
Started May 23 02:33:40 PM PDT 24
Finished May 23 02:34:10 PM PDT 24
Peak memory 247508 kb
Host smart-10f784cd-e54c-4252-8f5a-ab7e6e5b1e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32679
499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.32679499
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2224704004
Short name T61
Test name
Test status
Simulation time 263310930 ps
CPU time 25.83 seconds
Started May 23 02:33:38 PM PDT 24
Finished May 23 02:34:04 PM PDT 24
Peak memory 248796 kb
Host smart-c2ea2087-0977-4549-a031-3191769d3895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247
04004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2224704004
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.567622942
Short name T540
Test name
Test status
Simulation time 564668959 ps
CPU time 30.68 seconds
Started May 23 02:33:36 PM PDT 24
Finished May 23 02:34:07 PM PDT 24
Peak memory 248784 kb
Host smart-4bbd5878-6b7b-46b4-9192-502b3f85b082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56762
2942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.567622942
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3776510561
Short name T463
Test name
Test status
Simulation time 32382789262 ps
CPU time 173.77 seconds
Started May 23 02:33:32 PM PDT 24
Finished May 23 02:36:26 PM PDT 24
Peak memory 256860 kb
Host smart-9a3a044e-9406-4b3f-82fa-90f5221f6582
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776510561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3776510561
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1331275398
Short name T58
Test name
Test status
Simulation time 160225758516 ps
CPU time 4062.4 seconds
Started May 23 02:33:37 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 338420 kb
Host smart-95058221-c6c6-4c35-9c5a-bd54c109aea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331275398 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1331275398
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1671822333
Short name T315
Test name
Test status
Simulation time 8328778343 ps
CPU time 1185.27 seconds
Started May 23 02:33:52 PM PDT 24
Finished May 23 02:53:38 PM PDT 24
Peak memory 273040 kb
Host smart-fb9dcc92-20b0-4808-8bab-e4aef959259f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671822333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1671822333
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1902464463
Short name T637
Test name
Test status
Simulation time 4563024437 ps
CPU time 92.61 seconds
Started May 23 02:33:53 PM PDT 24
Finished May 23 02:35:27 PM PDT 24
Peak memory 249972 kb
Host smart-b231305b-9a7a-44cf-ac25-f1208f0aff82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
64463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1902464463
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1227916457
Short name T461
Test name
Test status
Simulation time 1270300956 ps
CPU time 67.85 seconds
Started May 23 02:33:56 PM PDT 24
Finished May 23 02:35:04 PM PDT 24
Peak memory 248780 kb
Host smart-aaae2063-42a2-47dd-9fe8-3bac24e99a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
16457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1227916457
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3259047241
Short name T324
Test name
Test status
Simulation time 176571683293 ps
CPU time 2530.47 seconds
Started May 23 02:33:54 PM PDT 24
Finished May 23 03:16:05 PM PDT 24
Peak memory 283388 kb
Host smart-cf8bfe31-d177-4952-9c84-d1cb242ff222
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259047241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3259047241
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2943975423
Short name T437
Test name
Test status
Simulation time 13178515573 ps
CPU time 1404.9 seconds
Started May 23 02:33:51 PM PDT 24
Finished May 23 02:57:16 PM PDT 24
Peak memory 289108 kb
Host smart-3881e6d0-b608-41b8-a163-98a97a027f0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943975423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2943975423
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3072101923
Short name T603
Test name
Test status
Simulation time 279891269 ps
CPU time 16.68 seconds
Started May 23 02:33:52 PM PDT 24
Finished May 23 02:34:10 PM PDT 24
Peak memory 256764 kb
Host smart-be07879c-a6a5-4a4f-b410-22bcfe207b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
01923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3072101923
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2074642421
Short name T558
Test name
Test status
Simulation time 4360922514 ps
CPU time 39.71 seconds
Started May 23 02:33:54 PM PDT 24
Finished May 23 02:34:35 PM PDT 24
Peak memory 256144 kb
Host smart-722a381f-ab7f-468b-a3fa-84c7c9b79de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
42421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2074642421
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3266456676
Short name T435
Test name
Test status
Simulation time 91350948 ps
CPU time 12.56 seconds
Started May 23 02:33:53 PM PDT 24
Finished May 23 02:34:06 PM PDT 24
Peak memory 247516 kb
Host smart-c52d6b1b-a729-4181-adca-66914bab2c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32664
56676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3266456676
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2527841964
Short name T208
Test name
Test status
Simulation time 5111829911 ps
CPU time 30.05 seconds
Started May 23 02:33:32 PM PDT 24
Finished May 23 02:34:02 PM PDT 24
Peak memory 256652 kb
Host smart-36198c6c-249c-4e90-8427-eb737d1820da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278
41964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2527841964
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4189672536
Short name T443
Test name
Test status
Simulation time 34679303246 ps
CPU time 484.51 seconds
Started May 23 02:34:02 PM PDT 24
Finished May 23 02:42:08 PM PDT 24
Peak memory 257000 kb
Host smart-5f04ef3e-c336-4114-83f6-255c71ef8438
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189672536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4189672536
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3111492126
Short name T316
Test name
Test status
Simulation time 165826089612 ps
CPU time 2553.06 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 03:16:35 PM PDT 24
Peak memory 288888 kb
Host smart-ca277903-20c9-4c63-94ae-cc81da784e0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111492126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3111492126
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.509063727
Short name T657
Test name
Test status
Simulation time 1959459812 ps
CPU time 142.06 seconds
Started May 23 02:34:03 PM PDT 24
Finished May 23 02:36:26 PM PDT 24
Peak memory 250836 kb
Host smart-02b814b3-7a7a-429c-9c2b-27370f78dedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50906
3727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.509063727
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1367833170
Short name T283
Test name
Test status
Simulation time 3430163004 ps
CPU time 52.42 seconds
Started May 23 02:34:02 PM PDT 24
Finished May 23 02:34:55 PM PDT 24
Peak memory 255620 kb
Host smart-d993e0fa-f509-4d62-a9d5-c672ad71cbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
33170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1367833170
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1456640271
Short name T453
Test name
Test status
Simulation time 12914739153 ps
CPU time 1248.06 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 02:54:50 PM PDT 24
Peak memory 287676 kb
Host smart-ae38f3db-7c52-402c-a720-66802e04663e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456640271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1456640271
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2353800764
Short name T127
Test name
Test status
Simulation time 5535439489 ps
CPU time 235.42 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 02:37:57 PM PDT 24
Peak memory 248820 kb
Host smart-605d5d17-277c-4588-b4b8-83e486d44d35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353800764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2353800764
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2496875088
Short name T46
Test name
Test status
Simulation time 2793241538 ps
CPU time 54.33 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 02:34:56 PM PDT 24
Peak memory 248816 kb
Host smart-36cccf37-0284-4100-94ce-f58c9f0913f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24968
75088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2496875088
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.510905439
Short name T138
Test name
Test status
Simulation time 3154395679 ps
CPU time 54.66 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 02:34:57 PM PDT 24
Peak memory 248700 kb
Host smart-dbd89523-26fa-44ee-8af3-77e4cd0c9e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51090
5439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.510905439
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1890760979
Short name T93
Test name
Test status
Simulation time 50865238 ps
CPU time 5.85 seconds
Started May 23 02:34:03 PM PDT 24
Finished May 23 02:34:09 PM PDT 24
Peak memory 253920 kb
Host smart-5d777bef-bd31-4ad6-9679-ae2542e9d031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18907
60979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1890760979
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1364122499
Short name T21
Test name
Test status
Simulation time 649111898 ps
CPU time 12.7 seconds
Started May 23 02:34:01 PM PDT 24
Finished May 23 02:34:15 PM PDT 24
Peak memory 248772 kb
Host smart-c67e8dbd-d133-4d54-a9ab-937fc7bcdc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
22499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1364122499
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2493664796
Short name T276
Test name
Test status
Simulation time 3782555647 ps
CPU time 223.68 seconds
Started May 23 02:34:00 PM PDT 24
Finished May 23 02:37:45 PM PDT 24
Peak memory 257012 kb
Host smart-2978bd3d-961b-489c-817b-d98a789d36d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493664796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2493664796
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1654861093
Short name T119
Test name
Test status
Simulation time 20250693513 ps
CPU time 2054.19 seconds
Started May 23 02:34:14 PM PDT 24
Finished May 23 03:08:29 PM PDT 24
Peak memory 305672 kb
Host smart-1d4aef77-aefa-4956-92d8-83de0629cf01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654861093 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1654861093
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4170525543
Short name T118
Test name
Test status
Simulation time 49244342839 ps
CPU time 3110.89 seconds
Started May 23 02:34:15 PM PDT 24
Finished May 23 03:26:07 PM PDT 24
Peak memory 286504 kb
Host smart-5a13f31d-c0ef-4241-87a8-f2050f857a5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170525543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4170525543
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.670763014
Short name T67
Test name
Test status
Simulation time 401230955 ps
CPU time 27.2 seconds
Started May 23 02:34:14 PM PDT 24
Finished May 23 02:34:42 PM PDT 24
Peak memory 248748 kb
Host smart-5c5eac80-2f23-4644-b6b2-4db6fea9c150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67076
3014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.670763014
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3359742885
Short name T607
Test name
Test status
Simulation time 1252755949 ps
CPU time 68.25 seconds
Started May 23 02:34:13 PM PDT 24
Finished May 23 02:35:21 PM PDT 24
Peak memory 248784 kb
Host smart-78e49468-6de8-4271-8b63-5a6c6c895ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
42885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3359742885
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3434052493
Short name T594
Test name
Test status
Simulation time 57548960041 ps
CPU time 1466.11 seconds
Started May 23 02:34:14 PM PDT 24
Finished May 23 02:58:41 PM PDT 24
Peak memory 270424 kb
Host smart-26c3e1ff-1ddd-4488-9010-567cd3ecf767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434052493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3434052493
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3290054891
Short name T695
Test name
Test status
Simulation time 25150354568 ps
CPU time 1425.12 seconds
Started May 23 02:34:26 PM PDT 24
Finished May 23 02:58:13 PM PDT 24
Peak memory 273324 kb
Host smart-1c56ae87-874a-4a3d-9be5-71597237457f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290054891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3290054891
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.352579506
Short name T230
Test name
Test status
Simulation time 11834498476 ps
CPU time 525.27 seconds
Started May 23 02:34:13 PM PDT 24
Finished May 23 02:42:59 PM PDT 24
Peak memory 254980 kb
Host smart-25bbd016-f6bb-4256-b073-dd4acdd8a085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352579506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.352579506
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3822740514
Short name T107
Test name
Test status
Simulation time 173107912 ps
CPU time 12.69 seconds
Started May 23 02:34:15 PM PDT 24
Finished May 23 02:34:28 PM PDT 24
Peak memory 254152 kb
Host smart-3bc4824c-1273-4c2e-9802-04199f10947c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
40514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3822740514
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2616968623
Short name T77
Test name
Test status
Simulation time 3926578440 ps
CPU time 57.18 seconds
Started May 23 02:34:15 PM PDT 24
Finished May 23 02:35:13 PM PDT 24
Peak memory 255660 kb
Host smart-e19a5931-9cc5-4854-a2f9-34556fa4cd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26169
68623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2616968623
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3528146195
Short name T608
Test name
Test status
Simulation time 320471644 ps
CPU time 14.65 seconds
Started May 23 02:34:15 PM PDT 24
Finished May 23 02:34:30 PM PDT 24
Peak memory 252736 kb
Host smart-04d53ce3-10c1-44f4-8c00-f0cfd3ec5fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
46195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3528146195
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4218760410
Short name T381
Test name
Test status
Simulation time 4459457138 ps
CPU time 60.49 seconds
Started May 23 02:34:13 PM PDT 24
Finished May 23 02:35:14 PM PDT 24
Peak memory 256240 kb
Host smart-b1e15e11-5c09-42bb-aec1-3e818832888a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187
60410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4218760410
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.350576128
Short name T328
Test name
Test status
Simulation time 7449428623 ps
CPU time 626.48 seconds
Started May 23 02:34:26 PM PDT 24
Finished May 23 02:44:54 PM PDT 24
Peak memory 272000 kb
Host smart-32d3fafc-4be5-4a71-90cb-9345893ba298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350576128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.350576128
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3130251944
Short name T133
Test name
Test status
Simulation time 23482451764 ps
CPU time 290.81 seconds
Started May 23 02:34:26 PM PDT 24
Finished May 23 02:39:18 PM PDT 24
Peak memory 256936 kb
Host smart-39327c63-7101-4edc-81be-8b0e1c5c76fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31302
51944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3130251944
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.304084137
Short name T698
Test name
Test status
Simulation time 357458001 ps
CPU time 22.97 seconds
Started May 23 02:34:28 PM PDT 24
Finished May 23 02:34:52 PM PDT 24
Peak memory 248984 kb
Host smart-b5189a32-f1ab-4aec-b667-a39ec0dc1182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
4137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.304084137
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4051984767
Short name T363
Test name
Test status
Simulation time 59411120025 ps
CPU time 1625.81 seconds
Started May 23 02:34:27 PM PDT 24
Finished May 23 03:01:34 PM PDT 24
Peak memory 271368 kb
Host smart-39dbf232-ede2-46d9-81cf-0f1369d6424a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051984767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4051984767
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3145038436
Short name T139
Test name
Test status
Simulation time 154960568167 ps
CPU time 2161.89 seconds
Started May 23 02:34:27 PM PDT 24
Finished May 23 03:10:30 PM PDT 24
Peak memory 281576 kb
Host smart-d67a6207-588b-408c-8a2b-3f5de2f4526d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145038436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3145038436
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4217865591
Short name T580
Test name
Test status
Simulation time 4994156193 ps
CPU time 204.47 seconds
Started May 23 02:34:25 PM PDT 24
Finished May 23 02:37:50 PM PDT 24
Peak memory 248352 kb
Host smart-efbcd6dc-f936-4639-9001-a2da46038de6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217865591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4217865591
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3245299944
Short name T45
Test name
Test status
Simulation time 4404399511 ps
CPU time 58.36 seconds
Started May 23 02:34:24 PM PDT 24
Finished May 23 02:35:23 PM PDT 24
Peak memory 256168 kb
Host smart-997053f3-8f1b-4521-a0de-69a1ceb99958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
99944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3245299944
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4053716827
Short name T307
Test name
Test status
Simulation time 5868781072 ps
CPU time 60.51 seconds
Started May 23 02:34:26 PM PDT 24
Finished May 23 02:35:27 PM PDT 24
Peak memory 255144 kb
Host smart-b63ab101-d328-4e73-9de2-f458f3b55ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40537
16827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4053716827
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1253930895
Short name T62
Test name
Test status
Simulation time 571520601 ps
CPU time 45.05 seconds
Started May 23 02:34:27 PM PDT 24
Finished May 23 02:35:13 PM PDT 24
Peak memory 247464 kb
Host smart-78d8a719-3f3d-4665-8a2d-d887df67e655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12539
30895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1253930895
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1794154599
Short name T74
Test name
Test status
Simulation time 9079563227 ps
CPU time 53.54 seconds
Started May 23 02:34:28 PM PDT 24
Finished May 23 02:35:22 PM PDT 24
Peak memory 256296 kb
Host smart-345d77e9-7949-461f-ba4a-21493b257c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17941
54599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1794154599
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.756629067
Short name T530
Test name
Test status
Simulation time 60712555746 ps
CPU time 3785.19 seconds
Started May 23 02:34:39 PM PDT 24
Finished May 23 03:37:45 PM PDT 24
Peak memory 305732 kb
Host smart-4704973e-30c5-46ec-b113-0856f6ceb865
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756629067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.756629067
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3111626295
Short name T515
Test name
Test status
Simulation time 399720486493 ps
CPU time 2026.8 seconds
Started May 23 02:35:00 PM PDT 24
Finished May 23 03:08:49 PM PDT 24
Peak memory 273400 kb
Host smart-15a6ce81-627c-4e64-8d3b-260e6719b48e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111626295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3111626295
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.53528467
Short name T685
Test name
Test status
Simulation time 16639294672 ps
CPU time 282.83 seconds
Started May 23 02:34:39 PM PDT 24
Finished May 23 02:39:22 PM PDT 24
Peak memory 257016 kb
Host smart-c9f2623b-a2d8-4b92-9af4-010f197a1970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53528
467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.53528467
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1081475022
Short name T485
Test name
Test status
Simulation time 1831350874 ps
CPU time 39.9 seconds
Started May 23 02:34:37 PM PDT 24
Finished May 23 02:35:18 PM PDT 24
Peak memory 255480 kb
Host smart-2d6e7058-cbff-4263-9b9b-813b01669305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10814
75022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1081475022
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1246186188
Short name T364
Test name
Test status
Simulation time 262096135313 ps
CPU time 1483.79 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:59:35 PM PDT 24
Peak memory 268312 kb
Host smart-b1cd4b61-d753-49ee-b07c-2d216c388d4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246186188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1246186188
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2100645755
Short name T43
Test name
Test status
Simulation time 15575195368 ps
CPU time 1170.35 seconds
Started May 23 02:34:56 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 288944 kb
Host smart-33df07a2-6443-431c-914a-ebadb101c249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100645755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2100645755
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2338069005
Short name T332
Test name
Test status
Simulation time 4659322931 ps
CPU time 200.28 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:38:11 PM PDT 24
Peak memory 248204 kb
Host smart-55605153-0d18-4c29-9f56-442f5a712790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338069005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2338069005
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2353625130
Short name T428
Test name
Test status
Simulation time 417334197 ps
CPU time 20.29 seconds
Started May 23 02:34:39 PM PDT 24
Finished May 23 02:34:59 PM PDT 24
Peak memory 256048 kb
Host smart-6f253d2f-f098-4830-87da-814288afae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
25130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2353625130
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1082741163
Short name T693
Test name
Test status
Simulation time 856214776 ps
CPU time 16.28 seconds
Started May 23 02:34:39 PM PDT 24
Finished May 23 02:34:56 PM PDT 24
Peak memory 254232 kb
Host smart-4643cbd4-6f8b-47df-8192-47a16e012ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
41163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1082741163
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3649573892
Short name T322
Test name
Test status
Simulation time 342440896 ps
CPU time 21.31 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:35:12 PM PDT 24
Peak memory 248784 kb
Host smart-584faca6-4e91-4f38-8213-5e212e58a924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
73892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3649573892
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2345162399
Short name T652
Test name
Test status
Simulation time 592620552 ps
CPU time 23.17 seconds
Started May 23 02:34:38 PM PDT 24
Finished May 23 02:35:02 PM PDT 24
Peak memory 248788 kb
Host smart-bdd76d41-5236-4a16-80c6-855198a6a552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
62399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2345162399
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1844075780
Short name T260
Test name
Test status
Simulation time 195202686812 ps
CPU time 3072.14 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 03:26:04 PM PDT 24
Peak memory 280792 kb
Host smart-874edf21-7f63-46ae-bb1c-ead0c95912b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844075780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1844075780
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.302459386
Short name T123
Test name
Test status
Simulation time 270234065383 ps
CPU time 5680.53 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 04:09:32 PM PDT 24
Peak memory 314352 kb
Host smart-ff3e89c2-d0d0-4e42-b262-c4a3189b4c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302459386 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.302459386
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1728044331
Short name T433
Test name
Test status
Simulation time 22708286744 ps
CPU time 1298.61 seconds
Started May 23 02:34:57 PM PDT 24
Finished May 23 02:56:36 PM PDT 24
Peak memory 267336 kb
Host smart-0e0a53cd-505e-4c71-b400-49a5dbb67756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728044331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1728044331
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3728381820
Short name T499
Test name
Test status
Simulation time 2961009580 ps
CPU time 153.64 seconds
Started May 23 02:34:52 PM PDT 24
Finished May 23 02:37:26 PM PDT 24
Peak memory 257000 kb
Host smart-19c1cf29-5fa2-4e1d-a58e-008570f9b592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
81820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3728381820
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.234994582
Short name T257
Test name
Test status
Simulation time 743558119 ps
CPU time 37.83 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:35:28 PM PDT 24
Peak memory 248596 kb
Host smart-d6d21c5e-44c6-4a24-a14a-d5e345cb2679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
4582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.234994582
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1767496086
Short name T359
Test name
Test status
Simulation time 34491301171 ps
CPU time 786.34 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:47:57 PM PDT 24
Peak memory 265204 kb
Host smart-abc72642-0872-4f38-8b5e-7e164f27ac99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767496086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1767496086
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1989154696
Short name T654
Test name
Test status
Simulation time 215120173822 ps
CPU time 2544.24 seconds
Started May 23 02:34:55 PM PDT 24
Finished May 23 03:17:21 PM PDT 24
Peak memory 281556 kb
Host smart-929ef574-f981-4109-8edf-9ea277c86bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989154696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1989154696
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2709883970
Short name T331
Test name
Test status
Simulation time 26198397086 ps
CPU time 325.96 seconds
Started May 23 02:35:00 PM PDT 24
Finished May 23 02:40:26 PM PDT 24
Peak memory 248164 kb
Host smart-0c91ce19-7454-4dc9-902d-e94508d389c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709883970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2709883970
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2251550173
Short name T694
Test name
Test status
Simulation time 778868868 ps
CPU time 53.95 seconds
Started May 23 02:34:55 PM PDT 24
Finished May 23 02:35:50 PM PDT 24
Peak memory 255468 kb
Host smart-d9cd7e21-9943-4c5f-b8ea-fa8fc8873b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22515
50173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2251550173
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.64960119
Short name T548
Test name
Test status
Simulation time 418849666 ps
CPU time 29.56 seconds
Started May 23 02:35:00 PM PDT 24
Finished May 23 02:35:31 PM PDT 24
Peak memory 247556 kb
Host smart-b6fe23ff-3d6a-4e23-8674-8d44a23165be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64960
119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.64960119
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3805602874
Short name T418
Test name
Test status
Simulation time 102240924 ps
CPU time 12.42 seconds
Started May 23 02:34:50 PM PDT 24
Finished May 23 02:35:03 PM PDT 24
Peak memory 248784 kb
Host smart-04e6333d-7bf5-4cfd-914f-9f7220101cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38056
02874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3805602874
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1685155291
Short name T523
Test name
Test status
Simulation time 77190173601 ps
CPU time 1639.58 seconds
Started May 23 02:34:51 PM PDT 24
Finished May 23 03:02:12 PM PDT 24
Peak memory 300840 kb
Host smart-defb0cab-9992-4998-b0b6-c3f40e895575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685155291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1685155291
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3919652930
Short name T648
Test name
Test status
Simulation time 486223754819 ps
CPU time 5842.49 seconds
Started May 23 02:34:51 PM PDT 24
Finished May 23 04:12:15 PM PDT 24
Peak memory 354544 kb
Host smart-3ea0bf6c-51c3-45c2-8b9d-8596e030c3d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919652930 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3919652930
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3436835120
Short name T517
Test name
Test status
Simulation time 68790773879 ps
CPU time 650.71 seconds
Started May 23 02:35:01 PM PDT 24
Finished May 23 02:45:53 PM PDT 24
Peak memory 272664 kb
Host smart-ad37f5c0-4510-4186-b62b-efd3c8773e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436835120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3436835120
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1546038274
Short name T402
Test name
Test status
Simulation time 29483654 ps
CPU time 3.7 seconds
Started May 23 02:35:04 PM PDT 24
Finished May 23 02:35:08 PM PDT 24
Peak memory 239128 kb
Host smart-690cba49-f41a-4243-81e3-a5e990106566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15460
38274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1546038274
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3638267211
Short name T564
Test name
Test status
Simulation time 258072085 ps
CPU time 26.3 seconds
Started May 23 02:35:04 PM PDT 24
Finished May 23 02:35:31 PM PDT 24
Peak memory 248796 kb
Host smart-2114b299-624d-4000-bf9f-8cab952ff874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36382
67211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3638267211
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2657574403
Short name T659
Test name
Test status
Simulation time 528638837975 ps
CPU time 2635.32 seconds
Started May 23 02:35:15 PM PDT 24
Finished May 23 03:19:12 PM PDT 24
Peak memory 289044 kb
Host smart-1fa08fd4-c06b-4403-8bd2-39ec99eb4fdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657574403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2657574403
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4060615664
Short name T18
Test name
Test status
Simulation time 6821755783 ps
CPU time 697.89 seconds
Started May 23 02:35:15 PM PDT 24
Finished May 23 02:46:54 PM PDT 24
Peak memory 265288 kb
Host smart-20724b28-d5b1-4085-8958-a056b85bb3b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060615664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4060615664
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2630994417
Short name T616
Test name
Test status
Simulation time 2100915004 ps
CPU time 35.86 seconds
Started May 23 02:35:03 PM PDT 24
Finished May 23 02:35:39 PM PDT 24
Peak memory 248788 kb
Host smart-ac0a4367-b7b0-4e7b-81ea-b840dcca995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26309
94417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2630994417
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3924406774
Short name T577
Test name
Test status
Simulation time 469709130 ps
CPU time 42.99 seconds
Started May 23 02:35:02 PM PDT 24
Finished May 23 02:35:45 PM PDT 24
Peak memory 254368 kb
Host smart-81591864-dead-43e0-a13e-3c35bf232534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
06774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3924406774
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2175809597
Short name T700
Test name
Test status
Simulation time 1639492186 ps
CPU time 62.61 seconds
Started May 23 02:35:03 PM PDT 24
Finished May 23 02:36:06 PM PDT 24
Peak memory 247624 kb
Host smart-e5a18cbe-3c43-42ce-bd15-becac4f53ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
09597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2175809597
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4292562380
Short name T509
Test name
Test status
Simulation time 287092607 ps
CPU time 8.56 seconds
Started May 23 02:35:04 PM PDT 24
Finished May 23 02:35:14 PM PDT 24
Peak memory 248792 kb
Host smart-609c921b-c653-4c8e-b55a-abe8cd222f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
62380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4292562380
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.576358938
Short name T290
Test name
Test status
Simulation time 155392065303 ps
CPU time 2677.85 seconds
Started May 23 02:35:14 PM PDT 24
Finished May 23 03:19:53 PM PDT 24
Peak memory 289732 kb
Host smart-4f71089e-e4fc-4914-b564-9c2a679371fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576358938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.576358938
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1700492027
Short name T241
Test name
Test status
Simulation time 51509250 ps
CPU time 4.52 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:29:31 PM PDT 24
Peak memory 248932 kb
Host smart-cc620035-665d-4df7-a59b-1b67e6382085
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1700492027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1700492027
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2993896492
Short name T494
Test name
Test status
Simulation time 9480814322 ps
CPU time 1067.99 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:47:14 PM PDT 24
Peak memory 289840 kb
Host smart-6da86b87-7a82-41e1-b920-80ea150b5768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993896492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2993896492
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3248361350
Short name T262
Test name
Test status
Simulation time 927728085 ps
CPU time 12.92 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:29:38 PM PDT 24
Peak memory 248792 kb
Host smart-0ca8397d-76c0-4dbd-a83b-9553d361f0b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3248361350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3248361350
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.252818024
Short name T522
Test name
Test status
Simulation time 1046539521 ps
CPU time 53.29 seconds
Started May 23 02:29:14 PM PDT 24
Finished May 23 02:30:08 PM PDT 24
Peak memory 256816 kb
Host smart-129d89e9-2c1a-4246-99c3-b66a9570d270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25281
8024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.252818024
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.803758655
Short name T383
Test name
Test status
Simulation time 558012876 ps
CPU time 31.13 seconds
Started May 23 02:29:10 PM PDT 24
Finished May 23 02:29:42 PM PDT 24
Peak memory 249208 kb
Host smart-edbc8e75-e12c-4d10-abff-318dd7b362b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80375
8655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.803758655
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2771160496
Short name T358
Test name
Test status
Simulation time 102674248727 ps
CPU time 1138.72 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:48:25 PM PDT 24
Peak memory 272920 kb
Host smart-3b0a5019-b32e-4030-b7c5-f6348e8b85fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771160496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2771160496
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.956265330
Short name T571
Test name
Test status
Simulation time 209774848630 ps
CPU time 1867.05 seconds
Started May 23 02:29:26 PM PDT 24
Finished May 23 03:00:34 PM PDT 24
Peak memory 272840 kb
Host smart-f5c0574d-cf99-4025-8299-537c70cc156f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956265330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.956265330
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2475479876
Short name T339
Test name
Test status
Simulation time 11368118675 ps
CPU time 462.53 seconds
Started May 23 02:29:24 PM PDT 24
Finished May 23 02:37:08 PM PDT 24
Peak memory 248116 kb
Host smart-9d25dc79-def9-4e9c-9866-f97e285cc055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475479876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2475479876
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2731582488
Short name T28
Test name
Test status
Simulation time 633524522 ps
CPU time 32.38 seconds
Started May 23 02:29:12 PM PDT 24
Finished May 23 02:29:45 PM PDT 24
Peak memory 256924 kb
Host smart-8b76cfff-a5fc-44e8-b545-8778621b34df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
82488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2731582488
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2376737602
Short name T406
Test name
Test status
Simulation time 156368069 ps
CPU time 3.77 seconds
Started May 23 02:29:11 PM PDT 24
Finished May 23 02:29:16 PM PDT 24
Peak memory 239244 kb
Host smart-3611ffe3-ae0f-4ca3-9047-e36586a81e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23767
37602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2376737602
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1623697248
Short name T14
Test name
Test status
Simulation time 1704648032 ps
CPU time 23.21 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:29:49 PM PDT 24
Peak memory 273960 kb
Host smart-575e467c-0726-48a7-ad5c-064e138e39d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1623697248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1623697248
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2442216761
Short name T482
Test name
Test status
Simulation time 499821028 ps
CPU time 30.88 seconds
Started May 23 02:29:12 PM PDT 24
Finished May 23 02:29:44 PM PDT 24
Peak memory 254992 kb
Host smart-77f11be3-3411-4e73-a24f-e74767e5056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
16761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2442216761
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2745439030
Short name T544
Test name
Test status
Simulation time 2378885853 ps
CPU time 68.74 seconds
Started May 23 02:29:14 PM PDT 24
Finished May 23 02:30:23 PM PDT 24
Peak memory 256412 kb
Host smart-dd4454ac-a76f-4612-bd8b-aaf9d4d67272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
39030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2745439030
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1833739935
Short name T311
Test name
Test status
Simulation time 12500008967 ps
CPU time 98.09 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 02:31:03 PM PDT 24
Peak memory 257012 kb
Host smart-c9e9c5c3-4caf-423e-9088-06f8a3b13e45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833739935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1833739935
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3212714947
Short name T103
Test name
Test status
Simulation time 53986579960 ps
CPU time 2021.47 seconds
Started May 23 02:29:25 PM PDT 24
Finished May 23 03:03:08 PM PDT 24
Peak memory 289836 kb
Host smart-29ade235-a828-494f-ac8f-7c9f2b24ad0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212714947 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3212714947
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2666776754
Short name T624
Test name
Test status
Simulation time 38001649922 ps
CPU time 1721.65 seconds
Started May 23 02:35:29 PM PDT 24
Finished May 23 03:04:12 PM PDT 24
Peak memory 289268 kb
Host smart-d5131263-7f8d-4889-8b20-d137b4e5432e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666776754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2666776754
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3102901452
Short name T447
Test name
Test status
Simulation time 8074291350 ps
CPU time 128.23 seconds
Started May 23 02:35:14 PM PDT 24
Finished May 23 02:37:23 PM PDT 24
Peak memory 257020 kb
Host smart-605f28f5-bb29-4370-8aca-9fe898f4237a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
01452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3102901452
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.647007232
Short name T676
Test name
Test status
Simulation time 128865843 ps
CPU time 13.53 seconds
Started May 23 02:35:20 PM PDT 24
Finished May 23 02:35:34 PM PDT 24
Peak memory 255964 kb
Host smart-28a43615-a879-4629-866e-1336158cbb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64700
7232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.647007232
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1174387984
Short name T349
Test name
Test status
Simulation time 66755707378 ps
CPU time 1835.15 seconds
Started May 23 02:35:28 PM PDT 24
Finished May 23 03:06:04 PM PDT 24
Peak memory 272400 kb
Host smart-a161052c-40ac-4333-b252-a5f9fd4a263a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174387984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1174387984
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1544086319
Short name T671
Test name
Test status
Simulation time 39570133078 ps
CPU time 2341.24 seconds
Started May 23 02:35:36 PM PDT 24
Finished May 23 03:14:38 PM PDT 24
Peak memory 273404 kb
Host smart-71ba3c62-e296-424c-ad20-5698c0cef404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544086319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1544086319
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1280885298
Short name T679
Test name
Test status
Simulation time 22450945336 ps
CPU time 256.24 seconds
Started May 23 02:35:29 PM PDT 24
Finished May 23 02:39:46 PM PDT 24
Peak memory 247924 kb
Host smart-d64e8d2b-914d-4c5e-a586-cdfde74bc6bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280885298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1280885298
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1455511869
Short name T449
Test name
Test status
Simulation time 896066413 ps
CPU time 63.69 seconds
Started May 23 02:35:14 PM PDT 24
Finished May 23 02:36:19 PM PDT 24
Peak memory 256196 kb
Host smart-f5fac281-e090-4479-b657-454a164c2374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14555
11869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1455511869
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2007637469
Short name T474
Test name
Test status
Simulation time 956438612 ps
CPU time 49.89 seconds
Started May 23 02:35:14 PM PDT 24
Finished May 23 02:36:05 PM PDT 24
Peak memory 247636 kb
Host smart-4ecf9580-55b7-4b03-9147-f1f803e4d028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076
37469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2007637469
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.773948988
Short name T221
Test name
Test status
Simulation time 139126895 ps
CPU time 4.59 seconds
Started May 23 02:35:30 PM PDT 24
Finished May 23 02:35:35 PM PDT 24
Peak memory 240572 kb
Host smart-58354269-c8a2-428f-a7bd-b856108a19e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77394
8988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.773948988
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1248128885
Short name T306
Test name
Test status
Simulation time 1386227231 ps
CPU time 24.37 seconds
Started May 23 02:35:16 PM PDT 24
Finished May 23 02:35:41 PM PDT 24
Peak memory 248836 kb
Host smart-557ed60a-468a-4c34-b564-d60b79784574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
28885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1248128885
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4074351460
Short name T301
Test name
Test status
Simulation time 22375855695 ps
CPU time 758.36 seconds
Started May 23 02:35:38 PM PDT 24
Finished May 23 02:48:17 PM PDT 24
Peak memory 272044 kb
Host smart-2f8fce71-a442-4b3b-bd3c-37e35c378842
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074351460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4074351460
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2421061002
Short name T269
Test name
Test status
Simulation time 287313421243 ps
CPU time 4380.75 seconds
Started May 23 02:35:38 PM PDT 24
Finished May 23 03:48:40 PM PDT 24
Peak memory 306156 kb
Host smart-b91ea3ff-a840-4899-9ff4-321c3a50864a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421061002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2421061002
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.198752603
Short name T421
Test name
Test status
Simulation time 3870161607 ps
CPU time 124.75 seconds
Started May 23 02:35:39 PM PDT 24
Finished May 23 02:37:45 PM PDT 24
Peak memory 249072 kb
Host smart-3a7eb5b0-0ccb-4b79-8348-01f4dfc2cccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875
2603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.198752603
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.488596973
Short name T703
Test name
Test status
Simulation time 3015633107 ps
CPU time 35.64 seconds
Started May 23 02:35:39 PM PDT 24
Finished May 23 02:36:15 PM PDT 24
Peak memory 256788 kb
Host smart-c93b876a-8562-4c37-a3a0-f1019e003029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48859
6973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.488596973
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.908442974
Short name T545
Test name
Test status
Simulation time 212039030160 ps
CPU time 2765.23 seconds
Started May 23 02:35:57 PM PDT 24
Finished May 23 03:22:03 PM PDT 24
Peak memory 289080 kb
Host smart-15b8c21e-fa71-4da5-a067-1f5ddb42541b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908442974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.908442974
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2145275209
Short name T497
Test name
Test status
Simulation time 41197875264 ps
CPU time 1063.69 seconds
Started May 23 02:35:53 PM PDT 24
Finished May 23 02:53:38 PM PDT 24
Peak memory 273404 kb
Host smart-956c1865-3370-42f5-a7d0-eede24b27520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145275209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2145275209
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2505545959
Short name T330
Test name
Test status
Simulation time 14995561109 ps
CPU time 292.87 seconds
Started May 23 02:35:37 PM PDT 24
Finished May 23 02:40:31 PM PDT 24
Peak memory 254932 kb
Host smart-69ba77ee-ad5f-4950-8774-91f24aadf4ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505545959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2505545959
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.645307525
Short name T666
Test name
Test status
Simulation time 579236380 ps
CPU time 28.03 seconds
Started May 23 02:35:38 PM PDT 24
Finished May 23 02:36:07 PM PDT 24
Peak memory 248728 kb
Host smart-17be544a-cf7a-471a-bd00-83763092e6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64530
7525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.645307525
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4135870810
Short name T465
Test name
Test status
Simulation time 3192789010 ps
CPU time 47.03 seconds
Started May 23 02:35:37 PM PDT 24
Finished May 23 02:36:25 PM PDT 24
Peak memory 248812 kb
Host smart-a89c87fa-9b7b-4c6c-932f-729b2b89383d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
70810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4135870810
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2999714314
Short name T70
Test name
Test status
Simulation time 997224192 ps
CPU time 14.93 seconds
Started May 23 02:35:38 PM PDT 24
Finished May 23 02:35:54 PM PDT 24
Peak memory 248984 kb
Host smart-02657116-e4d5-49e9-92c2-e3be2539551e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29997
14314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2999714314
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3345253301
Short name T451
Test name
Test status
Simulation time 952251303 ps
CPU time 12.91 seconds
Started May 23 02:35:37 PM PDT 24
Finished May 23 02:35:51 PM PDT 24
Peak memory 248752 kb
Host smart-9a47ebac-bf46-4a22-8306-39f33a9fb445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33452
53301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3345253301
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1007778104
Short name T469
Test name
Test status
Simulation time 16902730019 ps
CPU time 256.2 seconds
Started May 23 02:35:55 PM PDT 24
Finished May 23 02:40:12 PM PDT 24
Peak memory 257020 kb
Host smart-19a2f23d-cd90-4377-8453-7756d7100c30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007778104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1007778104
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3767004009
Short name T81
Test name
Test status
Simulation time 108295399396 ps
CPU time 1378.46 seconds
Started May 23 02:35:56 PM PDT 24
Finished May 23 02:58:55 PM PDT 24
Peak memory 272200 kb
Host smart-5dd7aee3-471b-4c8b-a9dd-fcd8e9a129f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767004009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3767004009
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3180255979
Short name T295
Test name
Test status
Simulation time 1742687578 ps
CPU time 151.3 seconds
Started May 23 02:35:55 PM PDT 24
Finished May 23 02:38:27 PM PDT 24
Peak memory 256900 kb
Host smart-67edeb51-299c-4976-8db8-532692dbff87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
55979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3180255979
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1992221570
Short name T476
Test name
Test status
Simulation time 97125779 ps
CPU time 4.36 seconds
Started May 23 02:35:55 PM PDT 24
Finished May 23 02:36:00 PM PDT 24
Peak memory 240572 kb
Host smart-0f68bcf2-3ce0-4377-98ba-9dd66339926d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19922
21570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1992221570
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1067131018
Short name T636
Test name
Test status
Simulation time 42670391191 ps
CPU time 2431.85 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 03:16:40 PM PDT 24
Peak memory 288976 kb
Host smart-8935eb4d-9453-4c7c-af77-ed9da5fabedd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067131018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1067131018
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4179793410
Short name T521
Test name
Test status
Simulation time 185407180849 ps
CPU time 1242.69 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 282744 kb
Host smart-49aec9e3-efb6-4f4f-911a-d1dcc98b6355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179793410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4179793410
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1949321307
Short name T117
Test name
Test status
Simulation time 42604526390 ps
CPU time 168 seconds
Started May 23 02:36:10 PM PDT 24
Finished May 23 02:38:58 PM PDT 24
Peak memory 253852 kb
Host smart-697271aa-c100-49be-9ba8-ab82b32b2842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949321307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1949321307
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2660496421
Short name T436
Test name
Test status
Simulation time 335339481 ps
CPU time 21.86 seconds
Started May 23 02:35:54 PM PDT 24
Finished May 23 02:36:17 PM PDT 24
Peak memory 248776 kb
Host smart-449dd476-e5b7-4d56-8fc6-404e55fa6a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
96421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2660496421
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3609238402
Short name T416
Test name
Test status
Simulation time 889360778 ps
CPU time 16.08 seconds
Started May 23 02:35:56 PM PDT 24
Finished May 23 02:36:13 PM PDT 24
Peak memory 253628 kb
Host smart-ef6b6233-9be5-4ab7-aed3-748ee22c4a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36092
38402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3609238402
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.851094697
Short name T645
Test name
Test status
Simulation time 210032796 ps
CPU time 22.51 seconds
Started May 23 02:35:57 PM PDT 24
Finished May 23 02:36:20 PM PDT 24
Peak memory 255292 kb
Host smart-9fb04949-62a1-4880-8d25-806962396a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85109
4697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.851094697
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3344896975
Short name T554
Test name
Test status
Simulation time 158817117 ps
CPU time 11.39 seconds
Started May 23 02:35:56 PM PDT 24
Finished May 23 02:36:08 PM PDT 24
Peak memory 248840 kb
Host smart-d1bda5ea-352f-45c7-8061-8f6771745575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33448
96975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3344896975
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2860452690
Short name T66
Test name
Test status
Simulation time 233085463785 ps
CPU time 2302.27 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 03:14:30 PM PDT 24
Peak memory 288052 kb
Host smart-e19cc17a-8ec6-4ad9-bc49-c961a9d8aad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860452690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2860452690
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2276049318
Short name T78
Test name
Test status
Simulation time 3478191621 ps
CPU time 75.01 seconds
Started May 23 02:36:09 PM PDT 24
Finished May 23 02:37:25 PM PDT 24
Peak memory 249876 kb
Host smart-4cfcdf0c-218f-4b47-8f34-719f79486d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760
49318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2276049318
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1366874979
Short name T384
Test name
Test status
Simulation time 266872121 ps
CPU time 29.82 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:36:37 PM PDT 24
Peak memory 248824 kb
Host smart-644f5193-c272-4b2b-8480-12253c91f220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
74979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1366874979
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1152569677
Short name T487
Test name
Test status
Simulation time 134721007845 ps
CPU time 2117.06 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 03:11:26 PM PDT 24
Peak memory 281824 kb
Host smart-4bacdf9e-57d5-4f96-aaa7-6e90ef66d68a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152569677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1152569677
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.959928429
Short name T27
Test name
Test status
Simulation time 18649720652 ps
CPU time 524.63 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 02:44:53 PM PDT 24
Peak memory 272500 kb
Host smart-0600593c-11b6-4672-9bb1-5da887ed8043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959928429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.959928429
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2961745185
Short name T677
Test name
Test status
Simulation time 8642724374 ps
CPU time 380.82 seconds
Started May 23 02:36:09 PM PDT 24
Finished May 23 02:42:31 PM PDT 24
Peak memory 248004 kb
Host smart-e0043ebd-2f33-49fc-b931-9d0f336b2b81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961745185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2961745185
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1832520033
Short name T602
Test name
Test status
Simulation time 409888957 ps
CPU time 21.59 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:36:29 PM PDT 24
Peak memory 256924 kb
Host smart-28c78f8d-4999-4721-bcad-62270e0b69f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
20033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1832520033
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.440450730
Short name T55
Test name
Test status
Simulation time 537705932 ps
CPU time 28.22 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:36:36 PM PDT 24
Peak memory 248768 kb
Host smart-471883d4-8b82-43c0-b17b-0f59e852231c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44045
0730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.440450730
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2877195803
Short name T620
Test name
Test status
Simulation time 908701019 ps
CPU time 21.74 seconds
Started May 23 02:36:09 PM PDT 24
Finished May 23 02:36:31 PM PDT 24
Peak memory 256004 kb
Host smart-1b80ca3d-2608-428d-8dfe-09408d75abad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
95803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2877195803
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3620355704
Short name T692
Test name
Test status
Simulation time 308931431 ps
CPU time 26.77 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 02:36:36 PM PDT 24
Peak memory 248764 kb
Host smart-28de0372-228c-4eea-adff-ed5b3f8e163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36203
55704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3620355704
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4171107238
Short name T279
Test name
Test status
Simulation time 748064425409 ps
CPU time 2569.2 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 03:18:57 PM PDT 24
Peak memory 289680 kb
Host smart-bfd63640-982c-434f-8bb7-98f9839ca4d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171107238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4171107238
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1431413683
Short name T114
Test name
Test status
Simulation time 149195674776 ps
CPU time 2346.77 seconds
Started May 23 02:36:23 PM PDT 24
Finished May 23 03:15:31 PM PDT 24
Peak memory 283148 kb
Host smart-69d28627-4541-4c90-b3ba-54d55b9579e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431413683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1431413683
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.642537061
Short name T520
Test name
Test status
Simulation time 20931185670 ps
CPU time 121.3 seconds
Started May 23 02:36:22 PM PDT 24
Finished May 23 02:38:24 PM PDT 24
Peak memory 256964 kb
Host smart-2219b131-1641-4709-8d22-4af9b3a5a01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64253
7061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.642537061
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2388707182
Short name T527
Test name
Test status
Simulation time 302447294 ps
CPU time 29.4 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 02:36:38 PM PDT 24
Peak memory 255852 kb
Host smart-630accc4-bd28-4877-a82b-170c7319be66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23887
07182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2388707182
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1260159920
Short name T326
Test name
Test status
Simulation time 36338900462 ps
CPU time 2498.26 seconds
Started May 23 02:36:19 PM PDT 24
Finished May 23 03:17:59 PM PDT 24
Peak memory 287848 kb
Host smart-cd336167-a379-4e73-8612-24a61b82215b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260159920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1260159920
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1456362416
Short name T472
Test name
Test status
Simulation time 112445903170 ps
CPU time 3083.24 seconds
Started May 23 02:36:21 PM PDT 24
Finished May 23 03:27:45 PM PDT 24
Peak memory 289460 kb
Host smart-3debd6f8-f7c6-4520-b9f6-c79582d29396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456362416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1456362416
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.709657087
Short name T9
Test name
Test status
Simulation time 9011764193 ps
CPU time 363.61 seconds
Started May 23 02:36:20 PM PDT 24
Finished May 23 02:42:25 PM PDT 24
Peak memory 254728 kb
Host smart-70905402-232c-4292-87ad-4fc0f549c84d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709657087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.709657087
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1498858531
Short name T429
Test name
Test status
Simulation time 1083902628 ps
CPU time 17.64 seconds
Started May 23 02:36:06 PM PDT 24
Finished May 23 02:36:24 PM PDT 24
Peak memory 248768 kb
Host smart-af379fa3-4a1e-4b28-a7bd-5b85d84d177d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14988
58531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1498858531
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3229504732
Short name T613
Test name
Test status
Simulation time 1231840112 ps
CPU time 81.8 seconds
Started May 23 02:36:07 PM PDT 24
Finished May 23 02:37:29 PM PDT 24
Peak memory 255948 kb
Host smart-797ff2f5-453e-4c33-9116-7ccd712fe712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
04732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3229504732
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.800290045
Short name T535
Test name
Test status
Simulation time 4380649944 ps
CPU time 66.13 seconds
Started May 23 02:36:19 PM PDT 24
Finished May 23 02:37:26 PM PDT 24
Peak memory 248848 kb
Host smart-1f374554-8f81-4a9c-b709-9783b3c6c7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80029
0045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.800290045
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3475295340
Short name T132
Test name
Test status
Simulation time 477257704 ps
CPU time 13.96 seconds
Started May 23 02:36:08 PM PDT 24
Finished May 23 02:36:23 PM PDT 24
Peak memory 248768 kb
Host smart-0f6552a6-a67a-48d2-8e21-8c895f5e7449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
95340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3475295340
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4089184063
Short name T32
Test name
Test status
Simulation time 152057132641 ps
CPU time 2377.71 seconds
Started May 23 02:36:22 PM PDT 24
Finished May 23 03:16:01 PM PDT 24
Peak memory 288980 kb
Host smart-cc9e0c0f-5f92-4af7-82a6-cbd078666012
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089184063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4089184063
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.951641389
Short name T64
Test name
Test status
Simulation time 326370344586 ps
CPU time 9140.51 seconds
Started May 23 02:36:22 PM PDT 24
Finished May 23 05:08:44 PM PDT 24
Peak memory 394908 kb
Host smart-27cc3dcc-10b0-4b6f-8f41-a28f5b3a56e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951641389 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.951641389
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.394901765
Short name T581
Test name
Test status
Simulation time 19585919541 ps
CPU time 1323.33 seconds
Started May 23 02:36:31 PM PDT 24
Finished May 23 02:58:35 PM PDT 24
Peak memory 273420 kb
Host smart-ef63491b-350e-414f-a884-e060876d1e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394901765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.394901765
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1164188053
Short name T456
Test name
Test status
Simulation time 2581737808 ps
CPU time 55.21 seconds
Started May 23 02:36:33 PM PDT 24
Finished May 23 02:37:29 PM PDT 24
Peak memory 256960 kb
Host smart-9ecafe76-6226-49e8-b55b-5f25da3e8d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
88053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1164188053
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1894293213
Short name T289
Test name
Test status
Simulation time 70906157 ps
CPU time 5.08 seconds
Started May 23 02:36:22 PM PDT 24
Finished May 23 02:36:27 PM PDT 24
Peak memory 240796 kb
Host smart-e1e7b629-5508-46b2-a717-a091660b2a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18942
93213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1894293213
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1914721869
Short name T468
Test name
Test status
Simulation time 141018175122 ps
CPU time 1850.1 seconds
Started May 23 02:36:31 PM PDT 24
Finished May 23 03:07:22 PM PDT 24
Peak memory 283988 kb
Host smart-583ac80b-5556-43f4-bfea-bd7ffaafaf9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914721869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1914721869
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3477871226
Short name T600
Test name
Test status
Simulation time 17491209656 ps
CPU time 165.42 seconds
Started May 23 02:36:31 PM PDT 24
Finished May 23 02:39:16 PM PDT 24
Peak memory 248264 kb
Host smart-4f647f2a-aa73-47a5-8226-9ae740a4d188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477871226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3477871226
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3345732580
Short name T525
Test name
Test status
Simulation time 3079241137 ps
CPU time 71.92 seconds
Started May 23 02:36:20 PM PDT 24
Finished May 23 02:37:33 PM PDT 24
Peak memory 248828 kb
Host smart-5e53b1fd-da54-4de8-ae02-fbfb0f85d950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
32580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3345732580
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3827037130
Short name T660
Test name
Test status
Simulation time 2523480097 ps
CPU time 48.8 seconds
Started May 23 02:36:21 PM PDT 24
Finished May 23 02:37:10 PM PDT 24
Peak memory 255056 kb
Host smart-54f24d64-673c-414d-b40f-285a081b1137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38270
37130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3827037130
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2404746346
Short name T329
Test name
Test status
Simulation time 2387345557 ps
CPU time 47.71 seconds
Started May 23 02:36:33 PM PDT 24
Finished May 23 02:37:21 PM PDT 24
Peak memory 255688 kb
Host smart-b63fe020-3b95-439e-b8e2-dc142d4019d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
46346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2404746346
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1220445684
Short name T450
Test name
Test status
Simulation time 502997501 ps
CPU time 35.76 seconds
Started May 23 02:36:23 PM PDT 24
Finished May 23 02:37:00 PM PDT 24
Peak memory 248792 kb
Host smart-31a87c58-cfc1-41ee-9753-663c5b95ea13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
45684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1220445684
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2129340687
Short name T621
Test name
Test status
Simulation time 20476203973 ps
CPU time 1035.95 seconds
Started May 23 02:36:33 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 282596 kb
Host smart-c69198c9-36d8-4243-a56b-64b398c557af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129340687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2129340687
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3406091241
Short name T547
Test name
Test status
Simulation time 18632592293 ps
CPU time 899.25 seconds
Started May 23 02:36:44 PM PDT 24
Finished May 23 02:51:44 PM PDT 24
Peak memory 265524 kb
Host smart-49c0c7c0-16bd-43a4-bc9d-89c6100f4084
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406091241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3406091241
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.97469471
Short name T426
Test name
Test status
Simulation time 2671032337 ps
CPU time 86.16 seconds
Started May 23 02:36:44 PM PDT 24
Finished May 23 02:38:11 PM PDT 24
Peak memory 257000 kb
Host smart-3260d4f9-178a-4c92-a43c-a94cc353a699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97469
471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.97469471
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3911378419
Short name T424
Test name
Test status
Simulation time 1718140745 ps
CPU time 56.94 seconds
Started May 23 02:36:45 PM PDT 24
Finished May 23 02:37:43 PM PDT 24
Peak memory 256020 kb
Host smart-ced26282-c7c0-40cf-b3d6-b2bd708b4b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39113
78419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3911378419
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3996511797
Short name T124
Test name
Test status
Simulation time 30833752918 ps
CPU time 670.2 seconds
Started May 23 02:36:45 PM PDT 24
Finished May 23 02:47:55 PM PDT 24
Peak memory 271908 kb
Host smart-857c8b78-fed6-4fac-ac70-da2ece752dfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996511797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3996511797
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.213967936
Short name T396
Test name
Test status
Simulation time 25551026566 ps
CPU time 1360.93 seconds
Started May 23 02:36:45 PM PDT 24
Finished May 23 02:59:26 PM PDT 24
Peak memory 272788 kb
Host smart-cd497442-2409-47d7-8c39-f4c66b9231d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213967936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.213967936
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.882429404
Short name T518
Test name
Test status
Simulation time 509157126 ps
CPU time 31.42 seconds
Started May 23 02:36:45 PM PDT 24
Finished May 23 02:37:17 PM PDT 24
Peak memory 248724 kb
Host smart-7e4e0af2-976d-4e55-955b-319e1da00b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88242
9404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.882429404
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2935310219
Short name T207
Test name
Test status
Simulation time 780734361 ps
CPU time 22.33 seconds
Started May 23 02:36:45 PM PDT 24
Finished May 23 02:37:08 PM PDT 24
Peak memory 255952 kb
Host smart-649b1870-aeaa-45a0-9fb9-644adcf81840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29353
10219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2935310219
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2740159053
Short name T298
Test name
Test status
Simulation time 4107539942 ps
CPU time 72.63 seconds
Started May 23 02:36:43 PM PDT 24
Finished May 23 02:37:56 PM PDT 24
Peak memory 248840 kb
Host smart-fd5f4adc-ac83-46fc-a491-7b235f1f27b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
59053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2740159053
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.673263976
Short name T704
Test name
Test status
Simulation time 82042859196 ps
CPU time 1705.32 seconds
Started May 23 02:36:58 PM PDT 24
Finished May 23 03:05:25 PM PDT 24
Peak memory 303508 kb
Host smart-21621561-23fa-4fbf-91d5-e4f87417c8bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673263976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.673263976
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3166587540
Short name T85
Test name
Test status
Simulation time 45826595958 ps
CPU time 2688.74 seconds
Started May 23 02:36:58 PM PDT 24
Finished May 23 03:21:48 PM PDT 24
Peak memory 281624 kb
Host smart-d87ee9db-e928-4967-870a-ff0b603cf1a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166587540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3166587540
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1161690645
Short name T567
Test name
Test status
Simulation time 10843609924 ps
CPU time 122.46 seconds
Started May 23 02:36:58 PM PDT 24
Finished May 23 02:39:01 PM PDT 24
Peak memory 248840 kb
Host smart-6fa78d4e-7959-44a0-b97e-5b466629c7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
90645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1161690645
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.594177682
Short name T6
Test name
Test status
Simulation time 1186048292 ps
CPU time 26.42 seconds
Started May 23 02:36:59 PM PDT 24
Finished May 23 02:37:26 PM PDT 24
Peak memory 255940 kb
Host smart-bef6af10-6c70-4888-a0d6-db3ea61d0739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59417
7682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.594177682
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3087332591
Short name T352
Test name
Test status
Simulation time 40988183476 ps
CPU time 1376.05 seconds
Started May 23 02:37:14 PM PDT 24
Finished May 23 03:00:11 PM PDT 24
Peak memory 265368 kb
Host smart-ae923afe-c195-4985-88d5-c9589aa7dbca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087332591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3087332591
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2203017779
Short name T439
Test name
Test status
Simulation time 11819122113 ps
CPU time 1152.71 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 02:56:27 PM PDT 24
Peak memory 272904 kb
Host smart-9f6d33e8-8ed6-4296-bca7-11f48df7ab0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203017779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2203017779
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2362524032
Short name T705
Test name
Test status
Simulation time 11044663174 ps
CPU time 225.77 seconds
Started May 23 02:37:14 PM PDT 24
Finished May 23 02:41:00 PM PDT 24
Peak memory 248140 kb
Host smart-725d1cd9-a852-4039-9c6e-1c52ffbd314a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362524032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2362524032
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1584837844
Short name T656
Test name
Test status
Simulation time 3118849197 ps
CPU time 52.3 seconds
Started May 23 02:36:58 PM PDT 24
Finished May 23 02:37:51 PM PDT 24
Peak memory 256116 kb
Host smart-1d3ba788-d43e-4a67-93b7-0f3b59bcd50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15848
37844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1584837844
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2948810284
Short name T673
Test name
Test status
Simulation time 696555295 ps
CPU time 6.08 seconds
Started May 23 02:36:58 PM PDT 24
Finished May 23 02:37:04 PM PDT 24
Peak memory 251168 kb
Host smart-1b8cb7ef-a97d-4063-8929-38b884bfd780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29488
10284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2948810284
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4206729186
Short name T15
Test name
Test status
Simulation time 196415683 ps
CPU time 24.55 seconds
Started May 23 02:36:59 PM PDT 24
Finished May 23 02:37:24 PM PDT 24
Peak memory 248332 kb
Host smart-da8ce75d-4961-4dd7-9a76-988d8a0fd78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
29186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4206729186
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2745986870
Short name T543
Test name
Test status
Simulation time 410252852 ps
CPU time 42.82 seconds
Started May 23 02:36:59 PM PDT 24
Finished May 23 02:37:42 PM PDT 24
Peak memory 248700 kb
Host smart-3b1a9bd2-621b-403a-a3b0-48b223939169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
86870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2745986870
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1543242205
Short name T291
Test name
Test status
Simulation time 211043304293 ps
CPU time 1176.69 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 02:56:50 PM PDT 24
Peak memory 289564 kb
Host smart-2c2f553d-20a0-44a0-9e84-9aef188377e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543242205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1543242205
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.159706149
Short name T582
Test name
Test status
Simulation time 501307497266 ps
CPU time 8502.14 seconds
Started May 23 02:37:12 PM PDT 24
Finished May 23 04:58:56 PM PDT 24
Peak memory 302968 kb
Host smart-aa69e3ab-2cdf-4fc0-81e2-89fbf4b45ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159706149 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.159706149
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2686006083
Short name T297
Test name
Test status
Simulation time 120346963347 ps
CPU time 2379.79 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 03:16:54 PM PDT 24
Peak memory 288920 kb
Host smart-46377283-ccc2-4831-9ad7-5632524ed79e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686006083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2686006083
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2710586345
Short name T647
Test name
Test status
Simulation time 7128612014 ps
CPU time 138.03 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 02:39:32 PM PDT 24
Peak memory 251520 kb
Host smart-64ad7e3a-63a3-48e0-b19c-e519a0b61246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
86345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2710586345
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2329763621
Short name T125
Test name
Test status
Simulation time 250281741 ps
CPU time 19.27 seconds
Started May 23 02:37:12 PM PDT 24
Finished May 23 02:37:32 PM PDT 24
Peak memory 248776 kb
Host smart-1dfc4687-fd10-4660-835c-971f21c6682f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23297
63621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2329763621
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.551531539
Short name T480
Test name
Test status
Simulation time 20653960521 ps
CPU time 1602.42 seconds
Started May 23 02:37:14 PM PDT 24
Finished May 23 03:03:57 PM PDT 24
Peak memory 288940 kb
Host smart-70723b07-01c1-4159-9e9c-708f2ecd06c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551531539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.551531539
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4219312611
Short name T438
Test name
Test status
Simulation time 74644746838 ps
CPU time 1611.46 seconds
Started May 23 02:37:12 PM PDT 24
Finished May 23 03:04:04 PM PDT 24
Peak memory 281656 kb
Host smart-c101175d-96e2-416c-8bf0-b24e2faa8fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219312611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4219312611
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4244784554
Short name T211
Test name
Test status
Simulation time 8061016706 ps
CPU time 319.24 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 02:42:33 PM PDT 24
Peak memory 247840 kb
Host smart-a1e12642-c7a2-463d-ac53-ab396d889393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244784554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4244784554
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2527498576
Short name T69
Test name
Test status
Simulation time 344459035 ps
CPU time 7.5 seconds
Started May 23 02:37:15 PM PDT 24
Finished May 23 02:37:23 PM PDT 24
Peak memory 254140 kb
Host smart-73753f07-5c1b-4286-b994-e2b9f40e44f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
98576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2527498576
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1876973858
Short name T498
Test name
Test status
Simulation time 337761472 ps
CPU time 10.99 seconds
Started May 23 02:37:13 PM PDT 24
Finished May 23 02:37:25 PM PDT 24
Peak memory 248692 kb
Host smart-16bba055-70d9-4d74-8438-1fdbf67ac2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
73858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1876973858
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3210480288
Short name T430
Test name
Test status
Simulation time 335072093 ps
CPU time 12.51 seconds
Started May 23 02:37:14 PM PDT 24
Finished May 23 02:37:27 PM PDT 24
Peak memory 249056 kb
Host smart-0c2d7d9a-89cf-4f12-b6b1-d47804efae00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32104
80288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3210480288
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.619569362
Short name T404
Test name
Test status
Simulation time 3006603393 ps
CPU time 46.55 seconds
Started May 23 02:37:12 PM PDT 24
Finished May 23 02:38:00 PM PDT 24
Peak memory 248864 kb
Host smart-307467be-9fb4-4bfa-aae6-209d988ffe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61956
9362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.619569362
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.629037587
Short name T410
Test name
Test status
Simulation time 4889280621 ps
CPU time 37.4 seconds
Started May 23 02:37:14 PM PDT 24
Finished May 23 02:37:52 PM PDT 24
Peak memory 256316 kb
Host smart-36d61b96-3d24-4d6c-9b23-fc283f76858d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629037587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.629037587
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2154999240
Short name T495
Test name
Test status
Simulation time 1087203940 ps
CPU time 29.69 seconds
Started May 23 02:37:26 PM PDT 24
Finished May 23 02:37:56 PM PDT 24
Peak memory 249108 kb
Host smart-a2c8caa7-ea34-4002-93d3-92d3d46c16e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
99240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2154999240
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3081881681
Short name T664
Test name
Test status
Simulation time 702902121 ps
CPU time 44.67 seconds
Started May 23 02:37:23 PM PDT 24
Finished May 23 02:38:08 PM PDT 24
Peak memory 255572 kb
Host smart-7ddb1a64-cc91-441d-96d2-8a3e463bc489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30818
81681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3081881681
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1480120600
Short name T583
Test name
Test status
Simulation time 32817622801 ps
CPU time 1598.93 seconds
Started May 23 02:37:25 PM PDT 24
Finished May 23 03:04:05 PM PDT 24
Peak memory 271896 kb
Host smart-5d003fd0-972e-4a54-b342-9372682c95a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480120600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1480120600
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1582373297
Short name T340
Test name
Test status
Simulation time 10600990665 ps
CPU time 441.68 seconds
Started May 23 02:37:23 PM PDT 24
Finished May 23 02:44:46 PM PDT 24
Peak memory 256216 kb
Host smart-fbeb066a-6ba0-448a-95d8-9e101d3b0577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582373297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1582373297
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1056121209
Short name T68
Test name
Test status
Simulation time 112594039 ps
CPU time 7.82 seconds
Started May 23 02:37:24 PM PDT 24
Finished May 23 02:37:33 PM PDT 24
Peak memory 248780 kb
Host smart-5ed4077f-00f9-4f77-88f4-e5602de94db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
21209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1056121209
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.177088533
Short name T37
Test name
Test status
Simulation time 3229277924 ps
CPU time 48.55 seconds
Started May 23 02:37:23 PM PDT 24
Finished May 23 02:38:12 PM PDT 24
Peak memory 247904 kb
Host smart-92ad4a92-0f03-4fdb-8c58-395d99a21cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17708
8533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.177088533
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2545410674
Short name T460
Test name
Test status
Simulation time 240595613 ps
CPU time 10.13 seconds
Started May 23 02:37:26 PM PDT 24
Finished May 23 02:37:37 PM PDT 24
Peak memory 252904 kb
Host smart-db94a143-789c-4b52-81e6-643cba89e27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
10674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2545410674
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2335505210
Short name T536
Test name
Test status
Simulation time 932940904 ps
CPU time 15.82 seconds
Started May 23 02:37:12 PM PDT 24
Finished May 23 02:37:29 PM PDT 24
Peak memory 248820 kb
Host smart-78e82ba3-1186-4c0b-ae18-78b1733fb897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23355
05210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2335505210
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4010070912
Short name T52
Test name
Test status
Simulation time 45735351250 ps
CPU time 979.97 seconds
Started May 23 02:37:24 PM PDT 24
Finished May 23 02:53:44 PM PDT 24
Peak memory 284100 kb
Host smart-4e0c8f58-6823-4a7e-b514-6e96d88f602e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010070912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4010070912
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1421630742
Short name T226
Test name
Test status
Simulation time 453930862493 ps
CPU time 2914.23 seconds
Started May 23 02:37:34 PM PDT 24
Finished May 23 03:26:09 PM PDT 24
Peak memory 321232 kb
Host smart-41e536a0-656c-4294-b1e7-263101359bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421630742 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1421630742
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1906602530
Short name T239
Test name
Test status
Simulation time 83936885 ps
CPU time 3.49 seconds
Started May 23 02:29:52 PM PDT 24
Finished May 23 02:29:56 PM PDT 24
Peak memory 248948 kb
Host smart-928ed74c-3057-4d7f-861f-3f270612ee4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1906602530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1906602530
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4224647997
Short name T31
Test name
Test status
Simulation time 28499208473 ps
CPU time 1875.29 seconds
Started May 23 02:29:39 PM PDT 24
Finished May 23 03:00:55 PM PDT 24
Peak memory 286076 kb
Host smart-451279ea-30e0-4c29-989e-297dd87f1fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224647997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4224647997
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2855997489
Short name T478
Test name
Test status
Simulation time 1005438325 ps
CPU time 23.43 seconds
Started May 23 02:29:50 PM PDT 24
Finished May 23 02:30:14 PM PDT 24
Peak memory 248760 kb
Host smart-26275ebe-f4bc-4c86-95c4-5f602153572f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2855997489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2855997489
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1674422253
Short name T399
Test name
Test status
Simulation time 3245340411 ps
CPU time 83.19 seconds
Started May 23 02:29:38 PM PDT 24
Finished May 23 02:31:01 PM PDT 24
Peak memory 256648 kb
Host smart-85891624-8ccd-4ec7-9713-de7338b5dc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
22253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1674422253
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1989031501
Short name T631
Test name
Test status
Simulation time 666021328 ps
CPU time 24.12 seconds
Started May 23 02:29:39 PM PDT 24
Finished May 23 02:30:04 PM PDT 24
Peak memory 255944 kb
Host smart-d01e454b-103d-4dea-9b75-eebbc6ab233c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19890
31501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1989031501
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.303247208
Short name T519
Test name
Test status
Simulation time 62306304751 ps
CPU time 3361.16 seconds
Started May 23 02:29:46 PM PDT 24
Finished May 23 03:25:48 PM PDT 24
Peak memory 289356 kb
Host smart-2734bd73-fc30-42a1-ae33-ee14dde09ad3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303247208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.303247208
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3724780111
Short name T505
Test name
Test status
Simulation time 12811425507 ps
CPU time 1024.41 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:46:56 PM PDT 24
Peak memory 271672 kb
Host smart-591222c4-07eb-4b32-9e85-b97718dc9268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724780111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3724780111
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.147043069
Short name T335
Test name
Test status
Simulation time 11305208405 ps
CPU time 483.41 seconds
Started May 23 02:29:40 PM PDT 24
Finished May 23 02:37:44 PM PDT 24
Peak memory 255020 kb
Host smart-df299f74-5ec2-4674-a2e8-7bb75458dcb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147043069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.147043069
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2941032908
Short name T493
Test name
Test status
Simulation time 699949612 ps
CPU time 29.93 seconds
Started May 23 02:29:39 PM PDT 24
Finished May 23 02:30:09 PM PDT 24
Peak memory 248796 kb
Host smart-9d3fecef-36ba-4528-b4b0-ef03cd8287df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29410
32908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2941032908
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.580485558
Short name T444
Test name
Test status
Simulation time 3563680772 ps
CPU time 38.23 seconds
Started May 23 02:29:38 PM PDT 24
Finished May 23 02:30:16 PM PDT 24
Peak memory 247612 kb
Host smart-a5c0d680-9d7f-4388-9a30-61ae3fa903cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58048
5558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.580485558
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4198969894
Short name T36
Test name
Test status
Simulation time 1484299910 ps
CPU time 61.88 seconds
Started May 23 02:29:52 PM PDT 24
Finished May 23 02:30:55 PM PDT 24
Peak memory 276700 kb
Host smart-baa48f06-98ea-4fc3-80b8-89dd68c2f680
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4198969894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4198969894
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.955616396
Short name T228
Test name
Test status
Simulation time 581592326 ps
CPU time 18.06 seconds
Started May 23 02:29:39 PM PDT 24
Finished May 23 02:29:57 PM PDT 24
Peak memory 247524 kb
Host smart-4fa84993-4efe-4d33-a14c-b9ae78daf922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95561
6396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.955616396
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1278900061
Short name T573
Test name
Test status
Simulation time 59512038 ps
CPU time 4.57 seconds
Started May 23 02:29:38 PM PDT 24
Finished May 23 02:29:43 PM PDT 24
Peak memory 248788 kb
Host smart-0c7461b2-89ea-4c2c-90c3-7ff9ea4252ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12789
00061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1278900061
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1246521260
Short name T2
Test name
Test status
Simulation time 3597802229 ps
CPU time 370.66 seconds
Started May 23 02:29:50 PM PDT 24
Finished May 23 02:36:01 PM PDT 24
Peak memory 257012 kb
Host smart-9f017f7c-9c48-42df-aa3e-faadfd4657d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246521260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1246521260
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3858367370
Short name T120
Test name
Test status
Simulation time 300456529338 ps
CPU time 1761.36 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:59:14 PM PDT 24
Peak memory 281740 kb
Host smart-a2fc4ed8-dcf5-43ab-9c04-265db7ad3fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858367370 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3858367370
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.172821275
Short name T40
Test name
Test status
Simulation time 106087998659 ps
CPU time 3406.86 seconds
Started May 23 02:37:49 PM PDT 24
Finished May 23 03:34:37 PM PDT 24
Peak memory 289356 kb
Host smart-40617800-649b-4867-a9aa-2f855726546e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172821275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.172821275
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3254107137
Short name T409
Test name
Test status
Simulation time 1181605181 ps
CPU time 66.79 seconds
Started May 23 02:37:48 PM PDT 24
Finished May 23 02:38:56 PM PDT 24
Peak memory 256764 kb
Host smart-7d5e6bc0-08be-478f-bf5d-43828780f1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
07137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3254107137
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3588995273
Short name T678
Test name
Test status
Simulation time 359926397 ps
CPU time 29.43 seconds
Started May 23 02:37:50 PM PDT 24
Finished May 23 02:38:20 PM PDT 24
Peak memory 254988 kb
Host smart-0e39d689-455e-46b9-a2fa-da59d0ad2e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35889
95273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3588995273
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.523702449
Short name T641
Test name
Test status
Simulation time 12222192081 ps
CPU time 1126.53 seconds
Started May 23 02:38:05 PM PDT 24
Finished May 23 02:56:53 PM PDT 24
Peak memory 271876 kb
Host smart-899fb2eb-65d5-452e-b5cd-4164af0947b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523702449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.523702449
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2911590320
Short name T320
Test name
Test status
Simulation time 12909139857 ps
CPU time 488.2 seconds
Started May 23 02:37:49 PM PDT 24
Finished May 23 02:45:58 PM PDT 24
Peak memory 248232 kb
Host smart-8b7f32ab-ff73-44e5-a0a7-d532acdbca40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911590320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2911590320
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2800405377
Short name T462
Test name
Test status
Simulation time 983750058 ps
CPU time 63.5 seconds
Started May 23 02:37:34 PM PDT 24
Finished May 23 02:38:38 PM PDT 24
Peak memory 248760 kb
Host smart-2f442b0c-b1aa-4ae4-b97c-ea4a5f17bc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004
05377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2800405377
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2052245316
Short name T570
Test name
Test status
Simulation time 363546908 ps
CPU time 13.77 seconds
Started May 23 02:37:49 PM PDT 24
Finished May 23 02:38:03 PM PDT 24
Peak memory 255224 kb
Host smart-e69d5869-2a08-4298-844e-0f799816baf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
45316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2052245316
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.499818348
Short name T707
Test name
Test status
Simulation time 742516188 ps
CPU time 55.6 seconds
Started May 23 02:37:48 PM PDT 24
Finished May 23 02:38:44 PM PDT 24
Peak memory 255500 kb
Host smart-da40e76f-1033-4b10-b18c-8fed7399cab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49981
8348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.499818348
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3222898282
Short name T579
Test name
Test status
Simulation time 1126793101 ps
CPU time 63.24 seconds
Started May 23 02:37:34 PM PDT 24
Finished May 23 02:38:38 PM PDT 24
Peak memory 248772 kb
Host smart-316c7a29-d93b-41f4-9473-bbaa998d7900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
98282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3222898282
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1064466328
Short name T26
Test name
Test status
Simulation time 242271341835 ps
CPU time 3384.32 seconds
Started May 23 02:38:12 PM PDT 24
Finished May 23 03:34:37 PM PDT 24
Peak memory 289360 kb
Host smart-43aa3593-d0fb-4400-86ff-6be6fb5d774d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064466328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1064466328
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.567673
Short name T549
Test name
Test status
Simulation time 179213634763 ps
CPU time 2110.98 seconds
Started May 23 02:38:24 PM PDT 24
Finished May 23 03:13:36 PM PDT 24
Peak memory 289220 kb
Host smart-fe793522-9964-4344-acf6-9bd67cd4606e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.567673
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3595846287
Short name T446
Test name
Test status
Simulation time 6770698158 ps
CPU time 198.93 seconds
Started May 23 02:38:12 PM PDT 24
Finished May 23 02:41:31 PM PDT 24
Peak memory 256352 kb
Host smart-af5db053-6fe5-493e-893e-8a7135fa7da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
46287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3595846287
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3366180425
Short name T458
Test name
Test status
Simulation time 812590414 ps
CPU time 51.16 seconds
Started May 23 02:38:10 PM PDT 24
Finished May 23 02:39:03 PM PDT 24
Peak memory 255892 kb
Host smart-2c86a1bc-3189-487f-950c-e44c9628791e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
80425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3366180425
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.30099168
Short name T80
Test name
Test status
Simulation time 9756446091 ps
CPU time 1133.94 seconds
Started May 23 02:38:20 PM PDT 24
Finished May 23 02:57:15 PM PDT 24
Peak memory 272776 kb
Host smart-aa385242-15f9-4bc0-9977-4c922a74952c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30099168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.30099168
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.292042225
Short name T559
Test name
Test status
Simulation time 66201750986 ps
CPU time 2392.81 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 03:18:15 PM PDT 24
Peak memory 287096 kb
Host smart-719d738b-9df8-46b5-8ef3-ae05ad89fc74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292042225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.292042225
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3050542566
Short name T346
Test name
Test status
Simulation time 36418394098 ps
CPU time 401.33 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 02:45:04 PM PDT 24
Peak memory 248124 kb
Host smart-1b6d4ecf-bdc4-4422-be00-31372af1be42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050542566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3050542566
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3430322900
Short name T599
Test name
Test status
Simulation time 243472755 ps
CPU time 23.34 seconds
Started May 23 02:38:06 PM PDT 24
Finished May 23 02:38:30 PM PDT 24
Peak memory 256048 kb
Host smart-eea45236-a99a-4c65-bad2-2accadf71a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303
22900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3430322900
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.586176796
Short name T313
Test name
Test status
Simulation time 418813384 ps
CPU time 36.25 seconds
Started May 23 02:38:06 PM PDT 24
Finished May 23 02:38:42 PM PDT 24
Peak memory 248668 kb
Host smart-728ad18e-945c-4f3f-9446-def5372498d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58617
6796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.586176796
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3979672292
Short name T585
Test name
Test status
Simulation time 223044944 ps
CPU time 5.05 seconds
Started May 23 02:38:05 PM PDT 24
Finished May 23 02:38:11 PM PDT 24
Peak memory 239264 kb
Host smart-4ff0640b-d318-4c11-9a00-bbd92db245ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39796
72292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3979672292
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3620974468
Short name T33
Test name
Test status
Simulation time 322927391 ps
CPU time 5.52 seconds
Started May 23 02:38:12 PM PDT 24
Finished May 23 02:38:18 PM PDT 24
Peak memory 240572 kb
Host smart-45dc0987-9360-4fd5-9a71-f8247ac9fdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209
74468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3620974468
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1067625086
Short name T115
Test name
Test status
Simulation time 48926737067 ps
CPU time 1227.02 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:58:49 PM PDT 24
Peak memory 286200 kb
Host smart-8240f84a-7dd6-4d3d-96bb-eeb75388bfdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067625086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1067625086
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2457553743
Short name T427
Test name
Test status
Simulation time 3005117639 ps
CPU time 148.28 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:40:51 PM PDT 24
Peak memory 257028 kb
Host smart-fa9520d2-6c3d-46f4-a62f-f5d1f4d26ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24575
53743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2457553743
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.805338226
Short name T87
Test name
Test status
Simulation time 1855423662 ps
CPU time 54.17 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:39:16 PM PDT 24
Peak memory 256100 kb
Host smart-ddbee3be-81b1-4169-9df0-ac0f12f62734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80533
8226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.805338226
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3857973910
Short name T344
Test name
Test status
Simulation time 78831973232 ps
CPU time 1412 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 03:01:55 PM PDT 24
Peak memory 265240 kb
Host smart-efe7255c-0ef2-48e2-a146-f178b865149c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857973910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3857973910
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1578917395
Short name T405
Test name
Test status
Simulation time 103758632653 ps
CPU time 2820.16 seconds
Started May 23 02:38:24 PM PDT 24
Finished May 23 03:25:25 PM PDT 24
Peak memory 281252 kb
Host smart-4bd3e300-f484-4050-8ad9-4732d540c53b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578917395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1578917395
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3898729919
Short name T496
Test name
Test status
Simulation time 18056663556 ps
CPU time 371.9 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 02:44:35 PM PDT 24
Peak memory 247896 kb
Host smart-a532a35e-1849-49b3-8216-fc423b2269e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898729919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3898729919
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1089699008
Short name T110
Test name
Test status
Simulation time 63149699 ps
CPU time 7.19 seconds
Started May 23 02:38:23 PM PDT 24
Finished May 23 02:38:31 PM PDT 24
Peak memory 248992 kb
Host smart-da321c64-e379-4b2f-9864-0dd1946c4802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10896
99008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1089699008
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3764594022
Short name T47
Test name
Test status
Simulation time 3370906452 ps
CPU time 36.94 seconds
Started May 23 02:38:23 PM PDT 24
Finished May 23 02:39:00 PM PDT 24
Peak memory 255704 kb
Host smart-1f3c7b6c-a50c-47df-b2b0-68452dce210b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
94022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3764594022
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1793341066
Short name T481
Test name
Test status
Simulation time 576019941 ps
CPU time 35.01 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:38:57 PM PDT 24
Peak memory 249748 kb
Host smart-136e2084-4e6b-453c-ae86-eead900201ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
41066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1793341066
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4223505768
Short name T422
Test name
Test status
Simulation time 311737985 ps
CPU time 10 seconds
Started May 23 02:38:24 PM PDT 24
Finished May 23 02:38:35 PM PDT 24
Peak memory 248780 kb
Host smart-ab81d0e1-2b53-4381-a3ad-c51418528085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
05768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4223505768
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.874015328
Short name T59
Test name
Test status
Simulation time 10147807429 ps
CPU time 203.96 seconds
Started May 23 02:38:20 PM PDT 24
Finished May 23 02:41:45 PM PDT 24
Peak memory 251072 kb
Host smart-76af7110-145b-4e3a-9caa-55d09a300f55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874015328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.874015328
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2350189033
Short name T650
Test name
Test status
Simulation time 8526060767 ps
CPU time 816.17 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:51:58 PM PDT 24
Peak memory 269464 kb
Host smart-dc823d15-de10-47ec-aca3-6ec7ab61cd76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350189033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2350189033
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1098493775
Short name T622
Test name
Test status
Simulation time 4134132914 ps
CPU time 129.63 seconds
Started May 23 02:38:20 PM PDT 24
Finished May 23 02:40:31 PM PDT 24
Peak memory 257012 kb
Host smart-4e5ff5dc-7369-483c-b12c-f50466a7ef89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10984
93775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1098493775
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2076644531
Short name T572
Test name
Test status
Simulation time 757113078 ps
CPU time 21.61 seconds
Started May 23 02:38:21 PM PDT 24
Finished May 23 02:38:43 PM PDT 24
Peak memory 254932 kb
Host smart-ed4e4e55-1e51-489a-9e96-319f0f943f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20766
44531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2076644531
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1707717281
Short name T258
Test name
Test status
Simulation time 38049435227 ps
CPU time 2124.64 seconds
Started May 23 02:38:31 PM PDT 24
Finished May 23 03:13:56 PM PDT 24
Peak memory 282268 kb
Host smart-07b3cd3f-859b-469c-acec-8c9ea9676adc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707717281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1707717281
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3013014034
Short name T302
Test name
Test status
Simulation time 69569299181 ps
CPU time 1333.35 seconds
Started May 23 02:38:33 PM PDT 24
Finished May 23 03:00:46 PM PDT 24
Peak memory 288872 kb
Host smart-fa70e16c-3580-42f7-adf9-081a95a8a9d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013014034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3013014034
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1878155178
Short name T334
Test name
Test status
Simulation time 18760872462 ps
CPU time 374.74 seconds
Started May 23 02:38:31 PM PDT 24
Finished May 23 02:44:47 PM PDT 24
Peak memory 248236 kb
Host smart-724d3c9e-6568-4200-bcb6-f55915539a9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878155178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1878155178
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.816990332
Short name T479
Test name
Test status
Simulation time 614210058 ps
CPU time 41.24 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 02:39:04 PM PDT 24
Peak memory 248924 kb
Host smart-6666a484-8c5b-42cc-96ae-414ca3c2c8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81699
0332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.816990332
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2130075886
Short name T513
Test name
Test status
Simulation time 136970617 ps
CPU time 11.46 seconds
Started May 23 02:38:25 PM PDT 24
Finished May 23 02:38:37 PM PDT 24
Peak memory 248764 kb
Host smart-1faf475c-4756-4f0d-8f99-290c0b9e3662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21300
75886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2130075886
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3685152329
Short name T574
Test name
Test status
Simulation time 776394701 ps
CPU time 19.36 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 02:38:43 PM PDT 24
Peak memory 247736 kb
Host smart-47aefda1-b4ba-45de-b97d-9f16101a687f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
52329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3685152329
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2287631206
Short name T455
Test name
Test status
Simulation time 402395100 ps
CPU time 25.51 seconds
Started May 23 02:38:22 PM PDT 24
Finished May 23 02:38:48 PM PDT 24
Peak memory 256904 kb
Host smart-688783e3-82b1-44a0-9898-12cb9845c72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22876
31206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2287631206
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1149697285
Short name T63
Test name
Test status
Simulation time 17528933652 ps
CPU time 1918.18 seconds
Started May 23 02:38:33 PM PDT 24
Finished May 23 03:10:32 PM PDT 24
Peak memory 306160 kb
Host smart-efdd8935-169c-47f5-a516-567ff8f53201
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149697285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1149697285
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2930949724
Short name T259
Test name
Test status
Simulation time 84451058712 ps
CPU time 6505.53 seconds
Started May 23 02:38:33 PM PDT 24
Finished May 23 04:27:00 PM PDT 24
Peak memory 305856 kb
Host smart-6d29250b-0d19-4cda-b251-8295a61cc4e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930949724 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2930949724
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3236361348
Short name T17
Test name
Test status
Simulation time 61061865470 ps
CPU time 3561.52 seconds
Started May 23 02:38:45 PM PDT 24
Finished May 23 03:38:07 PM PDT 24
Peak memory 289460 kb
Host smart-b4abeb7b-f04c-4c44-b61e-a6b04afdf05e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236361348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3236361348
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.410136601
Short name T611
Test name
Test status
Simulation time 7040573289 ps
CPU time 134.19 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 02:40:59 PM PDT 24
Peak memory 256880 kb
Host smart-61071ddd-b9cd-4e8f-8e74-4dcecdad07c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41013
6601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.410136601
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.43055065
Short name T84
Test name
Test status
Simulation time 167626474 ps
CPU time 6.96 seconds
Started May 23 02:38:33 PM PDT 24
Finished May 23 02:38:40 PM PDT 24
Peak memory 252832 kb
Host smart-066aa30a-c4f0-47f8-ad82-d9f48c47708c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43055
065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.43055065
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2464732806
Short name T39
Test name
Test status
Simulation time 177051958425 ps
CPU time 1471.38 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 03:03:16 PM PDT 24
Peak memory 289204 kb
Host smart-c57a1b36-cb3c-4a87-bf02-ff614fc5091c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464732806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2464732806
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.667507210
Short name T271
Test name
Test status
Simulation time 39062134623 ps
CPU time 2323.47 seconds
Started May 23 02:38:43 PM PDT 24
Finished May 23 03:17:27 PM PDT 24
Peak memory 283240 kb
Host smart-94eac7e9-23d4-498b-8613-498b763d4685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667507210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.667507210
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4157211667
Short name T503
Test name
Test status
Simulation time 25129949270 ps
CPU time 506.93 seconds
Started May 23 02:38:43 PM PDT 24
Finished May 23 02:47:11 PM PDT 24
Peak memory 248256 kb
Host smart-4de08013-3173-429c-8a94-69c07cc8deab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157211667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4157211667
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.667173765
Short name T626
Test name
Test status
Simulation time 7243178874 ps
CPU time 68.5 seconds
Started May 23 02:38:33 PM PDT 24
Finished May 23 02:39:43 PM PDT 24
Peak memory 248852 kb
Host smart-d6171c99-4d7b-4d8f-b0d7-0102ca1e939a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66717
3765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.667173765
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.423723250
Short name T57
Test name
Test status
Simulation time 2132533713 ps
CPU time 75.14 seconds
Started May 23 02:38:31 PM PDT 24
Finished May 23 02:39:47 PM PDT 24
Peak memory 248944 kb
Host smart-602a8752-1130-436c-8cd2-c6183fcaa9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
3250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.423723250
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2487426537
Short name T282
Test name
Test status
Simulation time 243219131 ps
CPU time 9.05 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 02:38:54 PM PDT 24
Peak memory 256956 kb
Host smart-e356d985-b6ea-42be-9f51-53124d0a9bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
26537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2487426537
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1673793248
Short name T562
Test name
Test status
Simulation time 588336832 ps
CPU time 23.58 seconds
Started May 23 02:38:31 PM PDT 24
Finished May 23 02:38:56 PM PDT 24
Peak memory 248752 kb
Host smart-159d0ab0-8282-4d39-8d67-a1fe23c3ccea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16737
93248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1673793248
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2687791212
Short name T53
Test name
Test status
Simulation time 111314059433 ps
CPU time 2572.71 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 03:21:50 PM PDT 24
Peak memory 288992 kb
Host smart-159a37cf-d9f0-443d-8de0-07279cc37730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687791212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2687791212
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3309288743
Short name T618
Test name
Test status
Simulation time 2449757814 ps
CPU time 159.14 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:41:36 PM PDT 24
Peak memory 248764 kb
Host smart-a0233f87-1ea7-424d-83e0-1cea149449e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33092
88743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3309288743
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.488618050
Short name T395
Test name
Test status
Simulation time 27073831 ps
CPU time 5.03 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:39:01 PM PDT 24
Peak memory 248776 kb
Host smart-fd3b4f88-ebf2-422f-adea-4dbdf0181a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48861
8050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.488618050
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.168328771
Short name T362
Test name
Test status
Simulation time 76751869179 ps
CPU time 1526.77 seconds
Started May 23 02:38:55 PM PDT 24
Finished May 23 03:04:23 PM PDT 24
Peak memory 287076 kb
Host smart-eedbf5bf-47f4-4d1b-8d65-5a8832fef2bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168328771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.168328771
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.113595318
Short name T393
Test name
Test status
Simulation time 106278869995 ps
CPU time 3153.66 seconds
Started May 23 02:38:57 PM PDT 24
Finished May 23 03:31:32 PM PDT 24
Peak memory 289708 kb
Host smart-4b5724e8-861b-41b1-9f34-14b4bc8d921f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113595318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.113595318
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1618911412
Short name T529
Test name
Test status
Simulation time 8645911153 ps
CPU time 179.39 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:41:56 PM PDT 24
Peak memory 248276 kb
Host smart-d61419a8-9eb6-478f-9f42-81ef6c7240ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618911412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1618911412
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.584643483
Short name T56
Test name
Test status
Simulation time 7384297805 ps
CPU time 51.62 seconds
Started May 23 02:38:43 PM PDT 24
Finished May 23 02:39:35 PM PDT 24
Peak memory 257016 kb
Host smart-c93f579d-f297-44ec-907d-1b1154225b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58464
3483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.584643483
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.12923137
Short name T484
Test name
Test status
Simulation time 3482690961 ps
CPU time 61.88 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 02:39:47 PM PDT 24
Peak memory 256736 kb
Host smart-41fbf0ce-1a3f-4829-bed2-70eecc9aa8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.12923137
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2248571325
Short name T274
Test name
Test status
Simulation time 885319255 ps
CPU time 36.32 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:39:33 PM PDT 24
Peak memory 248912 kb
Host smart-eb14257c-adac-45a3-a7c2-825e1296a067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
71325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2248571325
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2686359616
Short name T401
Test name
Test status
Simulation time 31733859 ps
CPU time 4.82 seconds
Started May 23 02:38:44 PM PDT 24
Finished May 23 02:38:50 PM PDT 24
Peak memory 240556 kb
Host smart-d1297b13-2f95-4d83-b645-8abd5d01c8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
59616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2686359616
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2008204019
Short name T532
Test name
Test status
Simulation time 15986945959 ps
CPU time 1212.24 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 02:59:21 PM PDT 24
Peak memory 281612 kb
Host smart-94ba5942-f532-4870-ac64-4bf68d6fdd61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008204019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2008204019
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2644901364
Short name T467
Test name
Test status
Simulation time 1598547564 ps
CPU time 42.08 seconds
Started May 23 02:39:07 PM PDT 24
Finished May 23 02:39:50 PM PDT 24
Peak memory 256956 kb
Host smart-5cb77669-d6e8-46d6-8514-eba057fac3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26449
01364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2644901364
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1630563322
Short name T538
Test name
Test status
Simulation time 1737898873 ps
CPU time 31.29 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 02:39:40 PM PDT 24
Peak memory 255876 kb
Host smart-f829b9e4-5f4b-43c5-a252-861bc6518f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
63322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1630563322
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.794560080
Short name T272
Test name
Test status
Simulation time 26847670310 ps
CPU time 1690.71 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 03:07:20 PM PDT 24
Peak memory 266228 kb
Host smart-41981682-12bb-4b8b-a7e6-99b1ab72ef6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794560080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.794560080
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3840163965
Short name T551
Test name
Test status
Simulation time 18002801370 ps
CPU time 366.63 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 02:45:15 PM PDT 24
Peak memory 254668 kb
Host smart-3e8a9af9-80d3-4af0-8489-16c45038c7cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840163965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3840163965
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2034604241
Short name T504
Test name
Test status
Simulation time 269652581 ps
CPU time 17.8 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:39:15 PM PDT 24
Peak memory 248768 kb
Host smart-36fdea7b-aaaf-4c61-aee9-849e4d208e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
04241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2034604241
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2285458051
Short name T7
Test name
Test status
Simulation time 778262883 ps
CPU time 53.43 seconds
Started May 23 02:38:56 PM PDT 24
Finished May 23 02:39:50 PM PDT 24
Peak memory 255992 kb
Host smart-61eddf48-1ef8-4c20-9d2d-7d0f67b6a438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22854
58051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2285458051
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.112174639
Short name T285
Test name
Test status
Simulation time 3391130347 ps
CPU time 57.11 seconds
Started May 23 02:39:08 PM PDT 24
Finished May 23 02:40:06 PM PDT 24
Peak memory 248916 kb
Host smart-1d06483d-e7bd-49d2-ad5c-e8884551c2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
4639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.112174639
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4017823648
Short name T423
Test name
Test status
Simulation time 2634970510 ps
CPU time 39.34 seconds
Started May 23 02:38:55 PM PDT 24
Finished May 23 02:39:36 PM PDT 24
Peak memory 248880 kb
Host smart-30f98718-758d-4e35-9468-3e5b519f68dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40178
23648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4017823648
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1261049448
Short name T442
Test name
Test status
Simulation time 34122418601 ps
CPU time 1864.58 seconds
Started May 23 02:39:21 PM PDT 24
Finished May 23 03:10:26 PM PDT 24
Peak memory 273464 kb
Host smart-7fd0560e-dd10-4b6e-9a41-2e1b1ac252a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261049448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1261049448
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.336114756
Short name T528
Test name
Test status
Simulation time 364054980 ps
CPU time 21.36 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:42 PM PDT 24
Peak memory 248796 kb
Host smart-862d12d5-46a2-4a5c-947a-a0b94b517cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
4756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.336114756
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1180459242
Short name T541
Test name
Test status
Simulation time 1216299094 ps
CPU time 35.62 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:56 PM PDT 24
Peak memory 255948 kb
Host smart-6fb4ffec-ee96-4fa1-a550-a2d1dfbd4a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
59242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1180459242
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3678008949
Short name T361
Test name
Test status
Simulation time 136851169574 ps
CPU time 2979.91 seconds
Started May 23 02:39:19 PM PDT 24
Finished May 23 03:29:00 PM PDT 24
Peak memory 281648 kb
Host smart-a0bd9f18-9434-4953-a489-0c397473f925
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678008949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3678008949
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.126051605
Short name T491
Test name
Test status
Simulation time 20798099185 ps
CPU time 1278.11 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 03:00:38 PM PDT 24
Peak memory 273424 kb
Host smart-c82e2045-60c6-4126-bd63-f60b35e8deda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126051605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.126051605
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3248986800
Short name T336
Test name
Test status
Simulation time 10006200190 ps
CPU time 98.91 seconds
Started May 23 02:39:21 PM PDT 24
Finished May 23 02:41:00 PM PDT 24
Peak memory 248344 kb
Host smart-59cee2af-d162-4a8a-abea-01caf0f28be2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248986800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3248986800
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.311762729
Short name T380
Test name
Test status
Simulation time 121228482 ps
CPU time 14.37 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:35 PM PDT 24
Peak memory 248756 kb
Host smart-f728d2ae-07f8-4d70-aecc-1f8ed36d25c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31176
2729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.311762729
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.88704587
Short name T129
Test name
Test status
Simulation time 191100056 ps
CPU time 13.27 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:34 PM PDT 24
Peak memory 249124 kb
Host smart-7c0a7d06-5452-40df-b367-8708ee283820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88704
587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.88704587
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2331725353
Short name T300
Test name
Test status
Simulation time 159724375 ps
CPU time 21.65 seconds
Started May 23 02:39:19 PM PDT 24
Finished May 23 02:39:42 PM PDT 24
Peak memory 247568 kb
Host smart-e316234b-36c8-4903-8e27-e562091e2f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317
25353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2331725353
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2064805440
Short name T617
Test name
Test status
Simulation time 19837187 ps
CPU time 3.2 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:24 PM PDT 24
Peak memory 240580 kb
Host smart-61a63174-2ca5-462b-99b6-bf4e7cfb24a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
05440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2064805440
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2611419074
Short name T604
Test name
Test status
Simulation time 98938234571 ps
CPU time 3050.53 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 03:30:11 PM PDT 24
Peak memory 289384 kb
Host smart-9c59e6f7-7dff-4cf6-8efb-1010fd410b94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611419074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2611419074
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.13926457
Short name T658
Test name
Test status
Simulation time 18841271616 ps
CPU time 1058.22 seconds
Started May 23 02:39:21 PM PDT 24
Finished May 23 02:57:00 PM PDT 24
Peak memory 289696 kb
Host smart-40dad8a8-e6ec-4b8d-83d9-8345e8b6b0cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13926457 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.13926457
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3348050061
Short name T477
Test name
Test status
Simulation time 1053509988 ps
CPU time 70.1 seconds
Started May 23 02:39:34 PM PDT 24
Finished May 23 02:40:45 PM PDT 24
Peak memory 248700 kb
Host smart-1478b280-1c81-4fc1-899b-a1dbac5f738d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480
50061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3348050061
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1660356163
Short name T473
Test name
Test status
Simulation time 400447398 ps
CPU time 27.42 seconds
Started May 23 02:39:35 PM PDT 24
Finished May 23 02:40:03 PM PDT 24
Peak memory 254924 kb
Host smart-52376733-c05d-407a-9bcc-b2543001e1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16603
56163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1660356163
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2567985683
Short name T630
Test name
Test status
Simulation time 218789432676 ps
CPU time 1724.61 seconds
Started May 23 02:39:35 PM PDT 24
Finished May 23 03:08:21 PM PDT 24
Peak memory 273332 kb
Host smart-89364163-b39b-46ac-8272-757f55154795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567985683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2567985683
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3534519231
Short name T319
Test name
Test status
Simulation time 17760728852 ps
CPU time 729.63 seconds
Started May 23 02:39:36 PM PDT 24
Finished May 23 02:51:47 PM PDT 24
Peak memory 265416 kb
Host smart-e29a736e-064b-4af9-b761-a9adb431b0fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534519231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3534519231
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2886921827
Short name T10
Test name
Test status
Simulation time 6109255100 ps
CPU time 260.68 seconds
Started May 23 02:39:36 PM PDT 24
Finished May 23 02:43:57 PM PDT 24
Peak memory 248220 kb
Host smart-5e4897b3-bcbf-40f5-855a-8a8c089eccbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886921827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2886921827
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2475740136
Short name T662
Test name
Test status
Simulation time 49005128 ps
CPU time 5.18 seconds
Started May 23 02:39:20 PM PDT 24
Finished May 23 02:39:26 PM PDT 24
Peak memory 240568 kb
Host smart-ef355768-f46c-4563-93d9-511d9653ada5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
40136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2475740136
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3371519926
Short name T661
Test name
Test status
Simulation time 712055704 ps
CPU time 41 seconds
Started May 23 02:39:24 PM PDT 24
Finished May 23 02:40:05 PM PDT 24
Peak memory 248768 kb
Host smart-2c46323f-ed37-4429-9328-ed84843353e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33715
19926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3371519926
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1086954330
Short name T398
Test name
Test status
Simulation time 398417076 ps
CPU time 11.22 seconds
Started May 23 02:39:21 PM PDT 24
Finished May 23 02:39:33 PM PDT 24
Peak memory 248960 kb
Host smart-de4844a1-c2f7-4803-a56c-6562c5fc1c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10869
54330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1086954330
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2029485464
Short name T688
Test name
Test status
Simulation time 285183026636 ps
CPU time 3221.04 seconds
Started May 23 02:39:36 PM PDT 24
Finished May 23 03:33:18 PM PDT 24
Peak memory 289656 kb
Host smart-f89a6b3c-704e-4243-9176-123d3b376550
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029485464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2029485464
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.899394632
Short name T299
Test name
Test status
Simulation time 16210129187 ps
CPU time 1567.12 seconds
Started May 23 02:39:47 PM PDT 24
Finished May 23 03:05:54 PM PDT 24
Peak memory 289436 kb
Host smart-14324085-9e95-4553-a1e1-20fdf3b152c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899394632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.899394632
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1876626588
Short name T223
Test name
Test status
Simulation time 604951276 ps
CPU time 56.71 seconds
Started May 23 02:39:47 PM PDT 24
Finished May 23 02:40:44 PM PDT 24
Peak memory 256816 kb
Host smart-15eb2906-4187-4618-9377-2a817df4d9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
26588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1876626588
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3683879685
Short name T684
Test name
Test status
Simulation time 3075420140 ps
CPU time 52.66 seconds
Started May 23 02:39:49 PM PDT 24
Finished May 23 02:40:42 PM PDT 24
Peak memory 248880 kb
Host smart-b74ef0d1-a007-4da0-9b55-58abf7e1f89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
79685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3683879685
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3423389186
Short name T557
Test name
Test status
Simulation time 42493382042 ps
CPU time 2325.7 seconds
Started May 23 02:39:49 PM PDT 24
Finished May 23 03:18:36 PM PDT 24
Peak memory 288408 kb
Host smart-3695437b-385f-42db-9b76-0fe7308265f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423389186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3423389186
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1329328980
Short name T619
Test name
Test status
Simulation time 3190334820 ps
CPU time 135.07 seconds
Started May 23 02:39:47 PM PDT 24
Finished May 23 02:42:03 PM PDT 24
Peak memory 248072 kb
Host smart-26710db9-160b-41d0-b450-0921c5807c0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329328980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1329328980
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3703582821
Short name T387
Test name
Test status
Simulation time 229941279 ps
CPU time 18.79 seconds
Started May 23 02:39:34 PM PDT 24
Finished May 23 02:39:54 PM PDT 24
Peak memory 248748 kb
Host smart-62933697-68c2-4183-8f68-a61771191583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
82821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3703582821
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3226661827
Short name T629
Test name
Test status
Simulation time 1333349369 ps
CPU time 30.22 seconds
Started May 23 02:39:48 PM PDT 24
Finished May 23 02:40:18 PM PDT 24
Peak memory 248972 kb
Host smart-b6ca41bd-fc5d-4530-b10b-e3dc44afaa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32266
61827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3226661827
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2766045046
Short name T130
Test name
Test status
Simulation time 2532198962 ps
CPU time 43.19 seconds
Started May 23 02:39:51 PM PDT 24
Finished May 23 02:40:34 PM PDT 24
Peak memory 248844 kb
Host smart-f11a3cd3-57df-4779-9fca-3d622fb7b068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27660
45046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2766045046
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3866682481
Short name T209
Test name
Test status
Simulation time 1256226181 ps
CPU time 33.99 seconds
Started May 23 02:39:34 PM PDT 24
Finished May 23 02:40:08 PM PDT 24
Peak memory 255824 kb
Host smart-6a24bc61-0379-4550-8312-908ae45fadfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38666
82481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3866682481
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2966451054
Short name T254
Test name
Test status
Simulation time 44022692443 ps
CPU time 2619.63 seconds
Started May 23 02:39:49 PM PDT 24
Finished May 23 03:23:30 PM PDT 24
Peak memory 286976 kb
Host smart-24a115e1-fbb3-4b22-9b77-958b6a562c2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966451054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2966451054
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1655790142
Short name T233
Test name
Test status
Simulation time 15626579 ps
CPU time 2.74 seconds
Started May 23 02:30:02 PM PDT 24
Finished May 23 02:30:05 PM PDT 24
Peak memory 248920 kb
Host smart-f53929a2-cbd1-4ff8-b824-6a0a2a94623a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1655790142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1655790142
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.549693789
Short name T675
Test name
Test status
Simulation time 34058261423 ps
CPU time 1990.68 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 03:03:03 PM PDT 24
Peak memory 273428 kb
Host smart-8537d441-47f5-4529-b1af-b251381b3d73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549693789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.549693789
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3236405626
Short name T412
Test name
Test status
Simulation time 3191674808 ps
CPU time 37.41 seconds
Started May 23 02:30:02 PM PDT 24
Finished May 23 02:30:40 PM PDT 24
Peak memory 248828 kb
Host smart-ec10aefe-6569-4e5b-a3c8-d02c4caa012a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3236405626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3236405626
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1452426640
Short name T440
Test name
Test status
Simulation time 192881976 ps
CPU time 17.71 seconds
Started May 23 02:29:52 PM PDT 24
Finished May 23 02:30:10 PM PDT 24
Peak memory 254504 kb
Host smart-f3814eb9-07d3-42f2-9ac2-226ce193b117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
26640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1452426640
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1341570440
Short name T263
Test name
Test status
Simulation time 90142709794 ps
CPU time 1574.12 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:56:06 PM PDT 24
Peak memory 272756 kb
Host smart-bc5bb584-b7ad-4151-9f66-2eb248a573b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341570440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1341570440
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2220615515
Short name T606
Test name
Test status
Simulation time 34731825175 ps
CPU time 1854.03 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 03:00:46 PM PDT 24
Peak memory 289460 kb
Host smart-b53bb433-f3d9-46e5-9d08-062dd189a92d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220615515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2220615515
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1967987125
Short name T345
Test name
Test status
Simulation time 28908252620 ps
CPU time 335.58 seconds
Started May 23 02:29:50 PM PDT 24
Finished May 23 02:35:27 PM PDT 24
Peak memory 248252 kb
Host smart-c067830d-089d-4db7-93d7-90ba66cd6d0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967987125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1967987125
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2688338230
Short name T553
Test name
Test status
Simulation time 7947432886 ps
CPU time 47.88 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:30:40 PM PDT 24
Peak memory 248896 kb
Host smart-70089099-2c78-457d-9335-7aea6c0c7437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
38230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2688338230
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2385197445
Short name T72
Test name
Test status
Simulation time 499081665 ps
CPU time 34.6 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:30:26 PM PDT 24
Peak memory 255480 kb
Host smart-0ff68687-1baf-40da-a813-2bc4eed4a609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
97445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2385197445
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1377032903
Short name T280
Test name
Test status
Simulation time 420434598 ps
CPU time 15.74 seconds
Started May 23 02:29:50 PM PDT 24
Finished May 23 02:30:06 PM PDT 24
Peak memory 248764 kb
Host smart-faf8d05d-7a0a-42bd-8aaa-1f668a06f8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
32903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1377032903
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1666539022
Short name T592
Test name
Test status
Simulation time 83298183 ps
CPU time 6.63 seconds
Started May 23 02:29:51 PM PDT 24
Finished May 23 02:29:58 PM PDT 24
Peak memory 248800 kb
Host smart-9037ebd2-5b40-4449-bb8b-a28a0080e0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665
39022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1666539022
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4155023412
Short name T312
Test name
Test status
Simulation time 119304167497 ps
CPU time 1823.64 seconds
Started May 23 02:30:04 PM PDT 24
Finished May 23 03:00:28 PM PDT 24
Peak memory 305896 kb
Host smart-f8c23ffc-24dc-4d57-aee0-998f437950f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155023412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4155023412
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1481682355
Short name T204
Test name
Test status
Simulation time 110937113438 ps
CPU time 9470.89 seconds
Started May 23 02:30:04 PM PDT 24
Finished May 23 05:07:57 PM PDT 24
Peak memory 370628 kb
Host smart-22df6195-2058-4126-8d55-24a348c42933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481682355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1481682355
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1349219646
Short name T240
Test name
Test status
Simulation time 59039996 ps
CPU time 2.99 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:30:20 PM PDT 24
Peak memory 248912 kb
Host smart-e2d788c4-1999-4eaa-b9ce-7642290a509d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1349219646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1349219646
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3703886441
Short name T589
Test name
Test status
Simulation time 20978180518 ps
CPU time 1275.04 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:51:32 PM PDT 24
Peak memory 287404 kb
Host smart-9d8e8f6b-173e-4e65-8257-83ad3312a4c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703886441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3703886441
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1185354137
Short name T385
Test name
Test status
Simulation time 1053997536 ps
CPU time 24.14 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:30:40 PM PDT 24
Peak memory 248784 kb
Host smart-aa036814-fbe9-4cad-98ab-a64967778f23
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1185354137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1185354137
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1377060489
Short name T563
Test name
Test status
Simulation time 659455140 ps
CPU time 38.84 seconds
Started May 23 02:30:04 PM PDT 24
Finished May 23 02:30:43 PM PDT 24
Peak memory 248932 kb
Host smart-569a393f-7b44-4d1d-a893-fd0c2a9684cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
60489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1377060489
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.234646862
Short name T668
Test name
Test status
Simulation time 45204647 ps
CPU time 4.44 seconds
Started May 23 02:30:02 PM PDT 24
Finished May 23 02:30:07 PM PDT 24
Peak memory 240588 kb
Host smart-da373255-2895-466c-8ce1-f24f30d26c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23464
6862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.234646862
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2863723530
Short name T305
Test name
Test status
Simulation time 19169177521 ps
CPU time 1796.59 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 03:00:14 PM PDT 24
Peak memory 288764 kb
Host smart-e37f1fd7-c93c-4402-ae09-11d552c4dcaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863723530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2863723530
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1148130757
Short name T569
Test name
Test status
Simulation time 12655635026 ps
CPU time 1413.73 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:53:51 PM PDT 24
Peak memory 281204 kb
Host smart-843d4f58-8ca1-4157-9669-1cfa3aa7808b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148130757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1148130757
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3656181846
Short name T337
Test name
Test status
Simulation time 40505767195 ps
CPU time 429.83 seconds
Started May 23 02:30:17 PM PDT 24
Finished May 23 02:37:27 PM PDT 24
Peak memory 248296 kb
Host smart-e79d0047-f50b-4965-a6c6-ff833fce7e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656181846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3656181846
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3572542237
Short name T397
Test name
Test status
Simulation time 1448658198 ps
CPU time 40.78 seconds
Started May 23 02:30:03 PM PDT 24
Finished May 23 02:30:44 PM PDT 24
Peak memory 248760 kb
Host smart-b9aa8475-4825-440a-84ec-455786869c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35725
42237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3572542237
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3319811222
Short name T697
Test name
Test status
Simulation time 220596804 ps
CPU time 15.62 seconds
Started May 23 02:30:03 PM PDT 24
Finished May 23 02:30:19 PM PDT 24
Peak memory 253972 kb
Host smart-e70646a7-d462-4d36-8b6b-988b786134cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
11222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3319811222
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3887600596
Short name T392
Test name
Test status
Simulation time 785300919 ps
CPU time 12.64 seconds
Started May 23 02:30:02 PM PDT 24
Finished May 23 02:30:16 PM PDT 24
Peak memory 248776 kb
Host smart-265c5b01-fde5-438a-b8f8-4c751b35b36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
00596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3887600596
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3565720547
Short name T284
Test name
Test status
Simulation time 5353748026 ps
CPU time 339.44 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:35:57 PM PDT 24
Peak memory 256980 kb
Host smart-551a9d44-0dba-4e75-ab10-57d1ebf4752b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565720547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3565720547
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.334241183
Short name T102
Test name
Test status
Simulation time 272850007910 ps
CPU time 6551.51 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 04:19:29 PM PDT 24
Peak memory 371180 kb
Host smart-f5f4022f-9a7a-404c-ad3b-fed96f7c508e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334241183 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.334241183
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.586943932
Short name T248
Test name
Test status
Simulation time 40958655 ps
CPU time 2.44 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:30:31 PM PDT 24
Peak memory 248936 kb
Host smart-50ed22d4-51b5-4d3e-886a-e82ae8820319
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=586943932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.586943932
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.869961874
Short name T586
Test name
Test status
Simulation time 165487174693 ps
CPU time 1988.93 seconds
Started May 23 02:30:28 PM PDT 24
Finished May 23 03:03:38 PM PDT 24
Peak memory 273456 kb
Host smart-28a70b2a-4027-488a-addd-5fd23783fca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869961874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.869961874
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.852920169
Short name T229
Test name
Test status
Simulation time 2669041954 ps
CPU time 28.87 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:30:56 PM PDT 24
Peak memory 240600 kb
Host smart-62cf4222-e087-4e0e-ae03-451f28e4a43f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=852920169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.852920169
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.614999838
Short name T206
Test name
Test status
Simulation time 827125433 ps
CPU time 70.8 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:31:39 PM PDT 24
Peak memory 248748 kb
Host smart-f08f3018-887b-451b-afe2-0a680ca2e32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61499
9838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.614999838
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2768424114
Short name T633
Test name
Test status
Simulation time 181597929 ps
CPU time 16.29 seconds
Started May 23 02:30:29 PM PDT 24
Finished May 23 02:30:46 PM PDT 24
Peak memory 254940 kb
Host smart-e58794a8-fe21-415d-8387-25d213787c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
24114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2768424114
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2938449865
Short name T38
Test name
Test status
Simulation time 80709806371 ps
CPU time 2798.71 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 03:17:07 PM PDT 24
Peak memory 289428 kb
Host smart-644b1207-8aed-4d72-a15e-751832cd0655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938449865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2938449865
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2067373874
Short name T674
Test name
Test status
Simulation time 15253819781 ps
CPU time 615.71 seconds
Started May 23 02:30:28 PM PDT 24
Finished May 23 02:40:45 PM PDT 24
Peak memory 248344 kb
Host smart-3ddd32b4-6119-4258-adf5-0ddf3753d971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067373874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2067373874
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3509662245
Short name T501
Test name
Test status
Simulation time 733624345 ps
CPU time 22.37 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:30:40 PM PDT 24
Peak memory 248780 kb
Host smart-01e182df-1647-4201-9920-14061dc2a012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
62245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3509662245
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.694480306
Short name T486
Test name
Test status
Simulation time 1122736475 ps
CPU time 10.87 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:30:39 PM PDT 24
Peak memory 254104 kb
Host smart-1a64dd1d-dd7f-4b56-a390-45273e5dc509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69448
0306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.694480306
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.483704620
Short name T278
Test name
Test status
Simulation time 968728571 ps
CPU time 39.84 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:31:07 PM PDT 24
Peak memory 256068 kb
Host smart-466fc51e-0fef-4d19-bae7-0e816966cab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48370
4620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.483704620
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4293328261
Short name T687
Test name
Test status
Simulation time 1603504827 ps
CPU time 22.25 seconds
Started May 23 02:30:16 PM PDT 24
Finished May 23 02:30:39 PM PDT 24
Peak memory 256280 kb
Host smart-38c4c049-3187-40cf-aff5-b11e3763291f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42933
28261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4293328261
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.790167798
Short name T317
Test name
Test status
Simulation time 37409492749 ps
CPU time 2121.61 seconds
Started May 23 02:30:29 PM PDT 24
Finished May 23 03:05:51 PM PDT 24
Peak memory 273324 kb
Host smart-951e89c8-e45e-4f6f-a7e7-e9cb5f344c4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790167798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.790167798
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.791136659
Short name T244
Test name
Test status
Simulation time 16790833 ps
CPU time 2.76 seconds
Started May 23 02:30:40 PM PDT 24
Finished May 23 02:30:43 PM PDT 24
Peak memory 248948 kb
Host smart-77f3176e-8f24-44e7-a4f6-e4aa41a10696
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=791136659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.791136659
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.579464725
Short name T696
Test name
Test status
Simulation time 44054399656 ps
CPU time 2513.25 seconds
Started May 23 02:30:39 PM PDT 24
Finished May 23 03:12:33 PM PDT 24
Peak memory 288708 kb
Host smart-0cf7c1a6-f14e-4521-908e-f8dce8be5d7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579464725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.579464725
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1636293629
Short name T642
Test name
Test status
Simulation time 1072321553 ps
CPU time 12.88 seconds
Started May 23 02:30:40 PM PDT 24
Finished May 23 02:30:54 PM PDT 24
Peak memory 248792 kb
Host smart-cfabbd0d-acfd-4573-8d97-9555d2a8debf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1636293629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1636293629
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3736858945
Short name T388
Test name
Test status
Simulation time 24195399316 ps
CPU time 333.78 seconds
Started May 23 02:30:40 PM PDT 24
Finished May 23 02:36:15 PM PDT 24
Peak memory 256960 kb
Host smart-957955ba-6509-4d14-a28c-e1e45db1afa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
58945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3736858945
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2938910972
Short name T225
Test name
Test status
Simulation time 442482156 ps
CPU time 35.04 seconds
Started May 23 02:30:40 PM PDT 24
Finished May 23 02:31:16 PM PDT 24
Peak memory 255892 kb
Host smart-fc8f2658-b5a6-44e2-9a09-60d8ca48d4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
10972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2938910972
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.657321375
Short name T615
Test name
Test status
Simulation time 33898675679 ps
CPU time 2042.76 seconds
Started May 23 02:30:41 PM PDT 24
Finished May 23 03:04:45 PM PDT 24
Peak memory 285984 kb
Host smart-20bcad60-3012-4562-9606-08996e937fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657321375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.657321375
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.61294492
Short name T471
Test name
Test status
Simulation time 162028912613 ps
CPU time 2737.53 seconds
Started May 23 02:30:38 PM PDT 24
Finished May 23 03:16:17 PM PDT 24
Peak memory 288992 kb
Host smart-20368f27-642e-40d0-89bc-a0960cc89c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61294492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.61294492
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1791893788
Short name T265
Test name
Test status
Simulation time 197336718359 ps
CPU time 446.38 seconds
Started May 23 02:30:39 PM PDT 24
Finished May 23 02:38:07 PM PDT 24
Peak memory 247960 kb
Host smart-709a4f2b-8ca0-432a-b236-3ab0016be1a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791893788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1791893788
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3961730949
Short name T296
Test name
Test status
Simulation time 1103050963 ps
CPU time 35.12 seconds
Started May 23 02:30:27 PM PDT 24
Finished May 23 02:31:03 PM PDT 24
Peak memory 248728 kb
Host smart-011d37bf-7ed4-4c40-a2b3-171cf36312bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
30949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3961730949
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2295244348
Short name T502
Test name
Test status
Simulation time 658815358 ps
CPU time 15.55 seconds
Started May 23 02:30:28 PM PDT 24
Finished May 23 02:30:45 PM PDT 24
Peak memory 253440 kb
Host smart-082f3de2-af2e-483f-8b6d-12d3d22f15db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22952
44348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2295244348
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2340107929
Short name T627
Test name
Test status
Simulation time 562880173 ps
CPU time 19.93 seconds
Started May 23 02:30:40 PM PDT 24
Finished May 23 02:31:01 PM PDT 24
Peak memory 247456 kb
Host smart-ff4982cf-0d42-4ab3-892d-39c2a187ab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401
07929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2340107929
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.543112126
Short name T48
Test name
Test status
Simulation time 34283578 ps
CPU time 3.67 seconds
Started May 23 02:30:28 PM PDT 24
Finished May 23 02:30:32 PM PDT 24
Peak memory 240552 kb
Host smart-0410ef59-5eb4-4fc1-99ee-7125185c59c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54311
2126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.543112126
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3029184
Short name T539
Test name
Test status
Simulation time 75075044136 ps
CPU time 6777.41 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 04:23:51 PM PDT 24
Peak memory 363244 kb
Host smart-8ecf285e-18a3-46d2-afe9-48f544a0fed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029184 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3029184
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2700748990
Short name T243
Test name
Test status
Simulation time 31180104 ps
CPU time 3.11 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:30:56 PM PDT 24
Peak memory 248916 kb
Host smart-60a64d08-e70d-4547-97e5-4bc01a798ef8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2700748990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2700748990
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2217808396
Short name T327
Test name
Test status
Simulation time 45827800341 ps
CPU time 1068.59 seconds
Started May 23 02:30:51 PM PDT 24
Finished May 23 02:48:41 PM PDT 24
Peak memory 273060 kb
Host smart-d07af1ed-748d-4436-a3f9-f0789c02c324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217808396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2217808396
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3648236425
Short name T452
Test name
Test status
Simulation time 9500628313 ps
CPU time 53.8 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:31:47 PM PDT 24
Peak memory 248868 kb
Host smart-12dccbd2-f738-4c7a-aeb7-c90024af6b0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3648236425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3648236425
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.519641944
Short name T651
Test name
Test status
Simulation time 742515734 ps
CPU time 68.39 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:32:01 PM PDT 24
Peak memory 256636 kb
Host smart-f850eae8-d9d2-4574-948c-6a13f7bcd95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51964
1944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.519641944
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3610980350
Short name T309
Test name
Test status
Simulation time 295214110 ps
CPU time 29.97 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:31:22 PM PDT 24
Peak memory 255952 kb
Host smart-4434f15d-f00c-43d4-9586-bd39e9ebdeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
80350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3610980350
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2655250931
Short name T365
Test name
Test status
Simulation time 45368810094 ps
CPU time 2623.71 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 03:14:37 PM PDT 24
Peak memory 281592 kb
Host smart-121fddaa-09b6-4fb2-9338-0819fe9127fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655250931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2655250931
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2635467773
Short name T135
Test name
Test status
Simulation time 62739938811 ps
CPU time 2140.96 seconds
Started May 23 02:30:51 PM PDT 24
Finished May 23 03:06:33 PM PDT 24
Peak memory 284456 kb
Host smart-d01eb796-a3a6-4e28-818c-78554c1bc38c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635467773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2635467773
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1094316026
Short name T342
Test name
Test status
Simulation time 8236318827 ps
CPU time 160.88 seconds
Started May 23 02:30:53 PM PDT 24
Finished May 23 02:33:34 PM PDT 24
Peak memory 248212 kb
Host smart-5b4239cc-f273-447c-92da-54a1e5160226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094316026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1094316026
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2421942514
Short name T82
Test name
Test status
Simulation time 892389035 ps
CPU time 28.58 seconds
Started May 23 02:30:52 PM PDT 24
Finished May 23 02:31:21 PM PDT 24
Peak memory 255052 kb
Host smart-144ef254-f680-4034-903e-ed65cd122b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219
42514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2421942514
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3026537175
Short name T73
Test name
Test status
Simulation time 4131230667 ps
CPU time 45.21 seconds
Started May 23 02:30:51 PM PDT 24
Finished May 23 02:31:37 PM PDT 24
Peak memory 248812 kb
Host smart-b143d193-6185-4366-9be3-8edfb97acbef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
37175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3026537175
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1106601289
Short name T413
Test name
Test status
Simulation time 121368226 ps
CPU time 14.56 seconds
Started May 23 02:30:51 PM PDT 24
Finished May 23 02:31:06 PM PDT 24
Peak memory 255772 kb
Host smart-078badc0-68bc-45fd-a499-a40edf826baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11066
01289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1106601289
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2778657440
Short name T400
Test name
Test status
Simulation time 1095729049 ps
CPU time 36.03 seconds
Started May 23 02:30:51 PM PDT 24
Finished May 23 02:31:28 PM PDT 24
Peak memory 248692 kb
Host smart-02590d7a-b8d9-42c2-a91d-60a51face000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
57440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2778657440
Directory /workspace/9.alert_handler_smoke/latest
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